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Tue, 6 Jan 2026 20:24:45 -0800 From: Kartik Rajput To: , , , , , , , , , CC: Kartik Rajput Subject: [PATCH v4 2/4] i2c: tegra: Move variant to tegra_i2c_hw_feature Date: Wed, 7 Jan 2026 09:54:32 +0530 Message-ID: <20260107042434.10587-3-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260107042434.10587-1-kkartik@nvidia.com> References: <20260107042434.10587-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000F:EE_|BN7PPF9E4583E15:EE_ X-MS-Office365-Filtering-Correlation-Id: 728a0a04-22a6-4f98-b4c7-08de4da4b7b6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?o5j/iFUApeziOnUTVGLq8Bl2v5vtxdrqVuukztPJFlrfeQ4zOtmQ0DnXNG9Q?= =?us-ascii?Q?aU1X4h302IEXz0TGMbNkQ/jNLcKMkuIjakGObKMlEpGJALzFWWwYpDblHL6M?= =?us-ascii?Q?Lz9gbDocbOoag7sJIgR+MaeW1xYraNwKKIMHaGyrjUX6I0HpNN1fuDa4SFci?= =?us-ascii?Q?zrhSiGITeYHjXTF25/Z0j66SxUPvlxRJgLSRbTLYsAKUzbhEDMdDFl5k7NAp?= =?us-ascii?Q?ysVgarvMUpWnJPx2x0GASym65mFmRk6cD07CreeZ8XeYU6XzgPlObfrrpzaf?= =?us-ascii?Q?HqzJ3Mm+dz5KnL9A6pZS6juOVWZrUJMQZ4+AXR/FmNhx+gLkZLkf3NZ2d7zV?= =?us-ascii?Q?ivuEkq9SlrUZuApAk8Fl99xEha/cl/dskWov+d6qWLa0WJlUl31tpBDexr67?= =?us-ascii?Q?2JI3yA+u7tzOgnEJwCpYzEnHoqcd08Y6tEvV+VtB6gzsVfHmTqNp+zjx+Sfl?= =?us-ascii?Q?y/KbOErOPABiHLFGgIfxwW3P2hG9+VYh/3qst6Dci5hjN+m6ibH39Ma5zKjI?= =?us-ascii?Q?yzDmYwLKBSb4eAQMHO5tx5Dy4kiynRcYNtcZ6x79S907wL+7QhXd8Zwo7xQi?= =?us-ascii?Q?BGy1R7mez7+hbusYYqn/JutQtSxIAR8PPli8h5EweR1UGcHt/BZAOZcdojib?= =?us-ascii?Q?fdOsKN7DD+aGd3n1eER95oD3UVAgQ5jmtQPm8o7ODLNbNusXdiE5h1LFyGn7?= =?us-ascii?Q?uUJAp1hguvXFINu1vgZ9Nzx0KaOaLnshq1LjyvkQ1gM9xYQunwsiUbXTPhWz?= =?us-ascii?Q?0qqc1GQDoTQhAxp4e+Qd1NZLA4z0mTuh9VyNr4lgohx4VTf/teJnhdpA8xjI?= =?us-ascii?Q?Nh2MO83ETIvElkAptk5qDgElGBd06LHCUB2Dy+4qvx94xMxNYsV7ymg4HOLC?= =?us-ascii?Q?O1SeN+bSczkTO0WCrFrD7EvaGvnqOKLI2KQuuRBCAUbLZ8iCZa7HcSDJhvfg?= =?us-ascii?Q?DVup9a+qO2JTKuTtdp1Y9+awnGxHZkptIacC+cSzO65rDUMtt99Z8xw6ZcwV?= =?us-ascii?Q?TcQObwAr/fKo7/8ZCXvaUUtl35bCh/xlzRkmNpboD/Ulxr8LxP8DYfsGNZwb?= =?us-ascii?Q?M5tdOr0Map2ghO7NlgSxKJ4YcVGMmRUCkLVJTthGsLNNe/AwscwrCrhyyA/N?= =?us-ascii?Q?Y8iYoXXoeJeXuGQPG5VZbekd+abgqzf1JSvU64oRHapLNLnWsaNPdtT95+WI?= =?us-ascii?Q?QxwlexX35sAHmg3Kd4e65BjWLRGDUuu3QMZve2ORTs3UAagHZZjZ8L3OOE4M?= =?us-ascii?Q?ArFXj7PCePN8UOsfmwHs0L4YZdNnGOoW3uzlvSb2xMyhkrk+uGYpev2vJtLM?= =?us-ascii?Q?Avd17YFxtBb+5AvXipZViun6ZqrMAd9mIVtGtDHvRYVyUhnqT64vSFUaeyAJ?= =?us-ascii?Q?KgsPmkXhQzH7PoBPf0z0jQGyAj4CNbtV0+0r4JR4N5JB8V0bD3TuN/ED0lBn?= =?us-ascii?Q?1HVfYmcEFWx7JhaDwZdMAxQiYRG2lnsltASCsanLcO5nqgIbaMviFxLvrQCo?= =?us-ascii?Q?hjLr/gghQIeDPPfCgWpXxbFiLSWuGXoxs2Mz2gC3B5ZFyZ/OiA4pybqCxG6b?= =?us-ascii?Q?RlAK05KlpQKXkpxORfn8XqTzJwB+cg+7g9dij0RG?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jan 2026 04:24:58.3951 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 728a0a04-22a6-4f98-b4c7-08de4da4b7b6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPF9E4583E15 Content-Type: text/plain; charset="utf-8" Move the variant field into tegra_i2c_hw_feature and populate it for all SoCs. Add dedicated SoC data for "nvidia,tegra20-i2c-dvc" and "nvidia,tegra210-i2c-vi" compatibles. Drop the compatible-string checks from tegra_i2c_parse_dt to initialize the Tegra I2C variant. Also remove the redundant config checks from IS_VI and IS_DVC macros. Signed-off-by: Kartik Rajput --- Changes in v4: * Reverted the change to remove config checks from IS_DVC and IS_VI macros. --- drivers/i2c/busses/i2c-tegra.c | 98 ++++++++++++++++++++++++++++------ 1 file changed, 81 insertions(+), 17 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 9a09079dcc9c..cb6455fb3ee1 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -235,6 +235,7 @@ enum tegra_i2c_variant { * timing settings. * @enable_hs_mode_support: Enable support for high speed (HS) mode transf= ers. * @has_mutex: Has mutex register for mutual exclusion with other firmware= s or VMs. + * @variant: This represents the I2C controller variant. */ struct tegra_i2c_hw_feature { bool has_continue_xfer_support; @@ -266,6 +267,7 @@ struct tegra_i2c_hw_feature { bool has_interface_timing_reg; bool enable_hs_mode_support; bool has_mutex; + enum tegra_i2c_variant variant; }; =20 /** @@ -281,7 +283,6 @@ struct tegra_i2c_hw_feature { * @base_phys: physical base address of the I2C controller * @cont_id: I2C controller ID, used for packet header * @irq: IRQ number of transfer complete interrupt - * @variant: This represents the I2C controller variant. * @msg_complete: transfer completion notifier * @msg_buf_remaining: size of unsent data in the message buffer * @msg_len: length of message in current transfer @@ -334,13 +335,12 @@ struct tegra_i2c_dev { bool atomic_mode; bool dma_mode; bool msg_read; - enum tegra_i2c_variant variant; }; =20 #define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && \ - (dev)->variant =3D=3D TEGRA_I2C_VARIANT_DVC) + (dev)->hw->variant =3D=3D TEGRA_I2C_VARIANT_DVC) #define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && \ - (dev)->variant =3D=3D TEGRA_I2C_VARIANT_VI) + (dev)->hw->variant =3D=3D TEGRA_I2C_VARIANT_VI) =20 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg) @@ -1649,8 +1649,42 @@ static const struct tegra_i2c_hw_feature tegra20_i2c= _hw =3D { .has_interface_timing_reg =3D false, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 +#if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) +static const struct tegra_i2c_hw_feature tegra20_dvc_i2c_hw =3D { + .has_continue_xfer_support =3D false, + .has_per_pkt_xfer_complete_irq =3D false, + .clk_divisor_hs_mode =3D 3, + .clk_divisor_std_mode =3D 0, + .clk_divisor_fast_mode =3D 0, + .clk_divisor_fast_plus_mode =3D 0, + .has_config_load_reg =3D false, + .has_multi_master_mode =3D false, + .has_slcg_override_reg =3D false, + .has_mst_fifo =3D false, + .has_mst_reset =3D false, + .quirks =3D &tegra_i2c_quirks, + .supports_bus_clear =3D false, + .has_apb_dma =3D true, + .tlow_std_mode =3D 0x4, + .thigh_std_mode =3D 0x2, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x2, + .setup_hold_time_std_mode =3D 0x0, + .setup_hold_time_fast_mode =3D 0x0, + .setup_hold_time_fastplus_mode =3D 0x0, + .setup_hold_time_hs_mode =3D 0x0, + .has_interface_timing_reg =3D false, + .enable_hs_mode_support =3D false, + .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DVC, +}; +#endif + static const struct tegra_i2c_hw_feature tegra30_i2c_hw =3D { .has_continue_xfer_support =3D true, .has_per_pkt_xfer_complete_irq =3D false, @@ -1679,6 +1713,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_= hw =3D { .has_interface_timing_reg =3D false, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra114_i2c_hw =3D { @@ -1709,6 +1744,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c= _hw =3D { .has_interface_timing_reg =3D false, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra124_i2c_hw =3D { @@ -1739,6 +1775,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra210_i2c_hw =3D { @@ -1769,8 +1806,42 @@ static const struct tegra_i2c_hw_feature tegra210_i2= c_hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 +#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) +static const struct tegra_i2c_hw_feature tegra210_vi_i2c_hw =3D { + .has_continue_xfer_support =3D true, + .has_per_pkt_xfer_complete_irq =3D true, + .clk_divisor_hs_mode =3D 1, + .clk_divisor_std_mode =3D 0x19, + .clk_divisor_fast_mode =3D 0x19, + .clk_divisor_fast_plus_mode =3D 0x10, + .has_config_load_reg =3D true, + .has_multi_master_mode =3D false, + .has_slcg_override_reg =3D true, + .has_mst_fifo =3D false, + .has_mst_reset =3D false, + .quirks =3D &tegra_i2c_quirks, + .supports_bus_clear =3D true, + .has_apb_dma =3D true, + .tlow_std_mode =3D 0x4, + .thigh_std_mode =3D 0x2, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x2, + .setup_hold_time_std_mode =3D 0, + .setup_hold_time_fast_mode =3D 0, + .setup_hold_time_fastplus_mode =3D 0, + .setup_hold_time_hs_mode =3D 0, + .has_interface_timing_reg =3D true, + .enable_hs_mode_support =3D false, + .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_VI, +}; +#endif + static const struct tegra_i2c_hw_feature tegra186_i2c_hw =3D { .has_continue_xfer_support =3D true, .has_per_pkt_xfer_complete_irq =3D true, @@ -1799,6 +1870,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra194_i2c_hw =3D { @@ -1831,6 +1903,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D true, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra256_i2c_hw =3D { @@ -1863,6 +1936,7 @@ static const struct tegra_i2c_hw_feature tegra256_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D true, .has_mutex =3D true, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra264_i2c_hw =3D { @@ -1895,6 +1969,7 @@ static const struct tegra_i2c_hw_feature tegra264_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D true, .has_mutex =3D true, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct of_device_id tegra_i2c_of_match[] =3D { @@ -1903,7 +1978,7 @@ static const struct of_device_id tegra_i2c_of_match[]= =3D { { .compatible =3D "nvidia,tegra194-i2c", .data =3D &tegra194_i2c_hw, }, { .compatible =3D "nvidia,tegra186-i2c", .data =3D &tegra186_i2c_hw, }, #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) - { .compatible =3D "nvidia,tegra210-i2c-vi", .data =3D &tegra210_i2c_hw, }, + { .compatible =3D "nvidia,tegra210-i2c-vi", .data =3D &tegra210_vi_i2c_hw= , }, #endif { .compatible =3D "nvidia,tegra210-i2c", .data =3D &tegra210_i2c_hw, }, { .compatible =3D "nvidia,tegra124-i2c", .data =3D &tegra124_i2c_hw, }, @@ -1911,7 +1986,7 @@ static const struct of_device_id tegra_i2c_of_match[]= =3D { { .compatible =3D "nvidia,tegra30-i2c", .data =3D &tegra30_i2c_hw, }, { .compatible =3D "nvidia,tegra20-i2c", .data =3D &tegra20_i2c_hw, }, #if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) - { .compatible =3D "nvidia,tegra20-i2c-dvc", .data =3D &tegra20_i2c_hw, }, + { .compatible =3D "nvidia,tegra20-i2c-dvc", .data =3D &tegra20_dvc_i2c_hw= , }, #endif {}, }; @@ -1919,23 +1994,12 @@ MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); =20 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) { - struct device_node *np =3D i2c_dev->dev->of_node; bool multi_mode; =20 i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true); =20 multi_mode =3D device_property_read_bool(i2c_dev->dev, "multi-master"); i2c_dev->multimaster_mode =3D multi_mode; - - i2c_dev->variant =3D TEGRA_I2C_VARIANT_DEFAULT; - - if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && - of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc")) - i2c_dev->variant =3D TEGRA_I2C_VARIANT_DVC; - - if (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && - of_device_is_compatible(np, "nvidia,tegra210-i2c-vi")) - i2c_dev->variant =3D TEGRA_I2C_VARIANT_VI; } =20 static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev) --=20 2.43.0