From nobody Sun Feb 8 10:30:19 2026 Received: from raptorengineering.com (mail.raptorengineering.com [23.155.224.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C8011D9346; Wed, 7 Jan 2026 00:29:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=23.155.224.40 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767745790; cv=none; b=TGpO/slFGPdrkQnlYQBuQBznhZBXJa86E1Pks/4+pwaTOQaJ+3fgzoabcDc5xWspEIz3CVS5WvMo2G2JGqinczgi9hAZ8LYfp+GxD9mzmKMbzcf/z4VWQKnSdXrMiAtM5sygjzIKVCrB8JpIWVhhCn/btUp6rIk42zCOq6dNVeY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767745790; c=relaxed/simple; bh=IGPIfpZGR/46Q4/1e4C1wzl43JL0eBSE58oALqFxTFw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WUtUET9W0hd7TVVvtF3uIBGhZrSueZOWtLDt0zmW9GHlt10nThJHDFj/whR96OodBTNGOVC9nWjtDBfKVMATW51neaZX3CPSMT2AlFZZhzZrkcC2877Gi2uck65h8o7LGK4TOE7N/T7LQhnRG4TUZGc47jrvxv/9wNZvskkWV7M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=raptorengineering.com; spf=pass smtp.mailfrom=raptorengineering.com; dkim=pass (1024-bit key) header.d=raptorengineering.com header.i=@raptorengineering.com header.b=tS8Fa60k; arc=none smtp.client-ip=23.155.224.40 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=raptorengineering.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=raptorengineering.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=raptorengineering.com header.i=@raptorengineering.com header.b="tS8Fa60k" Received: from localhost (localhost [127.0.0.1]) by mail.rptsys.com (Postfix) with ESMTP id E953F7790EFD; Tue, 6 Jan 2026 18:21:46 -0600 (CST) Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id rAgBSP4LZbUf; Tue, 6 Jan 2026 18:21:46 -0600 (CST) Received: from localhost (localhost [127.0.0.1]) by mail.rptsys.com (Postfix) with ESMTP id 1F5047790ECC; Tue, 6 Jan 2026 18:21:46 -0600 (CST) DKIM-Filter: OpenDKIM Filter v2.10.3 mail.rptsys.com 1F5047790ECC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=raptorengineering.com; s=B8E824E6-0BE2-11E6-931D-288C65937AAD; t=1767745306; bh=VM/Z9aNZ88exD7vwy9/smksPXM7Jr7QK6Agvj8TutWs=; h=From:To:Date:Message-Id:MIME-Version; b=tS8Fa60k7DqQ+2+TWjA17kKzio/toQR/5yh+Cz99ObMm71rSi5KojljRBDaz8i7fT umoWN0dql9ar4PeZtNdZt73rZ+jC6ncSXIos9jQFZfVa0rIVBQVatRu9Qo7j8kYBxG MPln32gPSz9R1EZmaw/sJdMB1uI2hlaXEoaEQgKo= X-Virus-Scanned: amavisd-new at rptsys.com Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id SfMBqXPBWQBc; Tue, 6 Jan 2026 18:21:46 -0600 (CST) Received: from rcs-ewks-005.starlink.edu (unknown [192.168.20.42]) by mail.rptsys.com (Postfix) with ESMTPSA id EA6F97790ECB; Tue, 6 Jan 2026 18:21:45 -0600 (CST) From: Timothy Pearson To: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, robh+dt@kernel.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, Georgy.Yakovlev@sony.com, sanastasio@raptorengineering.com, Timothy Pearson Subject: [PATCH v6 1/4] dt-bindings: mfd: Add sony,cronos-smc Date: Tue, 6 Jan 2026 18:21:33 -0600 Message-Id: <20260107002136.3121607-2-tpearson@raptorengineering.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260107002136.3121607-1-tpearson@raptorengineering.com> References: <20260107002136.3121607-1-tpearson@raptorengineering.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Shawn Anastasio The Sony Cronos Platform Controller is a multi-purpose platform controller that provides both a watchdog timer and an LED controller for the Sony Interactive Entertainment Cronos x86 server platform. As both functions are provided by the same CPLD, a multi-function device is exposed as the parent of both functions. Add a DT binding for this device. Signed-off-by: Shawn Anastasio Signed-off-by: Timothy Pearson --- .../bindings/mfd/sony,cronos-smc.yaml | 128 ++++++++++++++++++ 1 file changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/sony,cronos-smc.y= aml diff --git a/Documentation/devicetree/bindings/mfd/sony,cronos-smc.yaml b/D= ocumentation/devicetree/bindings/mfd/sony,cronos-smc.yaml new file mode 100644 index 000000000000..34ccd27e2996 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/sony,cronos-smc.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2025-2026 Raptor Engineering, LLC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/sony,cronos-smc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sony Cronos Platform Controller CPLD multi-function device + +maintainers: + - Georgy Yakovlev + +description: + The Sony Cronos Platform Controller CPLD is a multi-purpose platform + controller that provides both a watchdog timer and an LED controller for= the + Sony Interactive Entertainment Cronos x86 server platform. As both funct= ions + are provided by the same CPLD, a multi-function device is exposed as the + parent of both functions. + +properties: + compatible: + const: sony,cronos-smc + + reg: + maxItems: 1 + + leds: + type: object + $ref: /schemas/leds/common.yaml# + additionalProperties: false + description: | + The Cronos LED controller is a subfunction of the Cronos platform + controller, which is a multi-function device. + + Each led is represented as a child node of sony,cronos-led. Fifteen = RGB + LEDs are supported by the platform. + + properties: + compatible: + const: sony,cronos-led + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^multi-led@[0-9a-f]$": + type: object + $ref: /schemas/leds/leds-class-multicolor.yaml# + unevaluatedProperties: false + + properties: + reg: + description: + LED channel number (0..14) + minimum: 0 + maximum: 14 + + required: + - reg + + required: + - compatible + - "#address-cells" + - "#size-cells" + + watchdog: + type: object + + $ref: /schemas/watchdog/watchdog.yaml + + properties: + compatible: + const: sony,cronos-watchdog + + timeout-sec: true + + required: + - compatible + + additionalProperties: false + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + smc@3f { + compatible =3D "sony,cronos-smc"; + reg =3D <0x3f>; + + timeout-sec =3D <20>; + + watchdog { + compatible =3D "sony,cronos-watchdog"; + }; + + leds { + compatible =3D "sony,cronos-led"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + multi-led@0 { + /* + * No subnodes are needed, this controller only suppor= ts RGB + * LEDs. + */ + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_STATUS; + }; + }; + }; + }; + --=20 2.39.5 From nobody Sun Feb 8 10:30:19 2026 Received: from raptorengineering.com (mail.raptorengineering.com [23.155.224.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E83E1DB125; Wed, 7 Jan 2026 00:29:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=23.155.224.40 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767745790; cv=none; b=sYhzV8s+FkH+mN8fi6msy3l/eOM3FAobHXAG3Ut/U7Dh/JH2WyK4Gdnq3qAqwZ8GtLminZDoxo4BBIulL6s+Iq2D0/H0q5DwBusj7W8GewOJ1syBRrWGLaQW99jiMmn5Wj2ZCLjDimsBWNRZCqmXBJlL8X/63/oRJ9M0vF7fWz4= ARC-Message-Signature: i=1; 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Tue, 6 Jan 2026 18:21:46 -0600 (CST) Received: from rcs-ewks-005.starlink.edu (unknown [192.168.20.42]) by mail.rptsys.com (Postfix) with ESMTPSA id B61F57790ECB; Tue, 6 Jan 2026 18:21:46 -0600 (CST) From: Timothy Pearson To: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, robh+dt@kernel.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, Georgy.Yakovlev@sony.com, sanastasio@raptorengineering.com, Timothy Pearson Subject: [PATCH v6 2/4] mfd: sony-cronos-smc: Add driver for Sony Cronos SMC Date: Tue, 6 Jan 2026 18:21:34 -0600 Message-Id: <20260107002136.3121607-3-tpearson@raptorengineering.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260107002136.3121607-1-tpearson@raptorengineering.com> References: <20260107002136.3121607-1-tpearson@raptorengineering.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Sony Cronos Platform Controller is a multi-purpose platform controller that provides both a watchdog timer and an LED controller for the Sony Interactive Entertainment Cronos x86 server platform. As both functions are provided by the same CPLD, a multi-function device is exposed as the parent of both functions. Signed-off-by: Timothy Pearson Signed-off-by: Shawn Anastasio --- MAINTAINERS | 7 ++ drivers/mfd/Kconfig | 11 ++ drivers/mfd/Makefile | 2 + drivers/mfd/sony-cronos-smc.c | 212 ++++++++++++++++++++++++++++++++ include/linux/mfd/sony-cronos.h | 61 +++++++++ 5 files changed, 293 insertions(+) create mode 100644 drivers/mfd/sony-cronos-smc.c create mode 100644 include/linux/mfd/sony-cronos.h diff --git a/MAINTAINERS b/MAINTAINERS index a0dd762f5648..b5860a5dd7d7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -24281,6 +24281,13 @@ S: Maintained F: drivers/ssb/ F: include/linux/ssb/ =20 +SONY CRONOS SMC DRIVER +M: Georgy Yakovlev +S: Maintained +F: Documentation/devicetree/bindings/mfd/sony,cronos-smc.yaml +F: drivers/mfd/sony-cronos-smc.c +F: include/linux/mfd/sony-cronos.h + SONY IMX208 SENSOR DRIVER M: Sakari Ailus L: linux-media@vger.kernel.org diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index aace5766b38a..559aa64500e6 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2388,6 +2388,17 @@ config MFD_QCOM_PM8008 under it in the device tree. Additional drivers must be enabled in order to use the functionality of the device. =20 +config MFD_SONY_CRONOS_SMC + tristate "Sony Cronos System Management Controller" + select MFD_CORE + select REGMAP_I2C + depends on I2C && OF + help + Support for the Sony Cronos system controller. Additional drivers mu= st + be enabled in order to use the functionality of the device, includin= g LED + control and the system watchdog. The controller itself is a custom d= esign + tailored to the specific needs of the Sony Cronos hardware platform. + menu "Multimedia Capabilities Port drivers" depends on ARCH_SA1100 =20 diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index e75e8045c28a..2e8cf0c7096c 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -301,6 +301,8 @@ obj-$(CONFIG_MFD_QNAP_MCU) +=3D qnap-mcu.o obj-$(CONFIG_MFD_RSMU_I2C) +=3D rsmu_i2c.o rsmu_core.o obj-$(CONFIG_MFD_RSMU_SPI) +=3D rsmu_spi.o rsmu_core.o =20 +obj-$(CONFIG_MFD_SONY_CRONOS_SMC) +=3D sony-cronos-smc.o + obj-$(CONFIG_MFD_UPBOARD_FPGA) +=3D upboard-fpga.o =20 obj-$(CONFIG_MFD_LOONGSON_SE) +=3D loongson-se.o diff --git a/drivers/mfd/sony-cronos-smc.c b/drivers/mfd/sony-cronos-smc.c new file mode 100644 index 000000000000..9d9b5402f89b --- /dev/null +++ b/drivers/mfd/sony-cronos-smc.c @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Device driver for Sony Cronos SMCs + * Copyright (C) 2015-2017 Dialog Semiconductor + * Copyright (C) 2022-2025 Raptor Engineering, LLC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const struct mfd_cell cronos_smc_devs[] =3D { + { + .name =3D "cronos-watchdog", + .of_compatible =3D "sony,cronos-watchdog", + }, + { + .name =3D "cronos-led", + .of_compatible =3D "sony,cronos-led", + }, +}; + +static int sony_cronos_get_device_type(struct sony_cronos_smc *ddata) +{ + int device_id; + int byte_high; + int byte_low; + int ret; + + ret =3D regmap_read(ddata->regmap, CRONOS_SMC_DEVICE_ID_HIGH_REG, &byte_h= igh); + if (ret) { + dev_err(ddata->dev, "Cannot read ddata ID high byte.\n"); + return -EIO; + } + ret =3D regmap_read(ddata->regmap, CRONOS_SMC_DEVICE_ID_LOW_REG, &byte_lo= w); + if (ret) { + dev_err(ddata->dev, "Cannot read ddata ID low byte.\n"); + return -EIO; + } + + device_id =3D byte_high << 8; + device_id |=3D byte_low; + + if (device_id !=3D CRONOS_SMC_DEVICE_ID) { + dev_err(ddata->dev, "Unsupported device ID 0x%04x\n", device_id); + return -ENODEV; + } + + return ret; +} + +static bool cronos_smc_is_writeable_reg(struct device *dev, unsigned int r= eg) +{ + switch (reg) { + case CRONOS_SMC_BRIGHTNESS_RED_REG: + case CRONOS_SMC_BRIGHTNESS_GREEN_REG: + case CRONOS_SMC_BRIGHTNESS_BLUE_REG: + case CRONOS_LEDS_SMC_STATUS_REG: + case CRONOS_LEDS_SWITCH_STATUS_REG: + case CRONOS_LEDS_CCM1_STATUS_REG: + case CRONOS_LEDS_CCM2_STATUS_REG: + case CRONOS_LEDS_CCM3_STATUS_REG: + case CRONOS_LEDS_CCM4_STATUS_REG: + case CRONOS_LEDS_CCM_POWER_REG: + + case CRONOS_WDT_CTL_REG: + case CRONOS_WDT_CLR_REG: + + case CRONOS_SMC_UART_MUX_REG: + case CRONOS_SMC_SWITCH_BOOT_FLASH_SELECT_REG: + case CRONOS_SMC_SWITCH_RESET_CMD_REG: + case CRONOS_SMC_BMC_BOOT_FLASH_SELECT_REG: + case CRONOS_SMC_PAYLOAD_POWER_CTL_REG: + return true; + default: + return false; + } +} + +static bool cronos_smc_is_readable_reg(struct device *dev, unsigned int re= g) +{ + switch (reg) { + case CRONOS_SMC_REVISION_HIGH_REG: + case CRONOS_SMC_REVISION_LOW_REG: + case CRONOS_SMC_DEVICE_ID_HIGH_REG: + case CRONOS_SMC_DEVICE_ID_LOW_REG: + + case CRONOS_SMC_BRIGHTNESS_RED_REG: + case CRONOS_SMC_BRIGHTNESS_GREEN_REG: + case CRONOS_SMC_BRIGHTNESS_BLUE_REG: + case CRONOS_LEDS_SMC_STATUS_REG: + case CRONOS_LEDS_SWITCH_STATUS_REG: + case CRONOS_LEDS_CCM1_STATUS_REG: + case CRONOS_LEDS_CCM2_STATUS_REG: + case CRONOS_LEDS_CCM3_STATUS_REG: + case CRONOS_LEDS_CCM4_STATUS_REG: + case CRONOS_LEDS_CCM_POWER_REG: + + case CRONOS_WDT_CTL_REG: + case CRONOS_WDT_CLR_REG: + + case CRONOS_SMC_STATUS_2_REG: + case CRONOS_SMC_UART_MUX_REG: + case CRONOS_SMC_SWITCH_BOOT_FLASH_SELECT_REG: + case CRONOS_SMC_SWITCH_RESET_CMD_REG: + case CRONOS_SMC_BMC_BOOT_FLASH_SELECT_REG: + case CRONOS_SMC_PAYLOAD_POWER_CTL_REG: + + case CRONOS_SMC_BMC_MAC_LOW_REG ... CRONOS_SMC_BMC_MAC_HIGH_REG: + return true; + default: + return false; + } +} + +static bool cronos_smc_is_volatile_reg(struct device *dev, unsigned int re= g) +{ + switch (reg) { + case CRONOS_SMC_REVISION_HIGH_REG: + case CRONOS_SMC_REVISION_LOW_REG: + + case CRONOS_SMC_SWITCH_BOOT_FLASH_SELECT_REG: + case CRONOS_SMC_SWITCH_RESET_CMD_REG: + case CRONOS_SMC_BMC_BOOT_FLASH_SELECT_REG: + case CRONOS_SMC_PAYLOAD_POWER_CTL_REG: + + case CRONOS_WDT_CTL_REG: + case CRONOS_WDT_CLR_REG: + return true; + default: + return false; + } +} + +static struct regmap_config cronos_smc_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + .max_register =3D CRONOS_SMC_REVISION_HIGH_REG, + .writeable_reg =3D cronos_smc_is_writeable_reg, + .readable_reg =3D cronos_smc_is_readable_reg, + .volatile_reg =3D cronos_smc_is_volatile_reg, + .use_single_read =3D true, + .use_single_write =3D true, + .cache_type =3D REGCACHE_MAPLE, +}; + +static const struct of_device_id cronos_smc_dt_ids[] =3D { + { + .compatible =3D "sony,cronos-smc", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, cronos_smc_dt_ids); + +static int sony_cronos_i2c_probe(struct i2c_client *i2c) +{ + struct sony_cronos_smc *ddata; + int ret; + + ddata =3D devm_kzalloc(&i2c->dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + i2c_set_clientdata(i2c, ddata); + ddata->dev =3D &i2c->dev; + + ddata->regmap =3D devm_regmap_init_i2c(i2c, &cronos_smc_regmap_config); + if (IS_ERR(ddata->regmap)) { + return dev_err_probe(ddata->dev, PTR_ERR(ddata->regmap), + "Failed to allocate register map\n"); + } + + ret =3D sony_cronos_get_device_type(ddata); + if (ret) + return ret; + + ret =3D mfd_add_devices(ddata->dev, PLATFORM_DEVID_AUTO, cronos_smc_devs, + ARRAY_SIZE(cronos_smc_devs), NULL, 0, NULL); + if (ret) { + dev_err(ddata->dev, "Failed to register child devices\n"); + return ret; + } + + return ret; +} + +static void sony_cronos_i2c_remove(struct i2c_client *i2c) +{ + struct sony_cronos_smc *ddata =3D i2c_get_clientdata(i2c); + + mfd_remove_devices(ddata->dev); +} + +static struct i2c_driver sony_cronos_i2c_driver =3D { + .driver =3D { + .name =3D "sony-cronos-smc", + .of_match_table =3D of_match_ptr(cronos_smc_dt_ids), + }, + .probe =3D sony_cronos_i2c_probe, + .remove =3D sony_cronos_i2c_remove, +}; +module_i2c_driver(sony_cronos_i2c_driver); + +MODULE_DESCRIPTION("Device driver for the Sony Cronos system management co= ntroller"); +MODULE_AUTHOR("Raptor Engineering, LLC "); +MODULE_LICENSE("GPL"); \ No newline at end of file diff --git a/include/linux/mfd/sony-cronos.h b/include/linux/mfd/sony-crono= s.h new file mode 100644 index 000000000000..d82e46176bf7 --- /dev/null +++ b/include/linux/mfd/sony-cronos.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2015-2017 Dialog Semiconductor + * Copyright (C) 2022 Raptor Engineering, LLC + */ + +#ifndef __MFD_SONY_CRONOS_H__ +#define __MFD_SONY_CRONOS_H__ + +#define CRONOS_SMC_DEVICE_ID 0x0134 + +#define CRONOS_SMC_SWITCH_BOOT_FLASH_SELECT_REG 0x00 +#define CRONOS_SMC_SWITCH_RESET_CMD_REG 0x01 +#define CRONOS_SMC_BMC_BOOT_FLASH_SELECT_REG 0x02 +#define CRONOS_BMC_RESET_REG 0x03 +#define CRONOS_WDT_CLR_REG 0x03 +#define CRONOS_SMC_STATUS_2_REG 0x05 +#define CRONOS_SMC_PAYLOAD_POWER_CTL_REG 0x0a +#define CRONOS_WDT_CTL_REG 0x0c +#define CRONOS_SMC_UART_MUX_REG 0x0e + +#define CRONOS_SMC_BRIGHTNESS_RED_REG 0x17 +#define CRONOS_SMC_BRIGHTNESS_GREEN_REG 0x18 +#define CRONOS_SMC_BRIGHTNESS_BLUE_REG 0x19 + +#define CRONOS_LEDS_SMC_STATUS_REG 0x10 +#define CRONOS_LEDS_SWITCH_STATUS_REG 0x11 + +#define CRONOS_LEDS_CCM3_STATUS_REG 0x12 +#define CRONOS_LEDS_CCM2_STATUS_REG 0x13 +#define CRONOS_LEDS_CCM4_STATUS_REG 0x14 +#define CRONOS_LEDS_CCM1_STATUS_REG 0x15 + +#define CRONOS_LEDS_CCM_POWER_REG 0x16 + +#define CRONOS_SMC_BMC_MAC_LOW_REG 0x30 +#define CRONOS_SMC_BMC_MAC_HIGH_REG 0x35 + +#define CRONOS_SMC_DEVICE_ID_LOW_REG 0x70 +#define CRONOS_SMC_DEVICE_ID_HIGH_REG 0x71 +#define CRONOS_SMC_REVISION_LOW_REG 0x72 +#define CRONOS_SMC_REVISION_HIGH_REG 0x73 + +#define CRONOS_SMC_LEDS_BRIGHTNESS_SET_MASK 0x7F +#define CRONOS_LEDS_MAX_BRIGHTNESS 0x7F + +#define CRONOS_BMC_RESET_VAL 0xc2 + +#define CRONOS_WDT_CLR_VAL 0xc3 +#define CRONOS_WDT_ENABLE_MASK 0x80 +#define CRONOS_WDT_ENABLE_VAL 0x80 +#define CRONOS_WDT_DISABLE_VAL 0x00 +#define CRONOS_WDT_TIMEOUT_MASK 0x07 +#define CRONOS_WDT_CTL_RESET_VAL 0x00 + +struct sony_cronos_smc { + struct device *dev; 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Tue, 6 Jan 2026 18:21:47 -0600 (CST) DKIM-Filter: OpenDKIM Filter v2.10.3 mail.rptsys.com 73A917790ECC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=raptorengineering.com; s=B8E824E6-0BE2-11E6-931D-288C65937AAD; t=1767745307; bh=ohJuFHrV6bXhqPEzzVPSiODAlRIGP36xHY4yr/yjYvw=; h=From:To:Date:Message-Id:MIME-Version; b=gsUtJ+rFEOEx1zJlZu7LgoW4Bpx0lFB8Mq2eriWyRdeRv3ohUWX29NacY88GN50xT 3kGSeihu0JFuie8mnaOliK+kfAVzxOi8yq+HooZaRHwCEpT+ua2QM4K3JeubjPwSkP fiWIVck9t8W2ZUFOXKXyoVZe4bkFAm1DljUC6gQs= X-Virus-Scanned: amavisd-new at rptsys.com Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id lLXM8OfIu4wa; Tue, 6 Jan 2026 18:21:47 -0600 (CST) Received: from rcs-ewks-005.starlink.edu (unknown [192.168.20.42]) by mail.rptsys.com (Postfix) with ESMTPSA id 4A0A67790ECB; Tue, 6 Jan 2026 18:21:47 -0600 (CST) From: Timothy Pearson To: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, robh+dt@kernel.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, Georgy.Yakovlev@sony.com, sanastasio@raptorengineering.com, Timothy Pearson Subject: [PATCH v6 3/4] led: sony-cronos-smc: Add RGB LED driver for Sony Cronos SMC Date: Tue, 6 Jan 2026 18:21:35 -0600 Message-Id: <20260107002136.3121607-4-tpearson@raptorengineering.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260107002136.3121607-1-tpearson@raptorengineering.com> References: <20260107002136.3121607-1-tpearson@raptorengineering.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Sony Cronos Platform Controller is a multi-purpose platform controller = with an integrated multi-channel RGB LED controller. The LED controller is a pseudo-RGB device with only two states for each of the RGB subcomponents of each LED, but is exposed as a full RGB device for ease of integration with userspace software. Internal thresholding is used to convert the color val= ues to the required on/off RGB subcomponent controls. Signed-off-by: Timothy Pearson --- drivers/leds/Kconfig | 19 ++ drivers/leds/Makefile | 1 + drivers/leds/leds-sony-cronos.c | 376 ++++++++++++++++++++++++++++++++ 3 files changed, 396 insertions(+) create mode 100644 drivers/leds/leds-sony-cronos.c diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index 11e7282dc297..18bad7c643f3 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -1009,6 +1009,25 @@ config LEDS_IP30 To compile this driver as a module, choose M here: the module will be called leds-ip30. =20 +config LEDS_SONY_CRONOS + tristate "LED support for the Sony Cronos SMC" + depends on ARCH_ASPEED || COMPILE_TEST + depends on LEDS_CLASS && I2C + depends on LEDS_CLASS_MULTICOLOR + depends on MFD_SONY_CRONOS_SMC + + help + Say Y here to include support for LEDs for the + Sony Cronos system management controller. + + All known Cronos systems use the ASpeed AST2600 SoC, + therefore the configuration option is gated on + ARCH_ASPEED selection. If this changes, add the new + SoCs to the selection list. + + To compile this driver as a module, choose M here: the module + will be called leds-sony-cronos. + config LEDS_ACER_A500 tristate "Power button LED support for Acer Iconia Tab A500" depends on LEDS_CLASS && MFD_ACER_A500_EC diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile index 9a0333ec1a86..6dbcf747cab6 100644 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile @@ -84,6 +84,7 @@ obj-$(CONFIG_LEDS_POWERNV) +=3D leds-powernv.o obj-$(CONFIG_LEDS_PWM) +=3D leds-pwm.o obj-$(CONFIG_LEDS_QNAP_MCU) +=3D leds-qnap-mcu.o obj-$(CONFIG_LEDS_REGULATOR) +=3D leds-regulator.o +obj-$(CONFIG_LEDS_SONY_CRONOS) +=3D leds-sony-cronos.o obj-$(CONFIG_LEDS_SC27XX_BLTC) +=3D leds-sc27xx-bltc.o obj-$(CONFIG_LEDS_ST1202) +=3D leds-st1202.o obj-$(CONFIG_LEDS_SUN50I_A100) +=3D leds-sun50i-a100.o diff --git a/drivers/leds/leds-sony-cronos.c b/drivers/leds/leds-sony-crono= s.c new file mode 100644 index 000000000000..e2b40a27421e --- /dev/null +++ b/drivers/leds/leds-sony-cronos.c @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LED driver for Sony Cronos SMCs + * Copyright (C) 2012 Dialog Semiconductor Ltd. + * Copyright (C) 2023 Sony Interactive Entertainment + * Copyright (C) 2025 Raptor Engineering, LLC + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Masks and Bit shifts */ +#define CRONOS_LEDS_STATUS_FLASHING_MASK 0x40 +#define CRONOS_LEDS_STATUS_FLASHING_SHIFT 6 +#define CRONOS_LEDS_STATUS_COLOR_MASK 0x07 +#define CRONOS_LEDS_STATUS_COLOR_SHIFT 0 + +#define CRONOS_LEDS_LINK_FLASHING_MASK 0x80 +#define CRONOS_LEDS_LINK_FLASHING_SHIFT 7 +#define CRONOS_LEDS_LINK_COLOR_MASK 0x38 +#define CRONOS_LEDS_LINK_COLOR_SHIFT 3 + +#define CRONOS_LEDS_CCM1_POWER_COLOR_MASK 0x03 +#define CRONOS_LEDS_CCM1_POWER_COLOR_SHIFT 0 +#define CRONOS_LEDS_CCM2_POWER_COLOR_MASK 0x0C +#define CRONOS_LEDS_CCM2_POWER_COLOR_SHIFT 2 +#define CRONOS_LEDS_CCM3_POWER_COLOR_MASK 0x30 +#define CRONOS_LEDS_CCM3_POWER_COLOR_SHIFT 4 +#define CRONOS_LEDS_CCM4_POWER_COLOR_MASK 0xC0 +#define CRONOS_LEDS_CCM4_POWER_COLOR_SHIFT 6 + +/* LED Color mapping - Links and status LEDs */ +#define LED_COLOR_OFF 0x00 +#define LED_COLOR_BLUE 0x01 +#define LED_COLOR_GREEN 0x02 +#define LED_COLOR_RED 0x04 + +/* LED Color mapping - Power state LEDs */ +#define LED_COLOR_POWER_OFF 0x00 +#define LED_COLOR_POWER_RED 0x02 +#define LED_COLOR_POWER_GREEN 0x01 + +/* Number of LEDs per type */ +#define LED_COUNT_STATUS 6 +#define LED_COUNT_LINK 5 +#define LED_COUNT_POWER 4 +#define LED_COUNT_ALL (LED_COUNT_STATUS + LED_COUNT_LINK + LED_COUNT_POWER) + +enum sony_cronos_led_id { + LED_ID_CCM1_STATUS =3D 0x00, + LED_ID_CCM2_STATUS, + LED_ID_CCM3_STATUS, + LED_ID_CCM4_STATUS, + LED_ID_SWITCH_STATUS, + LED_ID_SMC_STATUS, + + LED_ID_CCM1_LINK, + LED_ID_CCM2_LINK, + LED_ID_CCM3_LINK, + LED_ID_CCM4_LINK, + LED_ID_SWITCH_LINK, + + LED_ID_CCM1_POWER, + LED_ID_CCM2_POWER, + LED_ID_CCM3_POWER, + LED_ID_CCM4_POWER +}; + +enum sony_cronos_led_type { + LED_TYPE_STATUS, + LED_TYPE_LINK, + LED_TYPE_POWER, +}; + +/** + * struct sony_cronos_led - per-LED part of driver private data structure + * @mc_cdev: multi-color LED class device + * @subled_info: per-channel information + * @led_register: led register in the MFD regmap + * @led_type: sie_cronos_led_type + * @led_id: sie_cronos_led_id + */ +struct sony_cronos_led { + struct led_classdev_mc mc_cdev; + struct mc_subled subled_info[LED_COUNT_ALL]; + u8 led_register; + enum sony_cronos_led_type led_type; + enum sony_cronos_led_id led_id; +}; + +#define to_cronos_led(l) container_of(l, struct sony_cronos_led, mc_cdev) + +/** + * struct sony_cronos_leds - driver private data structure + * @hw: handle to hw device + * @leds: flexible array of per-LED data + */ +struct sony_cronos_leds { + struct sony_cronos_smc *hw; + struct sony_cronos_led leds[]; +}; + +static int cronos_led_color_store(struct sony_cronos_smc *chip, struct son= y_cronos_led *led) +{ + u8 byte; + u8 color_mask; + u8 color_shift; + u8 color_key_red; + u8 color_key_green; + u8 color_key_blue; + int ret; + + if (led->led_type =3D=3D LED_TYPE_STATUS) { + color_mask =3D CRONOS_LEDS_STATUS_COLOR_MASK; + color_shift =3D CRONOS_LEDS_STATUS_COLOR_SHIFT; + } else if (led->led_type =3D=3D LED_TYPE_LINK) { + color_mask =3D CRONOS_LEDS_LINK_COLOR_MASK; + color_shift =3D CRONOS_LEDS_LINK_COLOR_SHIFT; + } else if (led->led_id =3D=3D LED_ID_CCM1_POWER) { + color_mask =3D CRONOS_LEDS_CCM1_POWER_COLOR_MASK; + color_shift =3D CRONOS_LEDS_CCM1_POWER_COLOR_SHIFT; + } else if (led->led_id =3D=3D LED_ID_CCM2_POWER) { + color_mask =3D CRONOS_LEDS_CCM2_POWER_COLOR_MASK; + color_shift =3D CRONOS_LEDS_CCM2_POWER_COLOR_SHIFT; + } else if (led->led_id =3D=3D LED_ID_CCM3_POWER) { + color_mask =3D CRONOS_LEDS_CCM3_POWER_COLOR_MASK; + color_shift =3D CRONOS_LEDS_CCM3_POWER_COLOR_SHIFT; + } else if (led->led_id =3D=3D LED_ID_CCM4_POWER) { + color_mask =3D CRONOS_LEDS_CCM4_POWER_COLOR_MASK; + color_shift =3D CRONOS_LEDS_CCM4_POWER_COLOR_SHIFT; + } else + return -EINVAL; + + switch (led->led_type) { + case LED_TYPE_POWER: + color_key_red =3D LED_COLOR_POWER_RED; + color_key_green =3D LED_COLOR_POWER_GREEN; + /* Blue channel does not exist for CCM power LEDs */ + color_key_blue =3D LED_COLOR_POWER_OFF; + break; + default: + color_key_red =3D LED_COLOR_RED; + color_key_green =3D LED_COLOR_GREEN; + color_key_blue =3D LED_COLOR_BLUE; + } + + /* Assemble SMC color command code */ + byte =3D LED_COLOR_POWER_OFF; + if (led->subled_info[0].brightness > 128) + byte |=3D color_key_red; + if (led->subled_info[1].brightness > 128) + byte |=3D color_key_green; + if (led->subled_info[2].brightness > 128) + byte |=3D color_key_blue; + + ret =3D regmap_update_bits(chip->regmap, led->led_register, color_mask, b= yte << color_shift); + if (ret) { + dev_err(chip->dev, "Failed to set color value 0x%02x to LED register 0x%= 02x\n", byte, + led->led_register); + return ret; + } + return 0; +} + +static int cronos_led_set_brightness(struct led_classdev *cdev, enum led_b= rightness brightness) +{ + struct led_classdev_mc *mc_cdev =3D lcdev_to_mccdev(cdev); + struct sony_cronos_leds *leds =3D dev_get_drvdata(cdev->dev->parent); + struct sony_cronos_led *led =3D to_cronos_led(mc_cdev); + + led_mc_calc_color_components(mc_cdev, brightness ?: cdev->max_brightness); + + return cronos_led_color_store(leds->hw, led); +} + +static int sony_cronos_led_register(struct device *dev, struct sony_cronos= _leds *leds, + struct sony_cronos_led *led, struct device_node *np) +{ + struct led_init_data init_data =3D {}; + struct led_classdev *cdev; + int led_index; + int ret, color; + + ret =3D of_property_read_u32(np, "reg", &led_index); + if (ret || led_index >=3D LED_COUNT_ALL) { + dev_err(dev, "'reg' property is out of range (0-%i)\n", LED_COUNT_ALL - = 1); + return -EINVAL; + } + + switch (led_index) { + case 0: + led->led_register =3D CRONOS_LEDS_CCM1_STATUS_REG; + led->led_type =3D LED_TYPE_STATUS; + led->led_id =3D LED_ID_CCM1_STATUS; + break; + case 1: + led->led_register =3D CRONOS_LEDS_CCM2_STATUS_REG; + led->led_type =3D LED_TYPE_STATUS; + led->led_id =3D LED_ID_CCM2_STATUS; + break; + case 2: + led->led_register =3D CRONOS_LEDS_CCM3_STATUS_REG; + led->led_type =3D LED_TYPE_STATUS; + led->led_id =3D LED_ID_CCM3_STATUS; + break; + case 3: + led->led_register =3D CRONOS_LEDS_CCM4_STATUS_REG; + led->led_type =3D LED_TYPE_STATUS; + led->led_id =3D LED_ID_CCM4_STATUS; + break; + case 4: + led->led_register =3D CRONOS_LEDS_SWITCH_STATUS_REG; + led->led_type =3D LED_TYPE_STATUS; + led->led_id =3D LED_ID_SWITCH_STATUS; + break; + case 5: + led->led_register =3D CRONOS_LEDS_SMC_STATUS_REG; + led->led_type =3D LED_TYPE_STATUS; + led->led_id =3D LED_ID_SMC_STATUS; + break; + case 6: + led->led_register =3D CRONOS_LEDS_CCM1_STATUS_REG; + led->led_type =3D LED_TYPE_LINK; + led->led_id =3D LED_ID_CCM1_LINK; + break; + case 7: + led->led_register =3D CRONOS_LEDS_CCM2_STATUS_REG; + led->led_type =3D LED_TYPE_LINK; + led->led_id =3D LED_ID_CCM1_LINK; + break; + case 8: + led->led_register =3D CRONOS_LEDS_CCM3_STATUS_REG; + led->led_type =3D LED_TYPE_LINK; + led->led_id =3D LED_ID_CCM2_LINK; + break; + case 9: + led->led_register =3D CRONOS_LEDS_CCM4_STATUS_REG; + led->led_type =3D LED_TYPE_LINK; + led->led_id =3D LED_ID_CCM3_LINK; + break; + case 10: + led->led_register =3D CRONOS_LEDS_SWITCH_STATUS_REG; + led->led_type =3D LED_TYPE_LINK; + led->led_id =3D LED_ID_CCM4_LINK; + break; + case 11: + led->led_register =3D CRONOS_LEDS_CCM_POWER_REG; + led->led_type =3D LED_TYPE_POWER; + led->led_id =3D LED_ID_CCM1_POWER; + break; + case 12: + led->led_register =3D CRONOS_LEDS_CCM_POWER_REG; + led->led_type =3D LED_TYPE_POWER; + led->led_id =3D LED_ID_CCM2_POWER; + break; + case 13: + led->led_register =3D CRONOS_LEDS_CCM_POWER_REG; + led->led_type =3D LED_TYPE_POWER; + led->led_id =3D LED_ID_CCM3_POWER; + break; + case 14: + led->led_register =3D CRONOS_LEDS_CCM_POWER_REG; + led->led_type =3D LED_TYPE_POWER; + led->led_id =3D LED_ID_CCM4_POWER; + break; + default: + return -EINVAL; + } + + ret =3D of_property_read_u32(np, "color", &color); + if (ret || color !=3D LED_COLOR_ID_RGB) { + dev_warn(dev, + "Node %pOF: must contain 'color' property with value LED_COLOR_ID_RGB\= n", + np); + return -EINVAL; + } + + led->subled_info[0].color_index =3D LED_COLOR_ID_RED; + led->subled_info[1].color_index =3D LED_COLOR_ID_GREEN; + led->subled_info[2].color_index =3D LED_COLOR_ID_BLUE; + + /* Initial color is white */ + for (int i =3D 0; i < LED_COUNT_ALL; i++) { + led->subled_info[i].intensity =3D 255; + led->subled_info[i].brightness =3D 255; + led->subled_info[i].channel =3D i; + } + + led->mc_cdev.subled_info =3D led->subled_info; + led->mc_cdev.num_colors =3D LED_COUNT_ALL; + + init_data.fwnode =3D &np->fwnode; + + cdev =3D &led->mc_cdev.led_cdev; + cdev->max_brightness =3D 255; + cdev->brightness_set_blocking =3D cronos_led_set_brightness; + + /* Set initial color */ + ret =3D cronos_led_color_store(leds->hw, led); + if (ret < 0) + return dev_err_probe(dev, ret, "Cannot set LED %pOF initial color\n", np= ); + + ret =3D devm_led_classdev_multicolor_register_ext(dev, &led->mc_cdev, &in= it_data); + if (ret) + return dev_err_probe(dev, ret, "Cannot register LED %pOF\n", np); + + /* Set global brightness for all LEDs */ + ret =3D regmap_write(leds->hw->regmap, CRONOS_SMC_BRIGHTNESS_RED_REG, 0x0= 0); + ret =3D regmap_write(leds->hw->regmap, CRONOS_SMC_BRIGHTNESS_GREEN_REG, 0= x00); + ret =3D regmap_write(leds->hw->regmap, CRONOS_SMC_BRIGHTNESS_BLUE_REG, 0x= 00); + + return 0; +} + +static int sony_cronos_leds_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev_of_node(dev); + struct sony_cronos_smc *chip; + struct sony_cronos_leds *leds; + struct sony_cronos_led *led; + int ret, count; + + chip =3D dev_get_drvdata(dev->parent); + if (!chip) + return -EINVAL; + + count =3D of_get_available_child_count(np); + if (count =3D=3D 0) + return dev_err_probe(dev, -ENODEV, "LEDs are not defined in device tree!= \n"); + if (count > LED_COUNT_ALL) + return dev_err_probe(dev, -EINVAL, "Too many LEDs defined in device tree= !\n"); + + leds =3D devm_kzalloc(dev, struct_size(leds, leds, count), GFP_KERNEL); + if (!leds) + return -ENOMEM; + + leds->hw =3D chip; + + led =3D &leds->leds[0]; + for_each_available_child_of_node_scoped(np, child) { + ret =3D sony_cronos_led_register(dev, leds, led, child); + if (ret) + return ret; + + led++; + } + + return 0; +} + +static const struct of_device_id sony_cronos_led_of_id_table[] =3D { + { .compatible =3D "sie,cronos-led" }, + {}, +}; +MODULE_DEVICE_TABLE(of, sony_cronos_led_of_id_table); + +static struct platform_driver sony_cronos_led_driver =3D { + .driver =3D { + .name =3D "sie-cronos-led", + .of_match_table =3D sony_cronos_led_of_id_table, + }, + .probe =3D sony_cronos_leds_probe, +}; +module_platform_driver(sony_cronos_led_driver); + +MODULE_DESCRIPTION("LED driver for SIE Cronos SMCs"); +MODULE_AUTHOR("Timothy Pearson "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:sony-cronos-leds"); --=20 2.39.5 From nobody Sun Feb 8 10:30:19 2026 Received: from raptorengineering.com (mail.raptorengineering.com [23.155.224.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 34E60199931; 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s=B8E824E6-0BE2-11E6-931D-288C65937AAD; t=1767745308; bh=x7Jl269MPnTGVh+oawTEvlijbkfUsn1ILrEkuSLx78M=; h=From:To:Date:Message-Id:MIME-Version; b=Ds98jNGRHWDFl05PClkGzDL7+3LMqcnYwY6M08rL5RpqDXbppffJwwSW2+7paUpaH 6MkwrV5jD06eFT1CelJ5u6di2UfvRb+gfX2eUiJ8SdoqtTLauzbTvKdYVmN28rqkL8 6FDK7pCJHCRQOc09KadT55VkYc7A49KfLqewlAJs= X-Virus-Scanned: amavisd-new at rptsys.com Received: from mail.rptsys.com ([127.0.0.1]) by localhost (vali.starlink.edu [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id qMTKWv_u0aRs; Tue, 6 Jan 2026 18:21:47 -0600 (CST) Received: from rcs-ewks-005.starlink.edu (unknown [192.168.20.42]) by mail.rptsys.com (Postfix) with ESMTPSA id BF6477790ECB; Tue, 6 Jan 2026 18:21:47 -0600 (CST) From: Timothy Pearson To: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, robh+dt@kernel.org, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lee@kernel.org, Georgy.Yakovlev@sony.com, sanastasio@raptorengineering.com, Timothy Pearson Subject: [PATCH v6 4/4] watchdog: sony-cronos-smc: Add watchdog driver for Sony Cronos SMC Date: Tue, 6 Jan 2026 18:21:36 -0600 Message-Id: <20260107002136.3121607-5-tpearson@raptorengineering.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260107002136.3121607-1-tpearson@raptorengineering.com> References: <20260107002136.3121607-1-tpearson@raptorengineering.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Sony Cronos Platform Controller is a multi-purpose platform controller = with an integrated watchdog. Add the watchdog driver for the Cronos SMC. Signed-off-by: Timothy Pearson --- drivers/watchdog/Kconfig | 17 ++ drivers/watchdog/Makefile | 1 + drivers/watchdog/sony-cronos-wdt.c | 283 +++++++++++++++++++++++++++++ 3 files changed, 301 insertions(+) create mode 100644 drivers/watchdog/sony-cronos-wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index d3b9df7d466b..9001e4184e9d 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -416,6 +416,23 @@ config SL28CPLD_WATCHDOG To compile this driver as a module, choose M here: the module will be called sl28cpld_wdt. =20 +config SONY_CRONOS_WATCHDOG + tristate "Sony Cronos CPLD Watchdog" + depends on ARCH_ASPEED || COMPILE_TEST + depends on I2C + select WATCHDOG_CORE + help + Say Y here to include support for the watchdog timer + for the Sony Cronos control CPLD. + + All known Cronos systems use the ASpeed AST2600 SoC, + therefore the configuration option is gated on + ARCH_ASPEED selection. If this changes, add the new + SoCs to the selection list. + + To compile this driver as a module, choose M here: the + module will be called sony-cronos-wdt. + # ALPHA Architecture =20 # ARM Architecture diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index ba52099b1253..aa4d7aa15613 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -244,3 +244,4 @@ obj-$(CONFIG_MENZ069_WATCHDOG) +=3D menz69_wdt.o obj-$(CONFIG_RAVE_SP_WATCHDOG) +=3D rave-sp-wdt.o obj-$(CONFIG_STPMIC1_WATCHDOG) +=3D stpmic1_wdt.o obj-$(CONFIG_SL28CPLD_WATCHDOG) +=3D sl28cpld_wdt.o +obj-$(CONFIG_SONY_CRONOS_WATCHDOG) +=3D sony-cronos-wdt.o diff --git a/drivers/watchdog/sony-cronos-wdt.c b/drivers/watchdog/sony-cro= nos-wdt.c new file mode 100644 index 000000000000..650fcee28885 --- /dev/null +++ b/drivers/watchdog/sony-cronos-wdt.c @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Watchdog device driver for Sony Cronos SMCs + * Copyright (C) 2015 Dialog Semiconductor Ltd. + * Copyright (C) 2022-2025 Raptor Engineering, LLC + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const unsigned int wdt_timeout[] =3D { 10, 80 }; +static const unsigned int wdt_timeout_ctl_bits[] =3D { 0x1, 0x0 }; +#define CRONOS_TWDSCALE_DISABLE 0 +#define CRONOS_TWDSCALE_MIN 1 +#define CRONOS_TWDSCALE_MAX (ARRAY_SIZE(wdt_timeout) - 1) +#define CRONOS_WDT_MIN_TIMEOUT wdt_timeout[CRONOS_TWDSCALE_MIN] +#define CRONOS_WDT_MAX_TIMEOUT wdt_timeout[CRONOS_TWDSCALE_MAX] +#define CRONOS_WDG_DEFAULT_TIMEOUT wdt_timeout[CRONOS_TWDSCALE_MAX] + +struct sony_cronos_watchdog { + struct sony_cronos_smc *hw; + struct watchdog_device wdtdev; +}; + +static unsigned int sony_cronos_wdt_read_timeout(struct sony_cronos_watchd= og *wdt) +{ + unsigned int i; + unsigned int val; + + regmap_read(wdt->hw->regmap, CRONOS_WDT_CTL_REG, &val); + + for (i =3D CRONOS_TWDSCALE_MIN; i <=3D CRONOS_TWDSCALE_MAX; i++) { + if (wdt_timeout_ctl_bits[i] =3D=3D (val & CRONOS_WDT_TIMEOUT_MASK)) + return wdt_timeout[i]; + } + + dev_err(wdt->hw->dev, "Invalid configuration data present in watchdog con= trol register!\n"); + return wdt_timeout[CRONOS_WDT_MIN_TIMEOUT]; +} + +static unsigned int sony_cronos_wdt_timeout_to_sel(unsigned int secs) +{ + unsigned int i; + + for (i =3D CRONOS_TWDSCALE_MIN; i <=3D CRONOS_TWDSCALE_MAX; i++) { + if (wdt_timeout[i] >=3D secs) + return wdt_timeout_ctl_bits[i]; + } + + return wdt_timeout_ctl_bits[CRONOS_TWDSCALE_MAX]; +} + +static int sony_cronos_reset_watchdog_timer(struct sony_cronos_watchdog *w= dt) +{ + return regmap_write(wdt->hw->regmap, CRONOS_WDT_CLR_REG, CRONOS_WDT_CLR_V= AL); +} + +static int sony_cronos_wdt_update_timeout_register(struct sony_cronos_watc= hdog *wdt, + unsigned int regval) +{ + int ret; + + struct sony_cronos_smc *chip =3D wdt->hw; + + ret =3D sony_cronos_reset_watchdog_timer(wdt); + if (ret) { + dev_err(wdt->hw->dev, "Watchdog failed to reset (err =3D %d)\n", ret); + goto done; + } + + return regmap_update_bits(chip->regmap, CRONOS_WDT_CTL_REG, CRONOS_WDT_TI= MEOUT_MASK, + regval); + +done: + return ret; +} + +static int sony_cronos_wdt_start(struct watchdog_device *wdd) +{ + struct sony_cronos_watchdog *wdt =3D watchdog_get_drvdata(wdd); + struct sony_cronos_smc *chip =3D wdt->hw; + unsigned int selector; + int ret; + + selector =3D sony_cronos_wdt_timeout_to_sel(wdt->wdtdev.timeout); + ret =3D sony_cronos_wdt_update_timeout_register(wdt, selector); + if (ret) { + dev_err(wdt->hw->dev, "Watchdog prestart configuration failed (err =3D %= d)\n", ret); + goto done; + } + + ret =3D regmap_update_bits(chip->regmap, CRONOS_WDT_CTL_REG, CRONOS_WDT_E= NABLE_MASK, 1); + + if (ret) + dev_err(wdt->hw->dev, "Watchdog failed to start (err =3D %d)\n", ret); + +done: + return ret; +} + +static int sony_cronos_wdt_stop(struct watchdog_device *wdd) +{ + struct sony_cronos_watchdog *wdt =3D watchdog_get_drvdata(wdd); + struct sony_cronos_smc *chip =3D wdt->hw; + int ret; + + ret =3D regmap_update_bits(chip->regmap, CRONOS_WDT_CTL_REG, CRONOS_WDT_E= NABLE_MASK, 1); + if (ret) + dev_err(wdt->hw->dev, "Watchdog failed to stop (err =3D %d)\n", ret); + + return ret; +} + +static int sony_cronos_wdt_ping(struct watchdog_device *wdd) +{ + struct sony_cronos_watchdog *wdt =3D watchdog_get_drvdata(wdd); + int ret; + + /* + * Prevent pings from occurring late in system poweroff/reboot sequence + * and possibly locking out restart handler from accessing i2c bus. + */ + if (system_state > SYSTEM_RUNNING) + return 0; + + ret =3D sony_cronos_reset_watchdog_timer(wdt); + if (ret) + dev_err(wdt->hw->dev, "Failed to ping the watchdog (err =3D %d)\n", ret); + + return ret; +} + +static int sony_cronos_wdt_set_timeout(struct watchdog_device *wdd, unsign= ed int timeout) +{ + struct sony_cronos_watchdog *wdt =3D watchdog_get_drvdata(wdd); + unsigned int selector; + int ret; + + selector =3D sony_cronos_wdt_timeout_to_sel(timeout); + ret =3D sony_cronos_wdt_update_timeout_register(wdt, selector); + if (ret) + dev_err(wdt->hw->dev, "Failed to set watchdog timeout (err =3D %d)\n", r= et); + else + wdd->timeout =3D wdt_timeout[selector]; + + return ret; +} + +static int sony_cronos_wdt_restart(struct watchdog_device *wdd, unsigned l= ong action, void *data) +{ + struct sony_cronos_watchdog *wdt =3D watchdog_get_drvdata(wdd); + struct i2c_client *client =3D to_i2c_client(wdt->hw->dev); + int ret; + + /* Don't use regmap because it is not atomic safe */ + ret =3D i2c_smbus_write_byte_data(client, CRONOS_WDT_CTL_REG, CRONOS_WDT_= CTL_RESET_VAL); + ret =3D i2c_smbus_write_byte_data(client, CRONOS_BMC_RESET_REG, CRONOS_BM= C_RESET_VAL); + if (ret < 0) + dev_alert(wdt->hw->dev, "Failed to shutdown (err =3D %d)\n", ret); + + /* wait for reset to assert... */ + mdelay(500); + + return ret; +} + +static const struct watchdog_info sony_cronos_watchdog_info =3D { + .options =3D WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, + .identity =3D "Sony Cronos WDT", +}; + +static const struct watchdog_ops sony_cronos_watchdog_ops =3D { + .owner =3D THIS_MODULE, + .start =3D sony_cronos_wdt_start, + .stop =3D sony_cronos_wdt_stop, + .ping =3D sony_cronos_wdt_ping, + .set_timeout =3D sony_cronos_wdt_set_timeout, + .restart =3D sony_cronos_wdt_restart, +}; + +static const struct of_device_id sony_cronos_compatible_id_table[] =3D { + { + .compatible =3D "sony,cronos-watchdog", + }, + {}, +}; + +MODULE_DEVICE_TABLE(of, sony_cronos_compatible_id_table); + +static int sony_cronos_wdt_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + unsigned int timeout; + struct sony_cronos_smc *chip; + struct sony_cronos_watchdog *wdt; + + chip =3D dev_get_drvdata(dev->parent); + if (!chip) + return -EINVAL; + + wdt =3D devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); + if (!wdt) + return -ENOMEM; + + wdt->hw =3D chip; + + wdt->wdtdev.info =3D &sony_cronos_watchdog_info; + wdt->wdtdev.ops =3D &sony_cronos_watchdog_ops; + wdt->wdtdev.min_timeout =3D CRONOS_WDT_MIN_TIMEOUT; + wdt->wdtdev.max_timeout =3D CRONOS_WDT_MAX_TIMEOUT; + wdt->wdtdev.min_hw_heartbeat_ms =3D 0; + wdt->wdtdev.timeout =3D CRONOS_WDG_DEFAULT_TIMEOUT; + wdt->wdtdev.status =3D WATCHDOG_NOWAYOUT_INIT_STATUS; + wdt->wdtdev.parent =3D dev; + + watchdog_set_restart_priority(&wdt->wdtdev, 128); + + watchdog_set_drvdata(&wdt->wdtdev, wdt); + dev_set_drvdata(dev, &wdt->wdtdev); + + timeout =3D sony_cronos_wdt_read_timeout(wdt); + if (timeout) + wdt->wdtdev.timeout =3D timeout; + + /* Set timeout from DT value if available */ + watchdog_init_timeout(&wdt->wdtdev, 0, dev->parent); + + if (timeout) { + sony_cronos_wdt_set_timeout(&wdt->wdtdev, wdt->wdtdev.timeout); + set_bit(WDOG_HW_RUNNING, &wdt->wdtdev.status); + } + + return devm_watchdog_register_device(dev, &wdt->wdtdev); +} + +static int __maybe_unused sony_cronos_wdt_suspend(struct device *dev) +{ + struct watchdog_device *wdd =3D dev_get_drvdata(dev); + + if (watchdog_active(wdd)) + return sony_cronos_wdt_stop(wdd); + + return 0; +} + +static int __maybe_unused sony_cronos_wdt_resume(struct device *dev) +{ + struct watchdog_device *wdd =3D dev_get_drvdata(dev); + + if (watchdog_active(wdd)) + return sony_cronos_wdt_start(wdd); + + return 0; +} + +static SIMPLE_DEV_PM_OPS(sony_cronos_wdt_pm_ops, sony_cronos_wdt_suspend, = sony_cronos_wdt_resume); + +static struct platform_driver sony_cronos_wdt_driver =3D { + .probe =3D sony_cronos_wdt_probe, + .driver =3D { + .name =3D "sony-cronos-watchdog", + .pm =3D &sony_cronos_wdt_pm_ops, + .of_match_table =3D sony_cronos_compatible_id_table, + }, +}; +module_platform_driver(sony_cronos_wdt_driver); + +MODULE_AUTHOR("Raptor Engineering, LLC "); +MODULE_DESCRIPTION("WDT device driver for Sony Cronos SMCs"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:sony-cronos-watchdog"); --=20 2.39.5