From nobody Sat Feb 7 07:24:30 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9B072FD675; Wed, 7 Jan 2026 21:46:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767822366; cv=none; b=dNzD7X9ACSASheOyL93AD29ed3K58xRSfUQancVbtBfcxW/kl7kfBJ4+HLHre7JOHevBTVg0/SrAlWsY1Ue6NgDqC7dF5IEDF4wS0J8gF5jiykdM1i4CNft7ptes4X7D2RpxQ8nFsB5NyL/z/m6pZjL7r15nd+yibAkf6NiR3f8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767822366; c=relaxed/simple; bh=NdS4ZdXBkkRN7K08sIvtbJQP3h4b7Q0tVM5s2X+lZ14=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=R5iFNsvv3dI7+1Dc62HKB1fcXW4MIt+8GBuYWfRWRG5p8anh8VxjvvCMrmFyGL+a3oxu/EVA1X1LpJtO9LwvIo8PMnJaxxBgzYDQhDMvd+xWbm0jCskZRCeXXCjITZ3GUTgVL3wIYwP1rH23/3vepJe4/9ziknFCGOAPfmmyVGg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=k0QqEpPa; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="k0QqEpPa" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1767822364; x=1799358364; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=NdS4ZdXBkkRN7K08sIvtbJQP3h4b7Q0tVM5s2X+lZ14=; b=k0QqEpPaY2EdNkSsUuGA5VS8ZprSZAOCmALi/q0HlqBzJ0Nbnpiz5fCh pGjGfiuffe4LoKtj/TZv0qu9dFW0uAnU+ZiZerwsbw4hNhpEfyMMhVUqM Cy4LuWiuTRfEQvihC3ZDmHwtmaBrGnrfEn4EkTaAl7QXdjPx9Gl2viWSu lUhERxT34yhgFyUly53xUQGIykYXga4/4j6PRyCDXjzq2xYUkk+FoQn4y kSZizWircY5NmDv/19jQBLc6MdBkc04ds+ClNiwHgoWbRm8Ifp/5clklE t7a/2wxfIx6ymtw6XO1542c2PXntx6gkSS9hEsMxY+NCEtxoKoaoeadYg g==; X-CSE-ConnectionGUID: 2spQBLkZTJ6AjRPCMjWG3Q== X-CSE-MsgGUID: 0McTCgOeSDaqy/wTvEaHMw== X-IronPort-AV: E=McAfee;i="6800,10657,11664"; a="69359269" X-IronPort-AV: E=Sophos;i="6.21,209,1763452800"; d="scan'208";a="69359269" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2026 13:46:01 -0800 X-CSE-ConnectionGUID: UzgZZJMtS7aXDaIuk6g7VA== X-CSE-MsgGUID: P8DIsaDNT42ExW8cS8eopQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,209,1763452800"; d="scan'208";a="207510892" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2026 13:46:01 -0800 From: Ricardo Neri Date: Wed, 07 Jan 2026 13:44:37 -0800 Subject: [PATCH v8 01/10] x86/topology: Add missing struct declaration and attribute dependency Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260107-rneri-wakeup-mailbox-v8-1-2f5b6785f2f5@linux.intel.com> References: <20260107-rneri-wakeup-mailbox-v8-0-2f5b6785f2f5@linux.intel.com> In-Reply-To: <20260107-rneri-wakeup-mailbox-v8-0-2f5b6785f2f5@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , kernel test robot , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767822314; l=2940; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=NdS4ZdXBkkRN7K08sIvtbJQP3h4b7Q0tVM5s2X+lZ14=; b=xzVydyLiGWBex4Xjw66rRDOffP2UTOf3Endcem8IFBdIE53KV79bxtqRpwLb5Jp//9h9bP6O5 KCAUXTXotX9BpQwKpYwD1EYV3XTvCS2Eta6qsqzTFlNQZUx94abv6Zy X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= The prototypes for get_topology_cpu_type_name() and get_topology_cpu_type() take a pointer to struct cpuinfo_x86, but asm/topology.h neither includes nor forward-declares the structure. Including asm/topology.h, directly or indirectly, without including asm/processor.h triggers a warning: ./arch/x86/include/asm/topology.h:159:47: error: =E2=80=98struct cpuinf= o_x86=E2=80=99 declared inside parameter list will not be visible outside of this definition or declaration [-Werror] 159 | const char *get_topology_cpu_type_name(struct cpuinfo_x86 *c); | ^~~~~~~~~~~ Since only a pointer is needed, add a forward declaration of struct cpuinfo_x86. Additionally, sysctl_sched_itmt_enabled is declared in asm/topology.h with the __read_mostly attribute, but the header does not include linux/cache.h. This causes a build failure when including asm/topology.h but not linux/ cache.h: ./arch/x86/include/asm/topology.h:264:27: error: expected =E2=80=98=3D= =E2=80=99, =E2=80=98,=E2=80=99, =E2=80=98;=E2=80=99, =E2=80=98asm=E2=80=99 or =E2=80=98__attribute__= =E2=80=99 before =E2=80=98sysctl_sched_itmt_enabled=E2=80=99 264 | extern bool __read_mostly sysctl_sched_itmt_enabled; | ^~~~~~~~~~~~~~~~~~~~~~~~~ Include the required header. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202511181954.UMxCeTV1-lkp@int= el.com/ Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202511190008.AA0NTn3G-lkp@int= el.com/ Signed-off-by: Ricardo Neri --- I independently found this issue when including asm/acpi.h to arch/x86/ hyperv/hv_vtl.c, which implicitly includes asm/topology.h but not asm/ processor.h nor linux/cache.h. --- Changes in v8: - Added this patch. Changes in v7: - N/A Changes in v6: - N/A Changes in v5: - N/A Changes in v4: - N/A Changes in v3: - N/A Changes in v2: - N/A Changes in v3: - N/A Changes in v2: - N/A --- arch/x86/include/asm/topology.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topolog= y.h index 1fadf0cf520c..630521a03982 100644 --- a/arch/x86/include/asm/topology.h +++ b/arch/x86/include/asm/topology.h @@ -156,6 +156,8 @@ extern unsigned int __max_threads_per_core; extern unsigned int __num_threads_per_package; extern unsigned int __num_cores_per_package; =20 +struct cpuinfo_x86; + const char *get_topology_cpu_type_name(struct cpuinfo_x86 *c); enum x86_topology_cpu_type get_topology_cpu_type(struct cpuinfo_x86 *c); =20 @@ -259,6 +261,7 @@ extern bool x86_topology_update; =20 #ifdef CONFIG_SCHED_MC_PRIO #include +#include =20 DECLARE_PER_CPU_READ_MOSTLY(int, sched_core_priority); extern bool __read_mostly sysctl_sched_itmt_enabled; --=20 2.43.0 From nobody Sat Feb 7 07:24:30 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBFB22FE566; Wed, 7 Jan 2026 21:46:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767822365; cv=none; b=SxiVmHpliVScc57bs3quskaTPVxFWT3OvK/Uo2BndU645A4nlcS8cNIAVmtToJT6oSUeglwctj/d2UOxXbvJL7UeQHxMZG+NuhiA+QsqibsoOL1/xDMjisZaWbRN1kZWucdbZqqy68JojWdEEikmFUu6IjFuL+DVxbcuB4lKUAI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767822365; c=relaxed/simple; bh=qsylEiZMnDxF0pG7XJNnK9yxlJ9rH0r3W6wRkR6FHv8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RV1Posqi+J74UA7oyCsGlL5Ku0EV0bM+Jy8j+YFxDWdOQRSGqumTQro2n10aHxr4XHysfxHfBnVjTCtdKiZLGrjm6wD7hfZHVxw3ozLp3XHXQWa+Ua020iu1F9M5/LQG6r3g9pKpspD2sz0HoGm7LDQItO9klIp0lXKBLDouKq4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=a5eS1ior; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="a5eS1ior" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1767822364; x=1799358364; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=qsylEiZMnDxF0pG7XJNnK9yxlJ9rH0r3W6wRkR6FHv8=; b=a5eS1ior+e7HH3fkwkfcBrErw6WaPqHCMgOypszfnBlSObCrb5SjqNfl 1ROhKJpiCXhMbRY9Nm/USyo2uAyBcLA5O1PuJ2W1TsbgoO+WaRhj7e+L0 9nYwzTilMomh/cmwAk3EkzfDDwf8l4T9eiYLpXgVhR4PB0QFJZvvQP4wI qb1ANRp6OwjUFsb95Cl6/5KoWsRpuhERzvVmTjAxl59iT2nCYmNb+XDFh VGArrlqIfQ8tXFZke3dK7ktBKa1CHuzTTlaj+KKzTIwPE20fcFkXhpM6i ZjI/I7VGUpaZOAzODje1NQUZWC/TvpzIZiOqonHUOpzjtxwU/sE2kcxrW A==; X-CSE-ConnectionGUID: CUH2C1E0Sye1BaggwN2Xpw== X-CSE-MsgGUID: 6O6uBkWFSICzrVYThkPgoA== X-IronPort-AV: E=McAfee;i="6800,10657,11664"; a="69359274" X-IronPort-AV: E=Sophos;i="6.21,209,1763452800"; d="scan'208";a="69359274" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2026 13:46:01 -0800 X-CSE-ConnectionGUID: nCm029DUR1SRzCiq1IpC5g== X-CSE-MsgGUID: NIGwZLpWSkyRArrvMxXQMQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,209,1763452800"; d="scan'208";a="207510896" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2026 13:46:01 -0800 From: Ricardo Neri Date: Wed, 07 Jan 2026 13:44:38 -0800 Subject: [PATCH v8 02/10] x86/acpi: Add functions to setup and access the wakeup mailbox Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260107-rneri-wakeup-mailbox-v8-2-2f5b6785f2f5@linux.intel.com> References: <20260107-rneri-wakeup-mailbox-v8-0-2f5b6785f2f5@linux.intel.com> In-Reply-To: <20260107-rneri-wakeup-mailbox-v8-0-2f5b6785f2f5@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767822314; l=3163; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=qsylEiZMnDxF0pG7XJNnK9yxlJ9rH0r3W6wRkR6FHv8=; b=8SBhZoOGv5eia+5DgOGyokViV8LLjJQp5LuTqFuyBsUd6prxJR7DHFl26g939x0vGklGBLiuy b5NOXNb81IwCcJNTc6upOl2UKe01BYcqR/wVdzSgHufCeI2wdu0ecHz X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= Systems that describe hardware using DeviceTree graphs may enumerate and implement the wakeup mailbox as defined in the ACPI specification but do not otherwise depend on ACPI. Expose functions to setup and access the location of the wakeup mailbox from outside ACPI code. The function acpi_setup_mp_wakeup_mailbox() stores the physical address of the mailbox and updates the wakeup_secondary_cpu_64() APIC callback. The function acpi_madt_multiproc_wakeup_mailbox() returns a pointer to the mailbox. Acked-by: Rafael J. Wysocki (Intel) Signed-off-by: Ricardo Neri --- Changes in v8: - Added Acked-by tag from Rafael. Thanks! Changes in v7: - Moved function declarations to arch/x86/include/asm/acpi.h - Added stubs for !CONFIG_ACPI. - Do not use these new functions in madt_wakeup.c. - Dropped Acked-by and Reviewed-by tags from Rafael and Dexuan as this patch changed. Changes in v6: - Fixed grammar error in the subject of the patch. (Rafael) - Added Acked-by tag from Rafael. Thanks! - Added Reviewed-by tag from Dexuan. Thanks! Changes in v5: - None Changes in v4: - Squashed the two first patches of the series into one, both introduce helper functions. (Rafael) - Renamed setup_mp_wakeup_mailbox() as acpi_setup_mp_wakeup_mailbox(). (Rafael) - Dropped the function prototype for !CONFIG_X86_64. (Rafael) Changes in v3: - Introduced this patch. Changes in v2: - N/A --- arch/x86/include/asm/acpi.h | 10 ++++++++++ arch/x86/kernel/acpi/madt_wakeup.c | 11 +++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h index a03aa6f999d1..820df375df79 100644 --- a/arch/x86/include/asm/acpi.h +++ b/arch/x86/include/asm/acpi.h @@ -182,6 +182,9 @@ void __iomem *x86_acpi_os_ioremap(acpi_physical_address= phys, acpi_size size); #define acpi_os_ioremap acpi_os_ioremap #endif =20 +void acpi_setup_mp_wakeup_mailbox(u64 addr); +struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wakeup_mailbox(void= ); + #else /* !CONFIG_ACPI */ =20 #define acpi_lapic 0 @@ -200,6 +203,13 @@ static inline u64 x86_default_get_root_pointer(void) return 0; } =20 +static inline void acpi_setup_mp_wakeup_mailbox(u64 addr) { } + +static inline struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wakeu= p_mailbox(void) +{ + return NULL; +} + #endif /* !CONFIG_ACPI */ =20 #define ARCH_HAS_POWER_INIT 1 diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt= _wakeup.c index 6d7603511f52..82caf44b45e3 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -247,3 +247,14 @@ int __init acpi_parse_mp_wake(union acpi_subtable_head= ers *header, =20 return 0; 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d="scan'208";a="207510900" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2026 13:46:01 -0800 From: Ricardo Neri Date: Wed, 07 Jan 2026 13:44:39 -0800 Subject: [PATCH v8 03/10] dt-bindings: reserved-memory: Wakeup Mailbox for Intel processors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260107-rneri-wakeup-mailbox-v8-3-2f5b6785f2f5@linux.intel.com> References: <20260107-rneri-wakeup-mailbox-v8-0-2f5b6785f2f5@linux.intel.com> In-Reply-To: <20260107-rneri-wakeup-mailbox-v8-0-2f5b6785f2f5@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , "Rafael J. Wysocki (Intel)" , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767822314; l=5190; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=82xM+H3fSBvMvy2l03PKfAo5wxYdkZ9cWHesuRhC6vg=; b=YIDmY0zSODSmEsmAdICm50Xs5tZBWPI6wqhrTPofOUtSyei06dvakB3Ms82f8KOOYroQGPl3h eO1AVqDz2+NDbZ5cDGluvPQZPOS9vkb8y6r1zS36lI6kAWR/cYpWvOF X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= Add DeviceTree bindings to enumerate the wakeup mailbox used in platform firmware for Intel processors. x86 platforms commonly boot secondary CPUs using an INIT assert, de-assert followed by Start-Up IPI messages. The wakeup mailbox can be used when this mechanism is unavailable. The wakeup mailbox offers more control to the operating system to boot secondary CPUs than a spin-table. It allows the reuse of the same wakeup vector for all CPUs while maintaining control over which CPUs to boot and when. While it is possible to achieve the same level of control using a spin-table, it would require specifying a separate `cpu-release-addr` for each secondary CPU. The operation and structure of the mailbox are described in the Multiprocessor Wakeup Structure defined in the ACPI specification. Note that this structure does not specify how to publish the mailbox to the operating system (ACPI-based platform firmware uses a separate table). No ACPI table is needed in DeviceTree-based firmware to enumerate the mailbox. Nodes that want to refer to the reserved memory usually define a `memory-region` property. /cpus/cpu* nodes would want to refer to the mailbox, but they do not have such property defined in the DeviceTree specification. Moreover, it would imply that there is a memory region per CPU. Instead, add a `compatible` property that the operating system can use to discover the mailbox. Reviewed-by: Dexuan Cui Reviewed-by: Rob Herring (Arm) Acked-by: Rafael J. Wysocki (Intel) Co-developed-by: Yunhong Jiang Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes in v8: - None Changes in v7: - Fixed Acked-by tag from Rafael to include the "(Intel)" suffix. Changes in v6: - Reworded the changelog for clarity. - Added Acked-by tag from Rafael. Thanks! - Added Reviewed-by tag from Rob. Thanks! - Added Reviewed-by tag from Dexuan. Thanks! Changes in v5: - Specified the version and section of the ACPI spec in which the wakeup mailbox is defined. (Rafael) - Fixed a warning from yamllint about line lengths of URLs. Changes in v4: - Removed redefinitions of the mailbox and instead referred to ACPI specification as per discussion on LKML. - Clarified that DeviceTree-based firmware do not require the use of ACPI tables to enumerate the mailbox. (Rob) - Described the need of using a `compatible` property. - Dropped the `alignment` property. (Krzysztof, Rafael) - Used a real address for the mailbox node. (Krzysztof) Changes in v3: - Implemented the mailbox as a reserved-memory node. Add to it a `compatible` property. (Krzysztof) - Explained the relationship between the mailbox and the `enable-mehod` property of the CPU nodes. - Expanded the documentation of the binding. Changes in v2: - Added more details to the description of the binding. - Added requirement a new requirement for cpu@N nodes to add an `enable-method`. --- .../reserved-memory/intel,wakeup-mailbox.yaml | 50 ++++++++++++++++++= ++++ 1 file changed, 50 insertions(+) diff --git a/Documentation/devicetree/bindings/reserved-memory/intel,wakeup= -mailbox.yaml b/Documentation/devicetree/bindings/reserved-memory/intel,wak= eup-mailbox.yaml new file mode 100644 index 000000000000..a80d3bac44c2 --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbo= x.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reserved-memory/intel,wakeup-mailbox.ya= ml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Wakeup Mailbox for Intel processors + +description: | + The Wakeup Mailbox provides a mechanism for the operating system to wake= up + secondary CPUs on Intel processors. It is an alternative to the INIT-!IN= IT- + SIPI sequence used on most x86 systems. + + The structure and operation of the mailbox is described in the Multiproc= essor + Wakeup Structure of the ACPI specification version 6.6 section 5.2.12.19= [1]. + + The implementation of the mailbox in platform firmware is described in t= he + Intel TDX Virtual Firmware Design Guide section 4.3.5 [2]. + + 1: https://uefi.org/specs/ACPI/6.6/05_ACPI_Software_Programming_Model.ht= ml#multiprocessor-wakeup-structure + 2: https://www.intel.com/content/www/us/en/content-details/733585/intel-= tdx-virtual-firmware-design-guide.html + + +maintainers: + - Ricardo Neri + +allOf: + - $ref: reserved-memory.yaml + +properties: + compatible: + const: intel,wakeup-mailbox + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <1>; + + wakeup-mailbox@ffff0000 { + compatible =3D "intel,wakeup-mailbox"; + reg =3D <0x0 0xffff0000 0x1000>; + }; + }; --=20 2.43.0 From nobody Sat Feb 7 07:24:30 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0717302163; Wed, 7 Jan 2026 21:46:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767822367; cv=none; b=VthzcHkAmjsHG+K6WO+5DJDtR9fUdJxFmVp0mrgufyUMFw2bwGV5HGfZEF3m/Cb54WZ34r8UKrGQw4G4YUntXtGoWXOZ8H6r2gHlIiIX87iKqfNN9I/twOsbhy+MtzRn8RXlwhfflNJ/s3+P1L0No8PBdUpK3ABcnVZVPnpk+CI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767822367; c=relaxed/simple; bh=vBl/wFc/Idotd1xOdmbDaIFtFynyU3RgAK2c/Q+umoY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=f1vWmY9faxEzySOvjpol14aHmvmC5xRinZZD4DmbTY2f0jEnpET4sZBCdusB6je4/l+OWNnv8lplYsf/tzrSiknZcc32DYNnSc3NGxPyVeVqpaxfTkNsH5tEIAllHPXYZyEezK61KtcL+ba9KxM6wFVhL4If7dDL/gxN016qq7I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=BHKEh0dx; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="BHKEh0dx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1767822365; x=1799358365; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=vBl/wFc/Idotd1xOdmbDaIFtFynyU3RgAK2c/Q+umoY=; b=BHKEh0dxCTClVlc1ajuCqjCIA38WVNx8u9DnjZiThV1NTaosJDm3C8ou Y619/9D2PfxcWOIlZcfLvq/8WCE2WS+paQ6ipjUygpDBjwGyzvuc5G3oc 6M0BOAq/eEpFs/o598Vb/nwo+jt5dSB2CYfNNha19SRZdTDEdj2uqncZ5 HQmtjeCHOVeADKSwmIQnLjlDDK/EQ3QaSQZS5WSb2Zz+Ey4f5rEJotXmA dWNsYcBaHx4we9Li9HNVRxVszq5gQW6CQ5TxAhKewXrst6HfhR2fIj50N PgNmL8eFnkESy9uGBJR95Y/b5+jYQKCSsxMy7HPGrvkXg0+uqhGSfceF2 g==; X-CSE-ConnectionGUID: O6D65noRSpa5Ug9XD2YYwA== X-CSE-MsgGUID: VmCIeIoJRjyLbq+0vTDOXA== X-IronPort-AV: E=McAfee;i="6800,10657,11664"; a="69359282" X-IronPort-AV: E=Sophos;i="6.21,209,1763452800"; d="scan'208";a="69359282" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2026 13:46:02 -0800 X-CSE-ConnectionGUID: b699fbwcS96ObaZIGuXTuw== X-CSE-MsgGUID: JwuWCHS/TjuG+cWkMwtnBA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,209,1763452800"; d="scan'208";a="207510905" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2026 13:46:01 -0800 From: Ricardo Neri Date: Wed, 07 Jan 2026 13:44:40 -0800 Subject: [PATCH v8 04/10] x86/dt: Parse the Wakeup Mailbox for Intel processors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260107-rneri-wakeup-mailbox-v8-4-2f5b6785f2f5@linux.intel.com> References: <20260107-rneri-wakeup-mailbox-v8-0-2f5b6785f2f5@linux.intel.com> In-Reply-To: <20260107-rneri-wakeup-mailbox-v8-0-2f5b6785f2f5@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767822314; l=4526; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=vBl/wFc/Idotd1xOdmbDaIFtFynyU3RgAK2c/Q+umoY=; b=1rluzKqIUMLBqdqnTjcprdZ+KRCf95fTZOk2YpJdAl9fKddOTnqZmqIT1MeOnm4+OxRULdk9T xploiIBFo7dAXrLBsRx5fsvGWRpNGfiT6E0wwQJK/F5qRtQRhdV/ws0 X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= The Wakeup Mailbox is a mechanism to boot secondary CPUs on systems that do not want or cannot use the INIT + StartUp IPI messages. The platform firmware is expected to implement the mailbox as described in the Multiprocessor Wakeup Structure of the ACPI specification. It is also expected to publish the mailbox to the operating system as described in the corresponding DeviceTree schema that accompanies the documentation of the Linux kernel. Reuse the existing functionality to set the memory location of the mailbox and update the wakeup_secondary_cpu_64() APIC callback. Make this functionality available to DeviceTree-based systems by making CONFIG_X86_ MAILBOX_WAKEUP depend on either CONFIG_OF or CONFIG_ACPI_MADT_WAKEUP. do_boot_cpu() uses wakeup_secondary_cpu_64() when set. It will be set if a wakeup mailbox is enumerated via an ACPI table or a DeviceTree node. For cases in which this behavior is not desired, this APIC callback can be updated later during boot using platform-specific hooks. Reviewed-by: Dexuan Cui Co-developed-by: Yunhong Jiang Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes in v8: - None Changes in v7: - #included asm/acpi.h to reflect the updated declaration of the needed functions. - (Kept Reviewed-by tag from Dexuan, as this single change is trivial.) Changes in v6: - Added Reviewed-by tag from Dexuan. Thanks! Changes in v5: - Made CONFIG_X86_MAILBOX_WAKEUP depend on CONFIG_OF or CONFIG_ACPI_ MADT_WAKEUP. Changes in v4: - Look for the wakeup mailbox unconditionally, regardless of whether cpu@N nodes have an `enable-method` property. - Add a reference to the ACPI specification. (Rafael) Changes in v3: - Added extra sanity checks when parsing the mailbox node. - Probe the mailbox using its `compatible` property - Setup the Wakeup Mailbox if the `enable-method` is found in the CPU nodes. - Cleaned up unneeded ifdeffery. - Clarified the mechanisms used to override the wakeup_secondary_64() callback to not use the mailbox when not desired. (Michael) - Edited the commit message for clarity. Changes in v2: - Disabled CPU offlining. - Modified dtb_parse_mp_wake() to return the address of the mailbox. --- arch/x86/kernel/devicetree.c | 47 ++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 47 insertions(+) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index dd8748c45529..318acaecb5ca 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -18,6 +18,7 @@ #include #include =20 +#include #include #include #include @@ -125,6 +126,51 @@ static void __init dtb_setup_hpet(void) #endif } =20 +#if defined(CONFIG_X86_64) && defined(CONFIG_SMP) + +#define WAKEUP_MAILBOX_SIZE 0x1000 +#define WAKEUP_MAILBOX_ALIGN 0x1000 + +/** dtb_wakeup_mailbox_setup() - Parse the wakeup mailbox from the device = tree + * + * Look for the presence of a wakeup mailbox in the DeviceTree. The mailbo= x is + * expected to follow the structure and operation described in the Multipr= ocessor + * Wakeup Structure of the ACPI specification. + */ +static void __init dtb_wakeup_mailbox_setup(void) +{ + struct device_node *node; + struct resource res; + + node =3D of_find_compatible_node(NULL, NULL, "intel,wakeup-mailbox"); + if (!node) + return; + + if (of_address_to_resource(node, 0, &res)) + goto done; + + /* The mailbox is a 4KB-aligned region.*/ + if (res.start & (WAKEUP_MAILBOX_ALIGN - 1)) + goto done; + + /* The mailbox has a size of 4KB. */ + if (res.end - res.start + 1 !=3D WAKEUP_MAILBOX_SIZE) + goto done; + + /* Not supported when the mailbox is used. */ + cpu_hotplug_disable_offlining(); + + acpi_setup_mp_wakeup_mailbox(res.start); +done: + of_node_put(node); +} +#else /* !CONFIG_X86_64 || !CONFIG_SMP */ +static inline int dtb_wakeup_mailbox_setup(void) +{ + return -EOPNOTSUPP; +} +#endif /* CONFIG_X86_64 && CONFIG_SMP */ + #ifdef CONFIG_X86_LOCAL_APIC =20 static void __init dtb_cpu_setup(void) @@ -287,6 +333,7 @@ static void __init x86_dtb_parse_smp_config(void) =20 dtb_setup_hpet(); dtb_apic_setup(); + dtb_wakeup_mailbox_setup(); } =20 void __init x86_flattree_get_config(void) --=20 2.43.0 From nobody Sat Feb 7 07:24:30 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07AB23043C9; Wed, 7 Jan 2026 21:46:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767822367; cv=none; b=F1Sdnu9v+Q3Jx01dOARLaWDKJT/W6lfYSOow3z8q+AW6xeH7Vg/LXSlY0bh7SeXjKLJladPNd9/G/VBzfJThvbvdyH7O5mQ+H2NlmQIrbb8MhSHJzU375mBuGdbrujiEdVpH1w3t0mJbTf6nRmowA4DG5iNykMryLQzzR8X2jfc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767822367; c=relaxed/simple; bh=v5H97xEUAh2fKGmHeY0PK9adgotGRC32vqqKPF82Vx8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XLEWCH9UYhKT+JEu4I4fefiv5XGsUkn7efgXkRnX6HK7nKiihOhnVXhY8EIL85/gZVes+TB7lH4h0ikF/e41p9jbxk3n3V/Kcfw0WG8bsvRbpS+Fcj6lH6kqHn9LVk4oW1+kfVFt7mCkgj+QWkd4MrEwrDfZEh+6Jpi5+noc5+A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WMX35N6W; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WMX35N6W" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1767822366; x=1799358366; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=v5H97xEUAh2fKGmHeY0PK9adgotGRC32vqqKPF82Vx8=; b=WMX35N6Wn6oqIjcRf/IsX5+gbekfhl6iP7U13IULBGEAddziIH/5WIvb FxK460gMlWklpSb3Gu/6uUHGQQ0tesGgQs4JX73lLPdiiAZexmbcVK7sQ CdRAQVrPbqj6SSP/5SNvnxYsHQmGOiEDxGLm55K4XxEgpMGqnu14y9p6i Q8S1fXycfPB4LIMAHuOn0tFr/PZ1RbepsdtIYlhIQ9TZhgi2u8pGBldJi Gj6gtaf+qyaHbAtc83bjgY/p9MWU1wCiskr5S4GcB5jnOdgrmeyPfj5E4 JKRBkjjGlQKWKCd+ut4MitaUQKvoweGU/jQ9wpo09pCOpb1t3Zx8e5mOC g==; X-CSE-ConnectionGUID: iDlaFtp4SLKfaxL4ae5CvQ== X-CSE-MsgGUID: n6mCimHySfKvs/bSH6DCMg== X-IronPort-AV: E=McAfee;i="6800,10657,11664"; a="69359289" X-IronPort-AV: E=Sophos;i="6.21,209,1763452800"; d="scan'208";a="69359289" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2026 13:46:02 -0800 X-CSE-ConnectionGUID: Je3Vdo9nSeW2rMVExiWCRg== X-CSE-MsgGUID: pMNoNe03SnemlgNr0iQiuQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,209,1763452800"; d="scan'208";a="207510909" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2026 13:46:02 -0800 From: Ricardo Neri Date: Wed, 07 Jan 2026 13:44:41 -0800 Subject: [PATCH v8 05/10] x86/hyperv/vtl: Set real_mode_header in hv_vtl_init_platform() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260107-rneri-wakeup-mailbox-v8-5-2f5b6785f2f5@linux.intel.com> References: <20260107-rneri-wakeup-mailbox-v8-0-2f5b6785f2f5@linux.intel.com> In-Reply-To: <20260107-rneri-wakeup-mailbox-v8-0-2f5b6785f2f5@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Yunhong Jiang , Thomas Gleixner , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767822314; l=2337; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=ErMFLuUmTpaxMgKxhwcgqcXaQtOiQTa7wQ9vKMhnTo4=; b=AYbsMzrKcaHaBESlMN2ZQJk4U3C9VR1nVwxjIHa9KrkjrdxOIWgaHUZltI5+ZUgi1kuuZHV0i GMTjUsqgVWTABhctud5mZwYAuyXZL0F/f93/4yJxNb2PHr+Kzq9vbnb X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= From: Yunhong Jiang Hyper-V VTL clears x86_platform.realmode_{init(), reserve()} in hv_vtl_init_platform() whereas it sets real_mode_header later in hv_vtl_early_init(). There is no need to deal with the settings of real mode memory in two places. Also, both functions are called much earlier than x86_platform.realmode_init() (via an early_initcall), where the real_mode_header is needed. Set real_mode_header in hv_vtl_init_platform() to keep all code dealing with memory for the real mode trampoline in one place. Besides making the code more readable, it prepares it for a subsequent changeset in which the behavior needs to change to support Hyper-V VTL guests in TDX a environment. Reviewed-by: Dexuan Cui Reviewed-by: Michael Kelley Suggested-by: Thomas Gleixner Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes in v8: - None Changes in v7: - None Changes in v6: - Corrected reference to hv_vtl_init_platform() in the changelog. (Dexuan) - Added Reviewed-by tag from Dexuan. Thanks! Changes in v5: - None Changes in v4: - Added Reviewed-by tag from Michael. Thanks! Changes in v3: - Edited the commit message for clarity. Changes in v2: - Introduced this patch. --- arch/x86/hyperv/hv_vtl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index c0edaed0efb3..f74199e77133 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -70,6 +70,7 @@ void __init hv_vtl_init_platform(void) =20 x86_platform.realmode_reserve =3D x86_init_noop; x86_platform.realmode_init =3D x86_init_noop; + real_mode_header =3D &hv_vtl_real_mode_header; x86_init.irqs.pre_vector_init =3D x86_init_noop; x86_init.timers.timer_init =3D x86_init_noop; x86_init.resources.probe_roms =3D x86_init_noop; @@ -249,7 +250,6 @@ int __init hv_vtl_early_init(void) panic("XSAVE has to be disabled as it is not supported by this module.\n" "Please add 'noxsave' to the kernel command line.\n"); =20 - real_mode_header =3D &hv_vtl_real_mode_header; apic_update_callback(wakeup_secondary_cpu_64, hv_vtl_wakeup_secondary_cpu= ); =20 return 0; --=20 2.43.0 From nobody Sat Feb 7 07:24:30 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF6DA318B89; Wed, 7 Jan 2026 21:46:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767822369; cv=none; b=rp4y9fvSpftsRksFP6tqX2A3ZIo+IrQqd85pgXbWGLvLGOK90hPbKm2PDNte0Dko/ZV/T7jPkxmjbZXDsvqXlT2fuGUXqhm7w9IVbrd0a1oH1vFN7h2S1xk05sWYtPbinGucJHgJvPRUf6nHjuwqKS89IFreGRdJsQhdslIJE+U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767822369; c=relaxed/simple; bh=9blOcO6x27MrcdDd6HLxfjCPfcgkn5DijlmNh5tB5GE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Xt09ag7lsiMELknr/3t+VSzLlJKx6ZRM4lFZ8mDWuVmPTzHXnW4DminCWEEt/qJafDMCjbwfJQW4NeP0uQksj7x/tUKjNRY1Ad2+e+ckmXf5guYfBq3OmBIgpYpTXdyUhOoyyYt4M1xFYHVX0Eo/N3auXlRWM2gc0JxP3Bt6rx4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EOmyPCrB; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EOmyPCrB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1767822367; x=1799358367; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=9blOcO6x27MrcdDd6HLxfjCPfcgkn5DijlmNh5tB5GE=; b=EOmyPCrBHGmafftBY7HCjGGWgRySfzdq/JObjIJ8z5bFbj6FS/0U7x+v S+d8S4lxuvD6Bvty2LQQX20j0/P2Y/wUd1KNATe9PSNp4OFWONFwLLmbn k9uFqEbRMcNDB4XIJeFYiH0Sy4ljHCWJP/FQWGQ59ByJaSEzWcHwknpnd XSOIAGNYCR00jWWk8ajKHs6qsjbBNAM9rHWgCgY3N+c+xO6gGi4fpz5OY 3YALD+WvJwH6FpFvHLwEYn8bwP4gWwom8SRY0h8p779sGZkDOMTPQeunA 3Lvjg61Ux/6HXxRShQCoF4DfgbKya2EfynvAZYHQTNgMLsNSKwZOAaqzy w==; X-CSE-ConnectionGUID: 5GAMAeAsQBKdOZc/siPa7Q== X-CSE-MsgGUID: 04HLYF0lRmaZMwb8xK8NaA== X-IronPort-AV: E=McAfee;i="6800,10657,11664"; a="69359292" X-IronPort-AV: E=Sophos;i="6.21,209,1763452800"; d="scan'208";a="69359292" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2026 13:46:02 -0800 X-CSE-ConnectionGUID: unxsrMyDR/iuIl2qD/DfqQ== X-CSE-MsgGUID: rv+/8wiBQe+wL8oW0cU/ag== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,209,1763452800"; d="scan'208";a="207510913" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2026 13:46:02 -0800 From: Ricardo Neri Date: Wed, 07 Jan 2026 13:44:42 -0800 Subject: [PATCH v8 06/10] x86/realmode: Make the location of the trampoline configurable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260107-rneri-wakeup-mailbox-v8-6-2f5b6785f2f5@linux.intel.com> References: <20260107-rneri-wakeup-mailbox-v8-0-2f5b6785f2f5@linux.intel.com> In-Reply-To: <20260107-rneri-wakeup-mailbox-v8-0-2f5b6785f2f5@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Yunhong Jiang , Thomas Gleixner , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767822314; l=3993; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=5LrntglSg7YhBSGj0x30FU7Ghm1ZgsQmlL/GeRIKcus=; b=jbos6LMgextmTayJjS4GcOl6d5B9wqgjLiFLlJzjv0EW0E4ixkYQR7Bu/OGT8rH9P+LgxB1+H z/zs4N0OM/rBIfK7QB8x3TV1N6K8JoGmiU1lUmi3N03Dr0ms8fzSZAH X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= From: Yunhong Jiang x86 CPUs boot in real mode. This mode uses a 1MB address space. The trampoline must reside below this 1MB memory boundary. There are platforms in which the firmware boots the secondary CPUs, switches them to long mode and transfers control to the kernel. An example of such a mechanism is the ACPI Multiprocessor Wakeup Structure. In this scenario there is no restriction on locating the trampoline under 1MB memory. Moreover, certain platforms (for example, Hyper-V VTL guests) may not have memory available for allocation below 1MB. Add a new member to struct x86_init_resources to specify the upper bound for the location of the trampoline memory. Preserve the default upper bound of 1MB to conserve the current behavior. Reviewed-by: Dexuan Cui Reviewed-by: Michael Kelley Originally-by: Thomas Gleixner Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes in v8: - None Changes in v7: - None Changes in v6: - Added Reviewed-by tag from Dexuan. Thanks! Changes in v5: - None Changes in v4: - Added Reviewed-by tag from Michael. Thanks! Changes in v3: - Edited the commit message for clarity. - Minor tweaks to comments. - Removed the option to not reserve the first 1MB of memory as it is not needed. Changes in v2: - Added this patch using code that Thomas suggested: https://lore.kernel.org/lkml/87a5ho2q6x.ffs@tglx/ --- arch/x86/include/asm/x86_init.h | 3 +++ arch/x86/kernel/x86_init.c | 3 +++ arch/x86/realmode/init.c | 7 +++---- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_ini= t.h index 6c8a6ead84f6..953d3199408a 100644 --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h @@ -31,12 +31,15 @@ struct x86_init_mpparse { * platform * @memory_setup: platform specific memory setup * @dmi_setup: platform specific DMI setup + * @realmode_limit: platform specific address limit for the real mode tra= mpoline + * (default 1M) */ struct x86_init_resources { void (*probe_roms)(void); void (*reserve_resources)(void); char *(*memory_setup)(void); void (*dmi_setup)(void); + unsigned long realmode_limit; }; =20 /** diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index 0a2bbd674a6d..a25fd7282811 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c @@ -9,6 +9,7 @@ #include #include #include +#include =20 #include #include @@ -69,6 +70,8 @@ struct x86_init_ops x86_init __initdata =3D { .reserve_resources =3D reserve_standard_io_resources, .memory_setup =3D e820__memory_setup_default, .dmi_setup =3D dmi_setup, + /* Has to be under 1M so we can execute real-mode AP code. */ + .realmode_limit =3D SZ_1M, }, =20 .mpparse =3D { diff --git a/arch/x86/realmode/init.c b/arch/x86/realmode/init.c index 88be32026768..694d80a5c68e 100644 --- a/arch/x86/realmode/init.c +++ b/arch/x86/realmode/init.c @@ -46,7 +46,7 @@ void load_trampoline_pgtable(void) =20 void __init reserve_real_mode(void) { - phys_addr_t mem; + phys_addr_t mem, limit =3D x86_init.resources.realmode_limit; size_t size =3D real_mode_size_needed(); =20 if (!size) @@ -54,10 +54,9 @@ void __init reserve_real_mode(void) =20 WARN_ON(slab_is_available()); =20 - /* Has to be under 1M so we can execute real-mode AP code. */ - mem =3D memblock_phys_alloc_range(size, PAGE_SIZE, 0, 1<<20); + mem =3D memblock_phys_alloc_range(size, PAGE_SIZE, 0, limit); if (!mem) - pr_info("No sub-1M memory is available for the trampoline\n"); + pr_info("No memory below %pa for the real-mode trampoline\n", &limit); else set_real_mode_mem(mem); =20 --=20 2.43.0 From nobody Sat Feb 7 07:24:30 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B034031B812; Wed, 7 Jan 2026 21:46:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; 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a="69359300" X-IronPort-AV: E=Sophos;i="6.21,209,1763452800"; d="scan'208";a="69359300" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2026 13:46:02 -0800 X-CSE-ConnectionGUID: +FoZx/nvQYyf8uAhytX5qg== X-CSE-MsgGUID: sibWz9pSQxOKz45/U4QUUA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,209,1763452800"; d="scan'208";a="207510919" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2026 13:46:02 -0800 From: Ricardo Neri Date: Wed, 07 Jan 2026 13:44:43 -0800 Subject: [PATCH v8 07/10] x86/hyperv/vtl: Setup the 64-bit trampoline for TDX guests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260107-rneri-wakeup-mailbox-v8-7-2f5b6785f2f5@linux.intel.com> References: <20260107-rneri-wakeup-mailbox-v8-0-2f5b6785f2f5@linux.intel.com> In-Reply-To: <20260107-rneri-wakeup-mailbox-v8-0-2f5b6785f2f5@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767822314; l=2718; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=vhY14NkKZxOjAgHyadn8owqSXQZwp+wSl3FyExPxLjM=; b=imcOffMmJ4D28oznl/JuiSow1i2XcrcdUBwEk9Z6hIfgxUUy70AOosDy2CXgAaeKAmwbNNhZ9 so1rxSIAYuHAy3WNEL7aQ7740cKmCRjPxkPEZCkVD72GGm+Ce9Ml3wX X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= From: Yunhong Jiang The hypervisor is an untrusted entity for TDX guests. It cannot be used to boot secondary CPUs - neither via hypercalls nor the INIT assert, de-assert, plus Start-Up IPI messages. Instead, the platform virtual firmware boots the secondary CPUs and puts them in a state to transfer control to the kernel. This mechanism uses the wakeup mailbox described in the Multiprocessor Wakeup Structure of the ACPI specification. The entry point to the kernel is trampoline_start64. Allocate and setup the trampoline using the default x86_platform callbacks. The platform firmware configures the secondary CPUs in long mode. It is no longer necessary to locate the trampoline under 1MB memory. After handoff from firmware, the trampoline code switches briefly to 32-bit addressing mode, which has an addressing limit of 4GB. Set the upper bound of the trampoline memory accordingly. Reviewed-by: Dexuan Cui Reviewed-by: Michael Kelley Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes in v8: - None Changes in v7: - None Changes in v6: - Added Reviewed-by tag from Dexuan. Thanks! Changes in v5: - None Changes in v4: - Added Reviewed-by tag from Michael. Thanks! Changes in v3: - Added a note regarding there is no need to check for a present paravisor. - Edited commit message for clarity. Changes in v2: - Dropped the function hv_reserve_real_mode(). Instead, used the new members realmode_limit and reserve_bios members of x86_init to set the upper bound of the trampoline memory. (Thomas) --- arch/x86/hyperv/hv_vtl.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index f74199e77133..752101544663 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -68,9 +68,14 @@ void __init hv_vtl_init_platform(void) */ pr_info("Linux runs in Hyper-V Virtual Trust Level %d\n", ms_hyperv.vtl); =20 - x86_platform.realmode_reserve =3D x86_init_noop; - x86_platform.realmode_init =3D x86_init_noop; - real_mode_header =3D &hv_vtl_real_mode_header; + /* There is no paravisor present if we are here. */ + if (hv_isolation_type_tdx()) { + x86_init.resources.realmode_limit =3D SZ_4G; + } else { + x86_platform.realmode_reserve =3D x86_init_noop; + x86_platform.realmode_init =3D x86_init_noop; + real_mode_header =3D &hv_vtl_real_mode_header; + } x86_init.irqs.pre_vector_init =3D x86_init_noop; x86_init.timers.timer_init =3D x86_init_noop; x86_init.resources.probe_roms =3D x86_init_noop; --=20 2.43.0 From nobody Sat Feb 7 07:24:30 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7A8B31ED68; Wed, 7 Jan 2026 21:46:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767822370; cv=none; b=Ec+kJij+L15kFsAQOQR/7Cby+l4MwiEGM1b5Ng9xuJb90bChlGWl7qzF6J8udyJqT6vRBtrEK2NXmDRrvNxWIiSEqByDutwuzZQqx+ox1OSsiAiXSvAypU7nAmdzfPQqx4tlLBZoaty2eqixhwjGLIUq1aZ1TwcU2MO0hYkL0c4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767822370; c=relaxed/simple; bh=75gXCNmWgP9UCQ6UxMfu7Sl0kTqwUzmvTWLhZ8xynLc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aFy5UDaIoHKZ4VBgzzyLewq8FmqXOFZV/9/m/zTDIqoCb1QVRs2pM3+U8feGJru1pokY0Yv+Suv5583CW83StAsPtTpe1Oc9BZgZA15q2NQxdcMs0ZyxJmzlTy+qBQYynCH5GHlPLky3yriaM0PtbseNfzej1yxIQLwWx0Qi7Yc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=aENHfmdk; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="aENHfmdk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1767822368; x=1799358368; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=75gXCNmWgP9UCQ6UxMfu7Sl0kTqwUzmvTWLhZ8xynLc=; b=aENHfmdks903tqhm/PcqaRkZl8Op8dSLqeDfzuPAoP8u2ZfucIY2E8c5 suucaFCnnGz7l4PnN02WDKxO2jgQsAjQbGmRWFhlXZWqWyTuAU0BRLXIQ CyIQmpdt6r5EC6Lkks7Ug4Ip5FZgF816lVPu4D0xz9jX/5482KQT+fwJQ cxgE4s0yi/7RuQFZ2zxQ5XdnnU4vvGKwDs4BX/xGitdD+Mri0oQWqEwIo jS0F0GCEHpuQbozOzaAI5UDgseJyD6EEnlq9sN7CcBzq4Fo7CMnifdcNZ 0p16r/YPUtrdJvYCVWuyXPB26gqobxiOfZYUePl6aZAcla3keEnF2xczO w==; X-CSE-ConnectionGUID: P1ZdbrlQTOugFqZy+Q4QUw== X-CSE-MsgGUID: /JdPCQHxTjW3Ch/5t/iEew== X-IronPort-AV: E=McAfee;i="6800,10657,11664"; a="69359301" X-IronPort-AV: E=Sophos;i="6.21,209,1763452800"; d="scan'208";a="69359301" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2026 13:46:02 -0800 X-CSE-ConnectionGUID: jtyQX7f4R8yD8KlmOHJhww== X-CSE-MsgGUID: B55a4nvUSWay4eYq2HJcaw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,209,1763452800"; d="scan'208";a="207510923" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2026 13:46:02 -0800 From: Ricardo Neri Date: Wed, 07 Jan 2026 13:44:44 -0800 Subject: [PATCH v8 08/10] x86/acpi: Add a helper get the address of the wakeup mailbox Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260107-rneri-wakeup-mailbox-v8-8-2f5b6785f2f5@linux.intel.com> References: <20260107-rneri-wakeup-mailbox-v8-0-2f5b6785f2f5@linux.intel.com> In-Reply-To: <20260107-rneri-wakeup-mailbox-v8-0-2f5b6785f2f5@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767822314; l=2313; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=75gXCNmWgP9UCQ6UxMfu7Sl0kTqwUzmvTWLhZ8xynLc=; b=DQTPnGDhVwgmiG7/0cA/L4oc2UHvc9RSwGoqs/04eMnozRkAXukWXM11mGN2y4wZPdRBI6P9d 1lAsIexyXDgBSdFSRty+S61PrrWwWVndnemGPybQuYrIhGt8rqNr3/I X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= A Hyper-V VTL level 2 guest in a TDX environment needs to map the physical page of the ACPI Multiprocessor Wakeup Structure as private (encrypted). It needs to know the physical address of this structure. Add a helper function to retrieve the address. Suggested-by: Michael Kelley Acked-by: Rafael J. Wysocki (Intel) Signed-off-by: Ricardo Neri --- Changes in v8: - Added Acked-by tag from Rafael. Thanks! Changes in v7: - Moved the added function to arch/x86/kernel/acpi/madt_wakeup.c - Dropped Reviewed-by tags from Dexuan and Michael as this patch changed. Changes in v6: - Added Reviewed-by tag from Dexuan. Thanks! Changes in v5: - None Changes in v4: - Renamed function to acpi_get_mp_wakeup_mailbox_paddr(). - Added Reviewed-by tag from Michael. Thanks! Changes in v3: - Introduced this patch Changes in v2: - N/A --- arch/x86/include/asm/acpi.h | 6 ++++++ arch/x86/kernel/acpi/madt_wakeup.c | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h index 820df375df79..c4e6459bd56b 100644 --- a/arch/x86/include/asm/acpi.h +++ b/arch/x86/include/asm/acpi.h @@ -184,6 +184,7 @@ void __iomem *x86_acpi_os_ioremap(acpi_physical_address= phys, acpi_size size); =20 void acpi_setup_mp_wakeup_mailbox(u64 addr); struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_wakeup_mailbox(void= ); +u64 acpi_get_mp_wakeup_mailbox_paddr(void); =20 #else /* !CONFIG_ACPI */ =20 @@ -210,6 +211,11 @@ static inline struct acpi_madt_multiproc_wakeup_mailbo= x *acpi_get_mp_wakeup_mail return NULL; } =20 +static inline u64 acpi_get_mp_wakeup_mailbox_paddr(void) +{ + return 0; +} + #endif /* !CONFIG_ACPI */ =20 #define ARCH_HAS_POWER_INIT 1 diff --git a/arch/x86/kernel/acpi/madt_wakeup.c b/arch/x86/kernel/acpi/madt= _wakeup.c index 82caf44b45e3..48734e4a6e8f 100644 --- a/arch/x86/kernel/acpi/madt_wakeup.c +++ b/arch/x86/kernel/acpi/madt_wakeup.c @@ -258,3 +258,8 @@ struct acpi_madt_multiproc_wakeup_mailbox *acpi_get_mp_= wakeup_mailbox(void) { return acpi_mp_wake_mailbox; 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07 Jan 2026 13:46:02 -0800 From: Ricardo Neri Date: Wed, 07 Jan 2026 13:44:45 -0800 Subject: [PATCH v8 09/10] x86/hyperv/vtl: Mark the wakeup mailbox page as private Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260107-rneri-wakeup-mailbox-v8-9-2f5b6785f2f5@linux.intel.com> References: <20260107-rneri-wakeup-mailbox-v8-0-2f5b6785f2f5@linux.intel.com> In-Reply-To: <20260107-rneri-wakeup-mailbox-v8-0-2f5b6785f2f5@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Yunhong Jiang , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767822314; l=2880; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=kjCB4miB0DwMRU0Ssua6vnQm6QUYmHXEZjj940X/k1A=; b=IsyeU6Ml8SpVtTl5bGpaN5gY+iub0LMs3HiZpvU/bdnjBsECl7n3Uy1fmLoi2OF8aDQaEguUb V76WgsFuTIkAlXgF5E1WaX3fbqXu7uWzFwCHE/S0N6einmonT1mbP9o X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= From: Yunhong Jiang The current code maps MMIO devices as shared (decrypted) by default in a confidential computing VM. In a TDX environment, secondary CPUs are booted using the Multiprocessor Wakeup Structure defined in the ACPI specification. The virtual firmware and the operating system function in the guest context, without intervention from the VMM. Map the physical memory of the mailbox as private. Use the is_private_mmio() callback. Signed-off-by: Yunhong Jiang Signed-off-by: Ricardo Neri --- Changes in v8: - Included linux/acpi.h to add missing definitions that caused build breaks (kernel test robot) Changes in v7: - Dropped check for !CONFIG_X86_MAILBOX_WAKEUP. The symbol is no longer valid and now we have a stub for !CONFIG_ACPI. - Dropped Reviewed-by tags from Dexuan and Michael as this patch changed. Changes in v6: - Fixed a compile error with !CONFIG_X86_MAILBOX_WAKEUP. - Added Reviewed-by tag from Dexuan. Thanks! Changes in v5: - None Changes in v4: - Updated to use the renamed function acpi_get_mp_wakeup_mailbox_paddr(). - Added Reviewed-by tag from Michael. Thanks! Changes in v3: - Use the new helper function get_mp_wakeup_mailbox_paddr(). - Edited the commit message for clarity. Changes in v2: - Added the helper function within_page() to improve readability - Override the is_private_mmio() callback when detecting a TDX environment. The address of the mailbox is checked in hv_is_private_mmio_tdx(). --- arch/x86/hyperv/hv_vtl.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index 752101544663..2af825f7a447 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -6,6 +6,9 @@ * Saurabh Sengar */ =20 +#include + +#include #include #include #include @@ -59,6 +62,18 @@ static void __noreturn hv_vtl_restart(char __maybe_unus= ed *cmd) hv_vtl_emergency_restart(); } =20 +static inline bool within_page(u64 addr, u64 start) +{ + return addr >=3D start && addr < (start + PAGE_SIZE); +} + +static bool hv_vtl_is_private_mmio_tdx(u64 addr) +{ + u64 mb_addr =3D acpi_get_mp_wakeup_mailbox_paddr(); + + return mb_addr && within_page(addr, mb_addr); +} + void __init hv_vtl_init_platform(void) { /* @@ -71,6 +86,8 @@ void __init hv_vtl_init_platform(void) /* There is no paravisor present if we are here. */ if (hv_isolation_type_tdx()) { x86_init.resources.realmode_limit =3D SZ_4G; + x86_platform.hyper.is_private_mmio =3D hv_vtl_is_private_mmio_tdx; + } else { x86_platform.realmode_reserve =3D x86_init_noop; x86_platform.realmode_init =3D x86_init_noop; --=20 2.43.0 From nobody Sat Feb 7 07:24:30 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC5973016F5; Wed, 7 Jan 2026 21:46:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767822371; cv=none; b=SfZPW3+iGCCgGupSBc7JUd48J6NKLolIgfSFpgiYKmIV9af6esS09V8uPLCMVQWmaVn6PddyYcFI0639Qp5MQ4AbBE3sAMyryOcHaD+/rjLDN7LumyjBX87lI91rdeGTwYZzEwDmTEVLjELL4o6fnXd7XFZrujZTlNkyp7u7D8w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767822371; c=relaxed/simple; bh=fOB9G2GRj0EWRDNGLEY7TkdAbfaGYmLPpeCfoQe1U1s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k5gQUwxVRnLAAalXMnuYDV6nUCj7pPpxdgUhinN6fNoHQ8Vw9JYczJ56Ww2muzEqH+wmpDC/inZ6S8MAjIJcHG9nsbV/iVI3hedlHxqC6CIPZAWDJkegIN7p0xZJf8lyfZdPf3tH1BtWv8YNDzeWGCxWZtyA0FdSjuV5R8C3Cco= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Lq04gOFb; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Lq04gOFb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1767822370; x=1799358370; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=fOB9G2GRj0EWRDNGLEY7TkdAbfaGYmLPpeCfoQe1U1s=; b=Lq04gOFb3mAW7U8Rexa4tCoNryROjINop3Ru+CkLV5hE6i5M08AIaaXL fhCNGqRlxv+1Seq2NWwDQTOsTfqXUPIeZmdnjQjknFr2v+wlVvYsTioiP ZK/ZNr9xe86KmDZRoD2vbOH0gFdj4yvRNjfe06BzpeMsZ/tVhNjd01m1N RU/hdPODeeWizxYSduWxk0Hwj06+6HkI6w870839cfNkAbwXBb8QPfSiJ nc3ihqRWNekbYphFJJnsVNB9Oc9iPAzcSWpwvlDr0Smv+FiiRV8BodngL rSxBwMc2qwOS1rMthV+ECMo/MZZuIM5hJjAc5VsYLE39UhtaJmeKdI7RU A==; X-CSE-ConnectionGUID: qsbELRsOR7qqNVXynpfdxA== X-CSE-MsgGUID: 1pHp7VwUTl+LScDC0qBSTQ== X-IronPort-AV: E=McAfee;i="6800,10657,11664"; a="69359307" X-IronPort-AV: E=Sophos;i="6.21,209,1763452800"; d="scan'208";a="69359307" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2026 13:46:02 -0800 X-CSE-ConnectionGUID: fk+W+ENzRymukqbWqx9EIg== X-CSE-MsgGUID: xd8yU/0BSwSemA26w6iL1Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,209,1763452800"; d="scan'208";a="207510929" Received: from unknown (HELO [172.25.112.21]) ([172.25.112.21]) by fmviesa005.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jan 2026 13:46:03 -0800 From: Ricardo Neri Date: Wed, 07 Jan 2026 13:44:46 -0800 Subject: [PATCH v8 10/10] x86/hyperv/vtl: Use the wakeup mailbox to boot secondary CPUs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260107-rneri-wakeup-mailbox-v8-10-2f5b6785f2f5@linux.intel.com> References: <20260107-rneri-wakeup-mailbox-v8-0-2f5b6785f2f5@linux.intel.com> In-Reply-To: <20260107-rneri-wakeup-mailbox-v8-0-2f5b6785f2f5@linux.intel.com> To: x86@kernel.org, Krzysztof Kozlowski , Conor Dooley , Rob Herring , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Michael Kelley , "Rafael J. Wysocki" Cc: Saurabh Sengar , Chris Oo , "Kirill A. Shutemov" , linux-hyperv@vger.kernel.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Ricardo Neri X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767822314; l=2032; i=ricardo.neri-calderon@linux.intel.com; s=20250602; h=from:subject:message-id; bh=fOB9G2GRj0EWRDNGLEY7TkdAbfaGYmLPpeCfoQe1U1s=; b=L/5OWWSyD5YTqCWqwEplNpYFC1FHa+KpbBhgNXpTVcykzNKodOasRh23B0p6MndBUm1Mk2AHT sLmjHdXdCVQDW140pUWd8N3GVRJbZHyqHgL0taNivhI1bMnxhTZI+ka X-Developer-Key: i=ricardo.neri-calderon@linux.intel.com; a=ed25519; pk=NfZw5SyQ2lxVfmNMaMR6KUj3+0OhcwDPyRzFDH9gY2w= The hypervisor is an untrusted entity for TDX guests. It cannot be used to boot secondary CPUs. The function hv_vtl_wakeup_secondary_cpu() cannot be used. Instead, the virtual firmware boots the secondary CPUs and places them in a state to transfer control to the kernel using the wakeup mailbox. The firmware enumerates the mailbox via either an ACPI table or a DeviceTree node. If the wakeup mailbox is present, the kernel updates the APIC callback wakeup_secondary_cpu_64() to use it. Reviewed-by: Dexuan Cui Reviewed-by: Michael Kelley Signed-off-by: Ricardo Neri --- Changes in v8: - None Changes in v7: - None Changes in v6: - Added Reviewed-by tag from Dexuan. Thanks! Changes in v5: - None Changes in v4: - Added Reviewed-by tag from Michael. Thanks! Changes in v3: - Unconditionally use the wakeup mailbox in a TDX confidential VM. (Michael). - Edited the commit message for clarity. Changes in v2: - None --- arch/x86/hyperv/hv_vtl.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index 2af825f7a447..fa4e7fda2868 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -272,7 +272,15 @@ int __init hv_vtl_early_init(void) panic("XSAVE has to be disabled as it is not supported by this module.\n" "Please add 'noxsave' to the kernel command line.\n"); =20 - apic_update_callback(wakeup_secondary_cpu_64, hv_vtl_wakeup_secondary_cpu= ); + /* + * TDX confidential VMs do not trust the hypervisor and cannot use it to + * boot secondary CPUs. Instead, they will be booted using the wakeup + * mailbox if detected during boot. See setup_arch(). + * + * There is no paravisor present if we are here. + */ + if (!hv_isolation_type_tdx()) + apic_update_callback(wakeup_secondary_cpu_64, hv_vtl_wakeup_secondary_cp= u); =20 return 0; } --=20 2.43.0