From nobody Mon Feb 9 17:23:38 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7604B32E130; Wed, 7 Jan 2026 14:11:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767795086; cv=none; b=a3lcLsxOfPnEUcMQAF0enIJvAEKKMDPzfEVy/LbPgcJV1WAVloftmtxJaSNx258miFJ8cT2inu2DWHH7BveRP6sVUsz9mEgSuhUmLghp430ZlG6tH95hpxQH0RHnbZg8SYZDWrtfiLVXbuK/0fu6XbGDzlprpAsGn8PN/cuDDgg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767795086; c=relaxed/simple; bh=wU1h6uWCj3ZpYYo8ykAc1GiA8TKQVwwg7g5jDBoPMn4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=r7YAI8N2d4CyWDqqj5QQIpPLsT2foeo6nfPkCIVVUSIUROi2NXsVQgu37lz05JoD4lSm43hXv4TjQfXuydjKdNf9OsSYjzFM3l4tw6REwyP6NsiUu4lK3+QNsVhKvLQPLRBv6vc7LdFgXnOsN5FdsefWvdI+pwGBrkquRcaJcRA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DkFLxahz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DkFLxahz" Received: by smtp.kernel.org (Postfix) with ESMTPS id F3243C19424; Wed, 7 Jan 2026 14:11:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1767795086; bh=wU1h6uWCj3ZpYYo8ykAc1GiA8TKQVwwg7g5jDBoPMn4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=DkFLxahzvDG3plnrvYkMfJVuQxWd1Oyphl2LRTZYKkRiCF0f1viMxVvC0jv7PpCl/ sJrGEJigB7tGnUeWyhy+TL9/NwBhm4c5u4HdwRAv4hfrDpWMwiK6vc6GtHolWW9Gx4 EClwmq1gvt/UIo0moRVBHwEu5PnFEbWljQBGqKX5bDe7xw58z9WIn6opIvnXV1rTT5 0COkPrkdvymoiOy6AhaA70TwVyY9QP+dQ95zARI7neIZxmrpG9RxTL/Zbe2milfl5g hWaed1g7Ts5uzSU37JzOYKBWRZ+N1DJxVmXjPb/Sqj52F5ZNi8q3Yb/ZcuIwx/c1tJ /KB5KJYpN9ueg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB27CCFD646; Wed, 7 Jan 2026 14:11:25 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 07 Jan 2026 19:41:25 +0530 Subject: [PATCH v5 3/5] PCI/pwrctrl: Add support for handling PCIe M.2 connectors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260107-pci-m2-v5-3-8173d8a72641@oss.qualcomm.com> References: <20260107-pci-m2-v5-0-8173d8a72641@oss.qualcomm.com> In-Reply-To: <20260107-pci-m2-v5-0-8173d8a72641@oss.qualcomm.com> To: Bjorn Helgaas , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Damien Le Moal , Niklas Cassel , Linus Walleij , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, linux-ide@vger.kernel.org, Manivannan Sadhasivam , Bartosz Golaszewski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3872; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=AO6DA+THdUbk+4mox05j2FvqW5j/957nknRRq0lgeZo=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpXmmLbuanTaixUENX17ESNDeHEkjjUvEDpSHQq OIa/nKMk+OJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaV5piwAKCRBVnxHm/pHO 9Yi1B/0SOYOlEeLDDD9jX9NWp3N+YIh9dJRecwZiEMGM9fNtU2UZGhUw0UksS+n+ZGt38guam1W p0f/qe5dKiVO/AvyJ12bHt/eePY77qkMqMptJt+Q1TGy4ym3x7jl8QwDXcyZLfHtpNUZ3J/wfxC 8YPRzY67gCxUmH7ffcGsiXKtDsmuMM4ltoKJZKB+1jTPfpt1Ll3eaFE0Th6ARW68OwyubaTmVjJ AJsKahYs/3BOZtT+fQkk3aTfmRGi3NB9WwZARsJo1B/a/UkiU3AroFrG9enqF2mA81g+sR1YdMY Yzng0kQP+4EMzqKCiauWJ2qcCsf3fYVwBXvUDhGBcdFGhI/6 X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam Add support for handling the PCIe M.2 connectors as Power Sequencing devices. These connectors are exposed as the Power Sequencing devices as they often support multiple interfaces like PCIe/SATA, USB/UART to the host machine and each interfaces could be driven by different client drivers at the same time. This driver handles the PCIe interface of these connectors. It first checks for the presence of the graph port in the Root Port node with the help of of_graph_is_present() API, if present, it acquires/poweres ON the corresponding pwrseq device. Once the pwrseq device is powered ON, the driver will skip parsing the Root Port/Slot resources and registers with the pwrctrl framework. Reviewed-by: Bartosz Golaszewski Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pwrctrl/Kconfig | 1 + drivers/pci/pwrctrl/slot.c | 35 ++++++++++++++++++++++++++++++----- 2 files changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pwrctrl/Kconfig b/drivers/pci/pwrctrl/Kconfig index e0f999f299bb..cd3aa15bad00 100644 --- a/drivers/pci/pwrctrl/Kconfig +++ b/drivers/pci/pwrctrl/Kconfig @@ -13,6 +13,7 @@ config PCI_PWRCTRL_PWRSEQ =20 config PCI_PWRCTRL_SLOT tristate "PCI Power Control driver for PCI slots" + select POWER_SEQUENCING select PCI_PWRCTRL help Say Y here to enable the PCI Power Control driver to control the power diff --git a/drivers/pci/pwrctrl/slot.c b/drivers/pci/pwrctrl/slot.c index 3320494b62d8..d46c2365208a 100644 --- a/drivers/pci/pwrctrl/slot.c +++ b/drivers/pci/pwrctrl/slot.c @@ -8,8 +8,10 @@ #include #include #include +#include #include #include +#include #include #include =20 @@ -17,12 +19,18 @@ struct pci_pwrctrl_slot_data { struct pci_pwrctrl ctx; struct regulator_bulk_data *supplies; int num_supplies; + struct pwrseq_desc *pwrseq; }; =20 static void devm_pci_pwrctrl_slot_power_off(void *data) { struct pci_pwrctrl_slot_data *slot =3D data; =20 + if (slot->pwrseq) { + pwrseq_power_off(slot->pwrseq); + return; + } + regulator_bulk_disable(slot->num_supplies, slot->supplies); regulator_bulk_free(slot->num_supplies, slot->supplies); } @@ -38,6 +46,20 @@ static int pci_pwrctrl_slot_probe(struct platform_device= *pdev) if (!slot) return -ENOMEM; =20 + if (of_graph_is_present(dev_of_node(dev))) { + slot->pwrseq =3D devm_pwrseq_get(dev, "pcie"); + if (IS_ERR(slot->pwrseq)) + return dev_err_probe(dev, PTR_ERR(slot->pwrseq), + "Failed to get the power sequencer\n"); + + ret =3D pwrseq_power_on(slot->pwrseq); + if (ret) + return dev_err_probe(dev, ret, + "Failed to power-on the device\n"); + + goto skip_resources; + } + ret =3D of_regulator_bulk_get_all(dev, dev_of_node(dev), &slot->supplies); if (ret < 0) { @@ -53,17 +75,20 @@ static int pci_pwrctrl_slot_probe(struct platform_devic= e *pdev) return ret; } =20 - ret =3D devm_add_action_or_reset(dev, devm_pci_pwrctrl_slot_power_off, - slot); - if (ret) - return ret; - clk =3D devm_clk_get_optional_enabled(dev, NULL); if (IS_ERR(clk)) { + regulator_bulk_disable(slot->num_supplies, slot->supplies); + regulator_bulk_free(slot->num_supplies, slot->supplies); return dev_err_probe(dev, PTR_ERR(clk), "Failed to enable slot clock\n"); } =20 +skip_resources: + ret =3D devm_add_action_or_reset(dev, devm_pci_pwrctrl_slot_power_off, + slot); + if (ret) + return ret; + pci_pwrctrl_init(&slot->ctx, dev); =20 ret =3D devm_pci_pwrctrl_device_set_ready(dev, &slot->ctx); --=20 2.48.1