From nobody Sun Feb 8 11:40:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F1A732AAC5; Wed, 7 Jan 2026 14:11:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767795086; cv=none; b=lPiGTCeygRbZ0P4mq5e+WvYjzdXyVL3AyXBCLiJF5R8kmICjDMSB8Emai3hqDOJscLyf2qG2XhxCA6mYGQe2J30MdjiXE0eAMmI26rOqjn4+/jcxrxA3FwzDaB4UesCFOC5K7S0kjs3Sl+dBz1kKzUf96dKgNH/luDEksFwKkiA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767795086; c=relaxed/simple; bh=586xK+Tt3k7/bbGWV0rchSixVB7IEZBKxgz1tfKFOmg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QNg+4whlsYT9BiwCO1yVLoKe+sH9dr33mCe39Wcr+bsjKdEEyk3l35SRQk9bKWlCMctO6GLWsPADvZRApiTtQ/WV1guLlaafvMxFU0UKdI6N1+omaRJQpPOCsKuzxPB+Jh3PpO07dY3eIB9iNYWprmD2G4qoD1j38iewaBp/Y9Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=M+U++E+z; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="M+U++E+z" Received: by smtp.kernel.org (Postfix) with ESMTPS id DE8FEC19421; Wed, 7 Jan 2026 14:11:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1767795086; bh=586xK+Tt3k7/bbGWV0rchSixVB7IEZBKxgz1tfKFOmg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=M+U++E+zmJXnCjwt2Q+renEf+ocL+yNHhLVYF/Jex/lOY3JCKY/s2Cc+FB5wHTBNy 5t1yeei0PO9kxbddOAT2oKfAwazmwWJDDSyEANM5pQA+GiylSLMaGYLXaDxh1XTBZU PHRxF8Dc2Ra2ccYUobBjfDggh7CEVcW4gTve9+DUNAald8XIwzyzHbYFHEb61il/Pk 9A9sqvR1X9JzK31ljcqlpYAI0axSip535+u0VB9ct1ec4jDqkfIOVEDp4CTvQoPctZ Gfad7i7PtOBftiqchxjKNUfGJsAfjKITN5iBYmD6KW7tUhDbDf2ncadxWBl9GQjuDw aKktx/oGqoFHg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEC1DCFD641; Wed, 7 Jan 2026 14:11:25 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 07 Jan 2026 19:41:23 +0530 Subject: [PATCH v5 1/5] dt-bindings: ata: sata: Document the graph port Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260107-pci-m2-v5-1-8173d8a72641@oss.qualcomm.com> References: <20260107-pci-m2-v5-0-8173d8a72641@oss.qualcomm.com> In-Reply-To: <20260107-pci-m2-v5-0-8173d8a72641@oss.qualcomm.com> To: Bjorn Helgaas , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Damien Le Moal , Niklas Cassel , Linus Walleij , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, linux-ide@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=917; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=9i4SXdeQUf4xFNTVF27hrzTgaGj3TYdVJNxV8w9WdaE=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpXmmLGXHl/IauCFQ+UOyeR70ghPTr+GzfjvDCN oQNv7m4UYGJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaV5piwAKCRBVnxHm/pHO 9SvMB/9+LmMbrio/668Iyce2ZVSAg803BhvaWzOavaKxc70H5dpTsdDJo1cHf217cJ4CTMkFNXH 0ZTHra88qnDl2Ot3juCRc8LbCId8gwZR4lsVwVNnm+SxbSZ9Q9ZIRKYJF1Z3XlpRjKGfkryRGBg O/LhI26yewj/bn9ZxSrAyLLETfnVu5YmqMp3E9g9jql6S7WkI8QVbaRnwkJYPzZzqvCxshk/RRt 7R7M49DiqWC3pazK+f/CPo55sfZHgY3iqU3R/G9OsG73s29yfLCV0Q9DALXBTirWfbLNUY1XFfC 3QlfjWUHeGWmqMFqaCBJBGMsvzvcOJqb3szqdbhYHsRc3V8D X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam An external connector like M.2 could expose the SATA interface to the plugin cards. So add the graph port to establish link between the SATA Port and the connector node. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/ata/sata-common.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/ata/sata-common.yaml b/Docum= entation/devicetree/bindings/ata/sata-common.yaml index 58c9342b9925..97cd69ebf331 100644 --- a/Documentation/devicetree/bindings/ata/sata-common.yaml +++ b/Documentation/devicetree/bindings/ata/sata-common.yaml @@ -54,4 +54,7 @@ $defs: each port can have a Port Multiplier attached thus allowing to access more than one drive by means of a single SATA port. =20 + port: + $ref: /schemas/graph.yaml#/properties/port + ... --=20 2.48.1 From nobody Sun Feb 8 11:40:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 760CB32E74F; Wed, 7 Jan 2026 14:11:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260107-pci-m2-v5-2-8173d8a72641@oss.qualcomm.com> References: <20260107-pci-m2-v5-0-8173d8a72641@oss.qualcomm.com> In-Reply-To: <20260107-pci-m2-v5-0-8173d8a72641@oss.qualcomm.com> To: Bjorn Helgaas , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Damien Le Moal , Niklas Cassel , Linus Walleij , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, linux-ide@vger.kernel.org, Manivannan Sadhasivam , Frank Li X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=5628; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=YTQhSamgN1w43R48rC+Jx7Y/pUNa3PeiP09cyA1Kc2U=; b=owGbwMvMwMUYOl/w2b+J574ynlZLYsiMy+yWqvXe33060sNz9/P+46Vla4x/pNzd9uTnpu9nw w0XadqldDIaszAwcjHIiimypC911mr0OH1jSYT6dJhBrEwgUxi4OAVgIsKV7P9TJq36ZsTQsyb1 ddPrsrSyz62tacs8PLuLf35RjWS/7fZ+ZU5jRIXZIp5XN0seWWVw2Svd8SvSzFylULC952Fduay ZCccqr+P6u9eXnnHZHDw/b00eW4rIudfLvWWUncJTQ8NyN6/Nu1Ck3Ocp6W75juGGGOPk/x0Vjp H+xa+uGry0z1SaXPQ8fF3b4dwXC9lkP/fq3c1k2LSoJ0PiWtg+juTPuZbNUfu4Hlvy3Iv1fKQ42 dGx4MZD6Z2N3w5MnbXigbDZjbfyLOL1208Xe+9k1p0t8Og6R2XN/GUtgemun8Wr5l/Y1frb/avG nLDH8xQbE1Wcty7VkCqL2ybzbXZ5Z5nVqnypVVvkmOs6AA== X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam Add the devicetree binding for PCIe M.2 Mechanical Key M connector defined in the PCI Express M.2 Specification, r4.0, sec 5.3. This connector provides interfaces like PCIe and SATA to attach the Solid State Drives (SSDs) to the host machine along with additional interfaces like USB, and SMBus for debugging and supplementary features. The connector provides a primary power supply of 3.3v, along with an optional 1.8v VIO supply for the Adapter I/O buffer circuitry operating at 1.8v sideband signaling. The connector also supplies optional signals in the form of GPIOs for fine grained power management. Reviewed-by: Frank Li Signed-off-by: Manivannan Sadhasivam --- .../bindings/connector/pcie-m2-m-connector.yaml | 133 +++++++++++++++++= ++++ 1 file changed, 133 insertions(+) diff --git a/Documentation/devicetree/bindings/connector/pcie-m2-m-connecto= r.yaml b/Documentation/devicetree/bindings/connector/pcie-m2-m-connector.ya= ml new file mode 100644 index 000000000000..e912ee6f6a59 --- /dev/null +++ b/Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/connector/pcie-m2-m-connector.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PCIe M.2 Mechanical Key M Connector + +maintainers: + - Manivannan Sadhasivam + +description: + A PCIe M.2 M connector node represents a physical PCIe M.2 Mechanical Ke= y M + connector. The Mechanical Key M connectors are used to connect SSDs to t= he + host system over PCIe/SATA interfaces. These connectors also offer optio= nal + interfaces like USB, SMBus. + +properties: + compatible: + const: pcie-m2-m-connector + + vpcie3v3-supply: + description: A phandle to the regulator for 3.3v supply. + + vpcie1v8-supply: + description: A phandle to the regulator for VIO 1.8v supply. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: OF graph bindings modeling the interfaces exposed on the + connector. Since a single connector can have multiple interfaces, ev= ery + interface has an assigned OF graph port number as described below. + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Host interfaces of the connector + + properties: + endpoint@0: + $ref: /schemas/graph.yaml#/properties/endpoint + description: PCIe interface + + endpoint@1: + $ref: /schemas/graph.yaml#/properties/endpoint + description: SATA interface + + anyOf: + - required: + - endpoint@0 + - required: + - endpoint@1 + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: USB 2.0 interface + + i2c-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: SMBus interface + + required: + - port@0 + + clocks: + description: 32.768 KHz Suspend Clock (SUSCLK) input from the host sys= tem to + the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.= 1 for + more details. + maxItems: 1 + + pedet-gpios: + description: GPIO input to PEDET signal. This signal is used by the ho= st + systems to determine the communication protocol that the M.2 card us= es; + SATA signaling (low) or PCIe signaling (high). Refer, PCI Express M.2 + Specification r4.0, sec 3.3.4.2 for more details. + maxItems: 1 + + viocfg-gpios: + description: GPIO output to IO voltage configuration (VIO_CFG) signal.= This + signal is used by the M.2 card to indicate to the host system that t= he + card supports an independent IO voltage domain for the sideband sign= als. + Refer, PCI Express M.2 Specification r4.0, sec 3.1.15.1 for more det= ails. + maxItems: 1 + + pwrdis-gpios: + description: GPIO input to Power Disable (PWRDIS) signal. This signal = is + used by the host system to disable power on the M.2 card. Refer, PCI + Express M.2 Specification r4.0, sec 3.3.5.2 for more details. + maxItems: 1 + + pln-gpios: + description: GPIO output to Power Loss Notification (PLN#) signal. This + signal is use to notify the M.2 card by the host system that the pow= er + loss event is expected to occur. Refer, PCI Express M.2 Specification + r4.0, sec 3.2.17.1 for more details. + maxItems: 1 + + plas3-gpios: + description: GPIO output to Power Loss Acknowledge (PLA_S3#) signal. T= his + signal is used by the M.2 card to notify the host system, the status= of + the M.2 card's preparation for power loss. + maxItems: 1 + +required: + - compatible + - vpcie3v3-supply + +additionalProperties: false + +examples: + # PCI M.2 Key M connector for SSDs with PCIe interface + - | + connector { + compatible =3D "pcie-m2-m-connector"; + vpcie3v3-supply =3D <&vreg_nvme>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + reg =3D <0>; + + endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&pcie6_port0_ep>; + }; + }; + }; + }; --=20 2.48.1 From nobody Sun Feb 8 11:40:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7604B32E130; Wed, 7 Jan 2026 14:11:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260107-pci-m2-v5-3-8173d8a72641@oss.qualcomm.com> References: <20260107-pci-m2-v5-0-8173d8a72641@oss.qualcomm.com> In-Reply-To: <20260107-pci-m2-v5-0-8173d8a72641@oss.qualcomm.com> To: Bjorn Helgaas , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Damien Le Moal , Niklas Cassel , Linus Walleij , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, linux-ide@vger.kernel.org, Manivannan Sadhasivam , Bartosz Golaszewski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3872; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=AO6DA+THdUbk+4mox05j2FvqW5j/957nknRRq0lgeZo=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpXmmLbuanTaixUENX17ESNDeHEkjjUvEDpSHQq OIa/nKMk+OJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaV5piwAKCRBVnxHm/pHO 9Yi1B/0SOYOlEeLDDD9jX9NWp3N+YIh9dJRecwZiEMGM9fNtU2UZGhUw0UksS+n+ZGt38guam1W p0f/qe5dKiVO/AvyJ12bHt/eePY77qkMqMptJt+Q1TGy4ym3x7jl8QwDXcyZLfHtpNUZ3J/wfxC 8YPRzY67gCxUmH7ffcGsiXKtDsmuMM4ltoKJZKB+1jTPfpt1Ll3eaFE0Th6ARW68OwyubaTmVjJ AJsKahYs/3BOZtT+fQkk3aTfmRGi3NB9WwZARsJo1B/a/UkiU3AroFrG9enqF2mA81g+sR1YdMY Yzng0kQP+4EMzqKCiauWJ2qcCsf3fYVwBXvUDhGBcdFGhI/6 X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam Add support for handling the PCIe M.2 connectors as Power Sequencing devices. These connectors are exposed as the Power Sequencing devices as they often support multiple interfaces like PCIe/SATA, USB/UART to the host machine and each interfaces could be driven by different client drivers at the same time. This driver handles the PCIe interface of these connectors. It first checks for the presence of the graph port in the Root Port node with the help of of_graph_is_present() API, if present, it acquires/poweres ON the corresponding pwrseq device. Once the pwrseq device is powered ON, the driver will skip parsing the Root Port/Slot resources and registers with the pwrctrl framework. Reviewed-by: Bartosz Golaszewski Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pwrctrl/Kconfig | 1 + drivers/pci/pwrctrl/slot.c | 35 ++++++++++++++++++++++++++++++----- 2 files changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pwrctrl/Kconfig b/drivers/pci/pwrctrl/Kconfig index e0f999f299bb..cd3aa15bad00 100644 --- a/drivers/pci/pwrctrl/Kconfig +++ b/drivers/pci/pwrctrl/Kconfig @@ -13,6 +13,7 @@ config PCI_PWRCTRL_PWRSEQ =20 config PCI_PWRCTRL_SLOT tristate "PCI Power Control driver for PCI slots" + select POWER_SEQUENCING select PCI_PWRCTRL help Say Y here to enable the PCI Power Control driver to control the power diff --git a/drivers/pci/pwrctrl/slot.c b/drivers/pci/pwrctrl/slot.c index 3320494b62d8..d46c2365208a 100644 --- a/drivers/pci/pwrctrl/slot.c +++ b/drivers/pci/pwrctrl/slot.c @@ -8,8 +8,10 @@ #include #include #include +#include #include #include +#include #include #include =20 @@ -17,12 +19,18 @@ struct pci_pwrctrl_slot_data { struct pci_pwrctrl ctx; struct regulator_bulk_data *supplies; int num_supplies; + struct pwrseq_desc *pwrseq; }; =20 static void devm_pci_pwrctrl_slot_power_off(void *data) { struct pci_pwrctrl_slot_data *slot =3D data; =20 + if (slot->pwrseq) { + pwrseq_power_off(slot->pwrseq); + return; + } + regulator_bulk_disable(slot->num_supplies, slot->supplies); regulator_bulk_free(slot->num_supplies, slot->supplies); } @@ -38,6 +46,20 @@ static int pci_pwrctrl_slot_probe(struct platform_device= *pdev) if (!slot) return -ENOMEM; =20 + if (of_graph_is_present(dev_of_node(dev))) { + slot->pwrseq =3D devm_pwrseq_get(dev, "pcie"); + if (IS_ERR(slot->pwrseq)) + return dev_err_probe(dev, PTR_ERR(slot->pwrseq), + "Failed to get the power sequencer\n"); + + ret =3D pwrseq_power_on(slot->pwrseq); + if (ret) + return dev_err_probe(dev, ret, + "Failed to power-on the device\n"); + + goto skip_resources; + } + ret =3D of_regulator_bulk_get_all(dev, dev_of_node(dev), &slot->supplies); if (ret < 0) { @@ -53,17 +75,20 @@ static int pci_pwrctrl_slot_probe(struct platform_devic= e *pdev) return ret; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260107-pci-m2-v5-4-8173d8a72641@oss.qualcomm.com> References: <20260107-pci-m2-v5-0-8173d8a72641@oss.qualcomm.com> In-Reply-To: <20260107-pci-m2-v5-0-8173d8a72641@oss.qualcomm.com> To: Bjorn Helgaas , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Damien Le Moal , Niklas Cassel , Linus Walleij , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, linux-ide@vger.kernel.org, Manivannan Sadhasivam , Bartosz Golaszewski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1400; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=Z2MQcMtEDf0+MlOwlvmKClr02SMu0Uf8mDR8S4+Fr7o=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpXmmLZq2kb6DM7zBcdz1FY3Cif3hxtq/XSQwI+ 02g1S1XVsOJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaV5piwAKCRBVnxHm/pHO 9YZGB/9hv+uW/q1uV59gnaGWSsqH2KwEbZM5xLBzYu0WLRnzXRK9tq6UiXt8lBZ1XflVAeHLJmO Kia1fraxxiXy5mAkL8eZzqT6+FaJ+YP5oh05CunSpjW/DZfmc3q+z1UC8PyHLYe1AZe99/R8/Of u2x241hLwkSil9GOKtHKBUZmmbBubq3j90Gcdwg8KpFUAwFLkofcsWdAuczj9QcFO6Y3Rz3+N2F 9dv33xFcToBS2ijLzADdLDx0k4ciCNfcCRXs2zPUWHKTgTGP+BcdYNWTi4RsRDEf6GCAfEfEwF9 9V4nuJmUyCQK+MLHwvMhqa9w1nd3udNHlJ/znauE2U7qdTLy X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam The devicetree node of the PCIe Root Port/Slot could have the graph port to link the PCIe M.2 connector node. Since the M.2 connectors are modelled as Power Sequencing devices, they need to be controlled by the pwrctrl driver as like the Root Port/Slot supplies. Hence, create the pwrctrl device if the graph port is found in the node. Reviewed-by: Bartosz Golaszewski Signed-off-by: Manivannan Sadhasivam --- drivers/pci/probe.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 41183aed8f5d..cd7efd20a74a 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -2585,7 +2586,7 @@ static struct platform_device *pci_pwrctrl_create_dev= ice(struct pci_bus *bus, in * not. This is decided based on at least one of the power supplies * being defined in the devicetree node of the device. */ - if (!of_pci_supply_present(np)) { + if (!of_pci_supply_present(np) && !of_graph_is_present(np)) { pr_debug("PCI/pwrctrl: Skipping OF node: %s\n", np->name); goto err_put_of_node; } --=20 2.48.1 From nobody Sun Feb 8 11:40:35 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD906331A46; Wed, 7 Jan 2026 14:11:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767795086; cv=none; b=Z4j0Tynk6wPb5MOEDjdpkn65R76hY7R2ETySdNkIMOEmggICORVoQ3Jw45j+jvJz4qYk4ziqfqaMAoL5KZanBW1RR9wwARQ4v8uAaf1TtVWxARDNuOLBlR/hv7DT+w3DbgUs4Ybp8dl9JIL/qkPfxIiVIEmVvoydSK2kec1STds= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767795086; c=relaxed/simple; bh=XwVyKvloCickKIupGifF7yuIjrVZYEDak/SyKG5qnog=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eFwnQ83rGzzkrunz7umQL4leYpIC3e+KegElF6ioRuM61unKChBApFzEqRchDcGDMhNgC5M8Dapi2Fol9U6s98gdJQH89jjZZ2kOA5Gp1+DMPToe0lwwxpSRRBkaMU8ogYvHQWO79xcFwFPxKwfNrzI03AwRhD4fKxCPfT/LewM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XPzz7upi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XPzz7upi" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1A124C2BC9E; Wed, 7 Jan 2026 14:11:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1767795086; bh=XwVyKvloCickKIupGifF7yuIjrVZYEDak/SyKG5qnog=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=XPzz7upi6wknkQZun8ZNiHm1ANCzjoOj+i0yX6AKzSVM1f4E3uSXclLvAyMBgBXk3 yPXbxud9WAwO4n0RxOKXLQLzxRTWF9pkPL5ZLCQs0G1ax1PAqPOe4o9TcLTrtwmbQ0 lsIaKIFzWbVuvtfRM/oNmd4nRPmtOdB8Lfl52Ppz+EtoLIGHurYdMA5tFs8/zL+kH2 xErHyz5DplNX/u72rN697/kaC/ktmPbctElorhT/JYlkbBOg7qZMVBiIVB7ax6idwZ lt2V9USUD0aKtAvx3MqmP4nbuA1jfKayZCpZUUDRgf6VR9oRGUfho8nSwXDm0HucrH VpuKm0krHzIAw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 109DFCFD647; Wed, 7 Jan 2026 14:11:26 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Wed, 07 Jan 2026 19:41:27 +0530 Subject: [PATCH v5 5/5] power: sequencing: Add the Power Sequencing driver for the PCIe M.2 connectors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260107-pci-m2-v5-5-8173d8a72641@oss.qualcomm.com> References: <20260107-pci-m2-v5-0-8173d8a72641@oss.qualcomm.com> In-Reply-To: <20260107-pci-m2-v5-0-8173d8a72641@oss.qualcomm.com> To: Bjorn Helgaas , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Damien Le Moal , Niklas Cassel , Linus Walleij , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, linux-ide@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7839; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=ozwbSbXg0129q31uwPEZPEFupIS0sT29S7CybwHBuR4=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpXmmMOKotm7Invr6pw7wYUmqpa9qZHY6R8kuiM ulDavXHnAiJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaV5pjAAKCRBVnxHm/pHO 9RL+B/44vHuZPYOwFq3QIVtLc7E3gvXBbgTII/xat+kENiTaxYW8FEA88uclERV9DgCEX+zdZNy IWP3wRVTnE6PnIW8mFtbiHBlBOYTstVy8X6PK66Pepv50/q/EB1AzMzk4/fFXP6xCsCwLcR8fsg cjY7/cdjQ2HtETW5JRLnFQE6B3amVv9ItkxCs4G7CyEd+UQPtE+4GTYTc2095KSn6qpMKzDrHbR Y3ZWivfppB15ss9DoN5E0zLW55IkV72ZUs1Cd2D1eb8m2emjy1rmvMuqECCWlKeZwoH1WZ5YURM g//ZwzmwXLuoZcJFGa1/R9e+bHfBaLjbDF6/P2JesHumLoNF X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam This driver is used to control the PCIe M.2 connectors of different Mechanical Keys attached to the host machines and supporting different interfaces like PCIe/SATA, USB/UART etc... Currently, this driver supports only the Mechanical Key M connectors with PCIe interface. The driver also only supports driving the mandatory 3.3v and optional 1.8v power supplies. The optional signals of the Key M connectors are not currently supported. Signed-off-by: Manivannan Sadhasivam --- MAINTAINERS | 7 ++ drivers/power/sequencing/Kconfig | 8 ++ drivers/power/sequencing/Makefile | 1 + drivers/power/sequencing/pwrseq-pcie-m2.c | 169 ++++++++++++++++++++++++++= ++++ 4 files changed, 185 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5b11839cba9d..2eb7b6d26573 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20791,6 +20791,13 @@ F: Documentation/driver-api/pwrseq.rst F: drivers/power/sequencing/ F: include/linux/pwrseq/ =20 +PCIE M.2 POWER SEQUENCING +M: Manivannan Sadhasivam +L: linux-pci@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml +F: drivers/power/sequencing/pwrseq-pcie-m2.c + POWER STATE COORDINATION INTERFACE (PSCI) M: Mark Rutland M: Lorenzo Pieralisi diff --git a/drivers/power/sequencing/Kconfig b/drivers/power/sequencing/Kc= onfig index 280f92beb5d0..f5fff84566ba 100644 --- a/drivers/power/sequencing/Kconfig +++ b/drivers/power/sequencing/Kconfig @@ -35,4 +35,12 @@ config POWER_SEQUENCING_TH1520_GPU GPU. This driver handles the complex clock and reset sequence required to power on the Imagination BXM GPU on this platform. =20 +config POWER_SEQUENCING_PCIE_M2 + tristate "PCIe M.2 connector power sequencing driver" + depends on OF || COMPILE_TEST + help + Say Y here to enable the power sequencing driver for PCIe M.2 + connectors. This driver handles the power sequencing for the M.2 + connectors exposing multiple interfaces like PCIe, SATA, UART, etc... + endif diff --git a/drivers/power/sequencing/Makefile b/drivers/power/sequencing/M= akefile index 96c1cf0a98ac..0911d4618298 100644 --- a/drivers/power/sequencing/Makefile +++ b/drivers/power/sequencing/Makefile @@ -5,3 +5,4 @@ pwrseq-core-y :=3D core.o =20 obj-$(CONFIG_POWER_SEQUENCING_QCOM_WCN) +=3D pwrseq-qcom-wcn.o obj-$(CONFIG_POWER_SEQUENCING_TH1520_GPU) +=3D pwrseq-thead-gpu.o +obj-$(CONFIG_POWER_SEQUENCING_PCIE_M2) +=3D pwrseq-pcie-m2.o diff --git a/drivers/power/sequencing/pwrseq-pcie-m2.c b/drivers/power/sequ= encing/pwrseq-pcie-m2.c new file mode 100644 index 000000000000..e01e19123415 --- /dev/null +++ b/drivers/power/sequencing/pwrseq-pcie-m2.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct pwrseq_pcie_m2_pdata { + const struct pwrseq_target_data **targets; +}; + +struct pwrseq_pcie_m2_ctx { + struct pwrseq_device *pwrseq; + struct device_node *of_node; + const struct pwrseq_pcie_m2_pdata *pdata; + struct regulator_bulk_data *regs; + size_t num_vregs; + struct notifier_block nb; +}; + +static int pwrseq_pcie_m2_m_vregs_enable(struct pwrseq_device *pwrseq) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + return regulator_bulk_enable(ctx->num_vregs, ctx->regs); +} + +static int pwrseq_pcie_m2_m_vregs_disable(struct pwrseq_device *pwrseq) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + + return regulator_bulk_disable(ctx->num_vregs, ctx->regs); +} + +static const struct pwrseq_unit_data pwrseq_pcie_m2_vregs_unit_data =3D { + .name =3D "regulators-enable", + .enable =3D pwrseq_pcie_m2_m_vregs_enable, + .disable =3D pwrseq_pcie_m2_m_vregs_disable, +}; + +static const struct pwrseq_unit_data *pwrseq_pcie_m2_m_unit_deps[] =3D { + &pwrseq_pcie_m2_vregs_unit_data, + NULL +}; + +static const struct pwrseq_unit_data pwrseq_pcie_m2_m_pcie_unit_data =3D { + .name =3D "pcie-enable", + .deps =3D pwrseq_pcie_m2_m_unit_deps, +}; + +static const struct pwrseq_target_data pwrseq_pcie_m2_m_pcie_target_data = =3D { + .name =3D "pcie", + .unit =3D &pwrseq_pcie_m2_m_pcie_unit_data, +}; + +static const struct pwrseq_target_data *pwrseq_pcie_m2_m_targets[] =3D { + &pwrseq_pcie_m2_m_pcie_target_data, + NULL +}; + +static const struct pwrseq_pcie_m2_pdata pwrseq_pcie_m2_m_of_data =3D { + .targets =3D pwrseq_pcie_m2_m_targets, +}; + +static int pwrseq_pcie_m2_match(struct pwrseq_device *pwrseq, + struct device *dev) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D pwrseq_device_get_drvdata(pwrseq); + struct device_node *endpoint __free(device_node) =3D NULL; + + /* + * Traverse the 'remote-endpoint' nodes and check if the remote node's + * parent matches the OF node of 'dev'. + */ + for_each_endpoint_of_node(ctx->of_node, endpoint) { + struct device_node *remote __free(device_node) =3D + of_graph_get_remote_port_parent(endpoint); + if (remote && (remote =3D=3D dev_of_node(dev))) + return PWRSEQ_MATCH_OK; + } + + return PWRSEQ_NO_MATCH; +} + +static void pwrseq_pcie_free_resources(void *data) +{ + struct pwrseq_pcie_m2_ctx *ctx =3D data; + + regulator_bulk_free(ctx->num_vregs, ctx->regs); +} + +static int pwrseq_pcie_m2_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pwrseq_pcie_m2_ctx *ctx; + struct pwrseq_config config =3D {}; + int ret; + + ctx =3D devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->of_node =3D of_node_get(dev->of_node); + ctx->pdata =3D device_get_match_data(dev); + if (!ctx->pdata) + return dev_err_probe(dev, -ENODEV, + "Failed to obtain platform data\n"); + + /* + * Currently, of_regulator_bulk_get_all() is the only regulator API that + * allows to get all supplies in the devicetree node without manually + * specifying them. + */ + ret =3D of_regulator_bulk_get_all(dev, dev_of_node(dev), &ctx->regs); + if (ret < 0) + return dev_err_probe(dev, ret, + "Failed to get all regulators\n"); + + ctx->num_vregs =3D ret; + + ret =3D devm_add_action_or_reset(dev, pwrseq_pcie_free_resources, ctx); + if (ret) + return ret; + + config.parent =3D dev; + config.owner =3D THIS_MODULE; + config.drvdata =3D ctx; + config.match =3D pwrseq_pcie_m2_match; + config.targets =3D ctx->pdata->targets; + + ctx->pwrseq =3D devm_pwrseq_device_register(dev, &config); + if (IS_ERR(ctx->pwrseq)) + return dev_err_probe(dev, PTR_ERR(ctx->pwrseq), + "Failed to register the power sequencer\n"); + + return 0; +} + +static const struct of_device_id pwrseq_pcie_m2_of_match[] =3D { + { + .compatible =3D "pcie-m2-m-connector", + .data =3D &pwrseq_pcie_m2_m_of_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, pwrseq_pcie_m2_of_match); + +static struct platform_driver pwrseq_pcie_m2_driver =3D { + .driver =3D { + .name =3D "pwrseq-pcie-m2", + .of_match_table =3D pwrseq_pcie_m2_of_match, + }, + .probe =3D pwrseq_pcie_m2_probe, +}; +module_platform_driver(pwrseq_pcie_m2_driver); + +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_DESCRIPTION("Power Sequencing driver for PCIe M.2 connector"); +MODULE_LICENSE("GPL"); --=20 2.48.1