From nobody Tue Feb 10 00:59:12 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E7FE325736 for ; Wed, 7 Jan 2026 09:43:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767779038; cv=none; b=PW22KQZAUIqI7hd8fTn6D8k54Ucz2zQIPCnaFO38+uPv+7bytM3TeZl3xipUjSmCnuUmmsUTyjIG/xq4VpTNTGfAmrXHsbV0qGKXL6X3AVcGEoGUu4F7QLRXT+VZvmTETCcHqJBn5pivVks8fRcBfzFuochNFgZc+YPc/3SYfVY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767779038; c=relaxed/simple; bh=PHR9cjR2LfkJwaJ1Ww/GoV2R1RC5ssU8Xkxynjw4SCU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XjYGNOWblcv7dZDBMEXbXR0b3l8AUytJa8csquykl1MOvbVocB8dgp5HUX5JXn3qcFr3g6ycCdd0Gs42GhEjMbn28mtq/Bn4Gf5jd/EDBd0xcV+UomFlBMG+Hj6uwyaPx+MB9Lezwkg+cWYuztpJH506VQdx72UAJW3dqcA6IXA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=brSDKPhY; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=LyoHiZw7; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="brSDKPhY"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="LyoHiZw7" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6076tHSm2378917 for ; Wed, 7 Jan 2026 09:43:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= B2i1KRiPrGnh4D4V6w8OHvKnnJ/w2uRSe8N/TBLImhw=; b=brSDKPhYWf/hJAQS Cmf3rKpkqQ0AvfB+j0yILipCosgLDn4urxbvzZxYbXc/uNQDFIumIHBz/u55MDbj TXsbvir5J2lbKs0VReI1Vk/X262B6jsAmkDU1+0El14Z2RLUqS9q5D7/YgCxgqw0 fHOSkkYm1OIDLBKMmlhNBZOaIidznYanQf+WP2MLXXluzKaKZqigN/xbiAn77ZNU /hhtfDcm+j+6LYpG95qM1Y9lGw8V50Dp30WJ29aHWyFCVAiSSw6A7B+5Qizpxzfo AoTAV2NpXkUIJw18MRjdayBaNbXseGIyJQUzqI0X8liwtL+KP6GqbRV3u5WyKIkU l7pvRw== Received: from mail-pf1-f197.google.com (mail-pf1-f197.google.com [209.85.210.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bhjn4rhrn-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 07 Jan 2026 09:43:56 +0000 (GMT) Received: by mail-pf1-f197.google.com with SMTP id d2e1a72fcca58-7b9ef46df43so2140913b3a.1 for ; Wed, 07 Jan 2026 01:43:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1767779036; x=1768383836; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=B2i1KRiPrGnh4D4V6w8OHvKnnJ/w2uRSe8N/TBLImhw=; b=LyoHiZw7v0/fGObTW5178KHugKHYTOVrwFD5GJeMyGIrfO8n4nNDtPhT8929rdTUK3 4q8NNrfPMtaaoD07uFKAzcVmHXlTAgP8pI39G12YhEAbST3WpWSCS1zuBPNl5thmgDGo G+/CCbJkWd7XVbOdn894KA+RDiEi/dJ/N1gz6elSU8xFdx4dy2xWIWQrtw0FWdj8NSJB VQFdeHvSgNdRzwWvYppIVL+v9ok12zVtwbvyWSOEkn88D9s5KrGXOPGn7BaKgp2BOptD iURz03O5/RmvvKzG39/lpCl562CcqE0UJkK4L1GJPFpwnlVVzrJTlgQNsIx/3GcFI0cT cFMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767779036; x=1768383836; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=B2i1KRiPrGnh4D4V6w8OHvKnnJ/w2uRSe8N/TBLImhw=; b=h7rHFXjtFEhX65hwIS5iOBoD2qX2u/PdpB96JYYB+h8kn+mYFTjGfImaYwB57Kfv1H XjZ89ryqn9BHr5Ysk3lAnajeQ/BzlGsps+sX8QlNagBvZGMSUXP19edBj3Cjwdkz3/yW FbDzPF05Tl0fwgqyzSPwu/9xELE5/lGD29wS9fLl6EPHFt1EyV+EFkUA+LdHgnEZnZqL SQiZ9tfp7yrbQVfHz4RW3+VBkyRMfDE+txax63VghjJx9/gMXcT+0ST2QNFKLKEtIoIz 6yAsYO79hEXZ2VUfuWpH7L+1w2SyvOYFwPJ+09tPReKx6h03fnQnOthx0ucOhodi3aDi OsnA== X-Forwarded-Encrypted: i=1; AJvYcCVtJtpcexuVUzrzhZrec6YFK69+fTEBN2+cRjwzJy2hCWpn7jXEjoWhG2W4Zn4tTlrJQyn8o2JEHdnb9Cs=@vger.kernel.org X-Gm-Message-State: AOJu0Yzpcy6fuCHfpvD21jD+Pi/NFQyXsq7Hgy+mTt63TBSQsdgKXS08 t+3PcnDxFQpBy0x6omtCUsjN6IZhr7+c2A3Oe4ZW5I3i4kObYvGxzcehUNQ0mPbUifYPH69xmK0 OV0NE2fzw6zIClQJzHg7y75R0FO7Mbq+wd6F38+j58wbYbu4qiCq3EbzREdCAv281Wmw= X-Gm-Gg: AY/fxX64/DaFclzTHqZLGMzUn2zKWRBEbm24xaVZ88izNZG/Oms/mVIvoMXbzEVV3kZ 2LRh/st+Ezro1+FjogWdxxQrfENE2Qc300o1Bo+KjlkfwJa/sBhXFrfYV+chsl9LOy13d3gsIu7 /Ph9DYwAHsIPJw0T1u6zHvAprjpod5XoUFce8iGwEoyrkcHVgGePHoYfU8pb44MCBC1nd66KL+9 Sc4LwulmPimOxm2snTzms2hrUdbh4KfM8V1A+8oXvfp7UDNfMnD+5sBESBvEYzUrClMXSLlAFcr +skdWLb0wi6ZgfFoLcy16Yxb+Kx6Yb3b4XRJAP8bZUfHvJIJ+V7umlurRBaSsA7hPSRVpBkrYr1 bOL7q86O7CW7cFkCzrFQSC11x/vggF2g6hA== X-Received: by 2002:a05:6a00:4305:b0:7b9:7f18:c716 with SMTP id d2e1a72fcca58-81b7eb28136mr1875672b3a.1.1767779035786; Wed, 07 Jan 2026 01:43:55 -0800 (PST) X-Google-Smtp-Source: AGHT+IGReT0Ao5bYnnyv1SHQu62L/LC7HN0YYIysBe16F298SkWzSul3y+K58RJkn0L3o9k16sKPLg== X-Received: by 2002:a05:6a00:4305:b0:7b9:7f18:c716 with SMTP id d2e1a72fcca58-81b7eb28136mr1875646b3a.1.1767779035301; Wed, 07 Jan 2026 01:43:55 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-819bafe9568sm4472944b3a.15.2026.01.07.01.43.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Jan 2026 01:43:54 -0800 (PST) From: Taniya Das Date: Wed, 07 Jan 2026 15:13:08 +0530 Subject: [PATCH v3 05/11] dt-bindings: clock: qcom: Add support for CAMCC for Kaanapali Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260107-kaanapali-mmcc-v3-v3-5-8e10adc236a8@oss.qualcomm.com> References: <20260107-kaanapali-mmcc-v3-v3-0-8e10adc236a8@oss.qualcomm.com> In-Reply-To: <20260107-kaanapali-mmcc-v3-v3-0-8e10adc236a8@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Maxime Coquelin , Alexandre Torgue , Vladimir Zapolskiy , Jagadeesh Kona , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Taniya Das , Krzysztof Kozlowski X-Mailer: b4 0.15-dev-aa3f6 X-Authority-Analysis: v=2.4 cv=LJhrgZW9 c=1 sm=1 tr=0 ts=695e2adc cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=M9E809UxJf-Bpjq6rgYA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA3MDA3OCBTYWx0ZWRfX1MpXNPTVBDjT +DZ0L3UEOVP4GbKB7TSkieEHRF75oy2pU4dJeXgIlRtHxtMtjhnTD25KWuu0TPwul1fG0ikE5kf jOXls3zYm4u47wOeE5G4xWcRtQXmV+ouwmgYpO2dt1MMzIbTkLV+9xdX3bU+O65wIVNtLuml2K0 Jp+D/JT9uIMUIPdMAG74d2uC6ykw6gNDJT7HjPA+84Uen/vWl4VWPG4VC8LHrt5O0MCj/bAf4bQ KivI47Uul8ON+5RGGWqvMX7OepB4BcVOuxTfIf3A8xB26JXx8xwHas9d2pPiYSKbnH2BEycMyds Ngajy+oY7N9evVf55CMq0zku1CdQHt3IQ3vqntNDmusp1F7ezOkONjoip8HFOe+1uDATvEz1UEW 9iPoa9fZ9sK0QPX7ag0Y6NquMtmVHhx2PiZUWmt7EsyDxrU6sfyPT6wLtSE3MKwoLiry26mg3i+ pwcYC09Zv86k2I/wtDg== X-Proofpoint-GUID: 0Bau4dSZHkCPWTEvAhz43XYQbI9f6KIo X-Proofpoint-ORIG-GUID: 0Bau4dSZHkCPWTEvAhz43XYQbI9f6KIo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-06_03,2026-01-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 adultscore=0 impostorscore=0 suspectscore=0 clxscore=1015 spamscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601070078 Update the compatible and the bindings for CAMCC support on Kaanapali SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Taniya Das --- .../bindings/clock/qcom,sm8450-camcc.yaml | 6 + .../clock/qcom,kaanapali-cambistmclkcc.h | 33 +++++ include/dt-bindings/clock/qcom,kaanapali-camcc.h | 147 +++++++++++++++++= ++++ 3 files changed, 186 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml= b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index c1e06f39431e68a3cd2f6c2dba84be2a3c143bb1..3ec9bf4d82ad3b0fbb3e58fe312= a416b3580c30c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -15,6 +15,8 @@ description: | domains on SM8450. =20 See also: + include/dt-bindings/clock/qcom,kaanapali-camcc.h + include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h include/dt-bindings/clock/qcom,sm8450-camcc.h include/dt-bindings/clock/qcom,sm8550-camcc.h include/dt-bindings/clock/qcom,sm8650-camcc.h @@ -22,6 +24,8 @@ description: | properties: compatible: enum: + - qcom,kaanapali-cambistmclkcc + - qcom,kaanapali-camcc - qcom,sm8450-camcc - qcom,sm8475-camcc - qcom,sm8550-camcc @@ -63,6 +67,8 @@ allOf: compatible: contains: enum: + - qcom,kaanapali-cambistmclkcc + - qcom,kaanapali-camcc - qcom,sc8280xp-camcc - qcom,sm8450-camcc - qcom,sm8550-camcc diff --git a/include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h b/inc= lude/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h new file mode 100644 index 0000000000000000000000000000000000000000..ddb083b5289ecc5ddbf9ce0b8af= a5e2b3bd7ccad --- /dev/null +++ b/include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_BIST_MCLK_CC_KAANAPALI_H +#define _DT_BINDINGS_CLK_QCOM_CAM_BIST_MCLK_CC_KAANAPALI_H + +/* CAM_BIST_MCLK_CC clocks */ +#define CAM_BIST_MCLK_CC_DEBUG_CLK 0 +#define CAM_BIST_MCLK_CC_DEBUG_DIV_CLK_SRC 1 +#define CAM_BIST_MCLK_CC_MCLK0_CLK 2 +#define CAM_BIST_MCLK_CC_MCLK0_CLK_SRC 3 +#define CAM_BIST_MCLK_CC_MCLK1_CLK 4 +#define CAM_BIST_MCLK_CC_MCLK1_CLK_SRC 5 +#define CAM_BIST_MCLK_CC_MCLK2_CLK 6 +#define CAM_BIST_MCLK_CC_MCLK2_CLK_SRC 7 +#define CAM_BIST_MCLK_CC_MCLK3_CLK 8 +#define CAM_BIST_MCLK_CC_MCLK3_CLK_SRC 9 +#define CAM_BIST_MCLK_CC_MCLK4_CLK 10 +#define CAM_BIST_MCLK_CC_MCLK4_CLK_SRC 11 +#define CAM_BIST_MCLK_CC_MCLK5_CLK 12 +#define CAM_BIST_MCLK_CC_MCLK5_CLK_SRC 13 +#define CAM_BIST_MCLK_CC_MCLK6_CLK 14 +#define CAM_BIST_MCLK_CC_MCLK6_CLK_SRC 15 +#define CAM_BIST_MCLK_CC_MCLK7_CLK 16 +#define CAM_BIST_MCLK_CC_MCLK7_CLK_SRC 17 +#define CAM_BIST_MCLK_CC_PLL0 18 +#define CAM_BIST_MCLK_CC_PLL_TEST_CLK 19 +#define CAM_BIST_MCLK_CC_PLL_TEST_DIV_CLK_SRC 20 +#define CAM_BIST_MCLK_CC_SLEEP_CLK 21 + +#endif diff --git a/include/dt-bindings/clock/qcom,kaanapali-camcc.h b/include/dt-= bindings/clock/qcom,kaanapali-camcc.h new file mode 100644 index 0000000000000000000000000000000000000000..58835136b356a558f001fa8ff74= a42ae698734bf --- /dev/null +++ b/include/dt-bindings/clock/qcom,kaanapali-camcc.h @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_KAANAPALI_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_KAANAPALI_H + +/* CAM_CC clocks */ +#define CAM_CC_CAM_TOP_AHB_CLK 0 +#define CAM_CC_CAM_TOP_FAST_AHB_CLK 1 +#define CAM_CC_CAMNOC_DCD_XO_CLK 2 +#define CAM_CC_CAMNOC_NRT_AXI_CLK 3 +#define CAM_CC_CAMNOC_NRT_CRE_CLK 4 +#define CAM_CC_CAMNOC_NRT_IPE_NPS_CLK 5 +#define CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK 6 +#define CAM_CC_CAMNOC_RT_AXI_CLK 7 +#define CAM_CC_CAMNOC_RT_AXI_CLK_SRC 8 +#define CAM_CC_CAMNOC_RT_IFE_LITE_CLK 9 +#define CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK 10 +#define CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK 11 +#define CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK 12 +#define CAM_CC_CAMNOC_XO_CLK 13 +#define CAM_CC_CCI_0_CLK 14 +#define CAM_CC_CCI_0_CLK_SRC 15 +#define CAM_CC_CCI_1_CLK 16 +#define CAM_CC_CCI_1_CLK_SRC 17 +#define CAM_CC_CCI_2_CLK 18 +#define CAM_CC_CCI_2_CLK_SRC 19 +#define CAM_CC_CORE_AHB_CLK 20 +#define CAM_CC_CPHY_RX_CLK_SRC 21 +#define CAM_CC_CRE_AHB_CLK 22 +#define CAM_CC_CRE_CLK 23 +#define CAM_CC_CRE_CLK_SRC 24 +#define CAM_CC_CSI0PHYTIMER_CLK 25 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 26 +#define CAM_CC_CSI1PHYTIMER_CLK 27 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 28 +#define CAM_CC_CSI2PHYTIMER_CLK 29 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 30 +#define CAM_CC_CSI3PHYTIMER_CLK 31 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 32 +#define CAM_CC_CSI4PHYTIMER_CLK 33 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 34 +#define CAM_CC_CSI5PHYTIMER_CLK 35 +#define CAM_CC_CSI5PHYTIMER_CLK_SRC 36 +#define CAM_CC_CSID_CLK 37 +#define CAM_CC_CSID_CLK_SRC 38 +#define CAM_CC_CSID_CSIPHY_RX_CLK 39 +#define CAM_CC_CSIPHY0_CLK 40 +#define CAM_CC_CSIPHY1_CLK 41 +#define CAM_CC_CSIPHY2_CLK 42 +#define CAM_CC_CSIPHY3_CLK 43 +#define CAM_CC_CSIPHY4_CLK 44 +#define CAM_CC_CSIPHY5_CLK 45 +#define CAM_CC_DRV_AHB_CLK 46 +#define CAM_CC_DRV_XO_CLK 47 +#define CAM_CC_FAST_AHB_CLK_SRC 48 +#define CAM_CC_GDSC_CLK 49 +#define CAM_CC_ICP_0_AHB_CLK 50 +#define CAM_CC_ICP_0_CLK 51 +#define CAM_CC_ICP_0_CLK_SRC 52 +#define CAM_CC_ICP_1_AHB_CLK 53 +#define CAM_CC_ICP_1_CLK 54 +#define CAM_CC_ICP_1_CLK_SRC 55 +#define CAM_CC_IFE_LITE_AHB_CLK 56 +#define CAM_CC_IFE_LITE_CLK 57 +#define CAM_CC_IFE_LITE_CLK_SRC 58 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 59 +#define CAM_CC_IFE_LITE_CSID_CLK 60 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 61 +#define CAM_CC_IPE_NPS_AHB_CLK 62 +#define CAM_CC_IPE_NPS_CLK 63 +#define CAM_CC_IPE_NPS_CLK_SRC 64 +#define CAM_CC_IPE_NPS_FAST_AHB_CLK 65 +#define CAM_CC_IPE_PPS_CLK 66 +#define CAM_CC_IPE_PPS_FAST_AHB_CLK 67 +#define CAM_CC_JPEG_CLK 68 +#define CAM_CC_JPEG_CLK_SRC 69 +#define CAM_CC_OFE_AHB_CLK 70 +#define CAM_CC_OFE_ANCHOR_CLK 71 +#define CAM_CC_OFE_ANCHOR_FAST_AHB_CLK 72 +#define CAM_CC_OFE_CLK_SRC 73 +#define CAM_CC_OFE_HDR_CLK 74 +#define CAM_CC_OFE_HDR_FAST_AHB_CLK 75 +#define CAM_CC_OFE_MAIN_CLK 76 +#define CAM_CC_OFE_MAIN_FAST_AHB_CLK 77 +#define CAM_CC_PLL0 78 +#define CAM_CC_PLL0_OUT_EVEN 79 +#define CAM_CC_PLL0_OUT_ODD 80 +#define CAM_CC_PLL1 81 +#define CAM_CC_PLL1_OUT_EVEN 82 +#define CAM_CC_PLL2 83 +#define CAM_CC_PLL2_OUT_EVEN 84 +#define CAM_CC_PLL3 85 +#define CAM_CC_PLL3_OUT_EVEN 86 +#define CAM_CC_PLL4 87 +#define CAM_CC_PLL4_OUT_EVEN 88 +#define CAM_CC_PLL5 89 +#define CAM_CC_PLL5_OUT_EVEN 90 +#define CAM_CC_PLL6 91 +#define CAM_CC_PLL6_OUT_EVEN 92 +#define CAM_CC_PLL6_OUT_ODD 93 +#define CAM_CC_PLL7 94 +#define CAM_CC_PLL7_OUT_EVEN 95 +#define CAM_CC_QDSS_DEBUG_CLK 96 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 97 +#define CAM_CC_QDSS_DEBUG_XO_CLK 98 +#define CAM_CC_SLEEP_CLK 99 +#define CAM_CC_SLOW_AHB_CLK_SRC 100 +#define CAM_CC_TFE_0_BAYER_CLK 101 +#define CAM_CC_TFE_0_BAYER_FAST_AHB_CLK 102 +#define CAM_CC_TFE_0_CLK_SRC 103 +#define CAM_CC_TFE_0_MAIN_CLK 104 +#define CAM_CC_TFE_0_MAIN_FAST_AHB_CLK 105 +#define CAM_CC_TFE_1_BAYER_CLK 106 +#define CAM_CC_TFE_1_BAYER_FAST_AHB_CLK 107 +#define CAM_CC_TFE_1_CLK_SRC 108 +#define CAM_CC_TFE_1_MAIN_CLK 109 +#define CAM_CC_TFE_1_MAIN_FAST_AHB_CLK 110 +#define CAM_CC_TFE_2_BAYER_CLK 111 +#define CAM_CC_TFE_2_BAYER_FAST_AHB_CLK 112 +#define CAM_CC_TFE_2_CLK_SRC 113 +#define CAM_CC_TFE_2_MAIN_CLK 114 +#define CAM_CC_TFE_2_MAIN_FAST_AHB_CLK 115 +#define CAM_CC_TRACENOC_TPDM_1_CMB_CLK 116 +#define CAM_CC_XO_CLK_SRC 117 + +/* CAM_CC power domains */ +#define CAM_CC_IPE_0_GDSC 0 +#define CAM_CC_OFE_GDSC 1 +#define CAM_CC_TFE_0_GDSC 2 +#define CAM_CC_TFE_1_GDSC 3 +#define CAM_CC_TFE_2_GDSC 4 +#define CAM_CC_TITAN_TOP_GDSC 5 + +/* CAM_CC resets */ +#define CAM_CC_DRV_BCR 0 +#define CAM_CC_ICP_BCR 1 +#define CAM_CC_IPE_0_BCR 2 +#define CAM_CC_OFE_BCR 3 +#define CAM_CC_QDSS_DEBUG_BCR 4 +#define CAM_CC_TFE_0_BCR 5 +#define CAM_CC_TFE_1_BCR 6 +#define CAM_CC_TFE_2_BCR 7 + +#endif --=20 2.34.1