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Wed, 07 Jan 2026 01:44:27 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-819bafe9568sm4472944b3a.15.2026.01.07.01.44.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Jan 2026 01:44:26 -0800 (PST) From: Taniya Das Date: Wed, 07 Jan 2026 15:13:13 +0530 Subject: [PATCH v3 10/11] clk: qcom: Add support for VideoCC driver for Kaanapali Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260107-kaanapali-mmcc-v3-v3-10-8e10adc236a8@oss.qualcomm.com> References: <20260107-kaanapali-mmcc-v3-v3-0-8e10adc236a8@oss.qualcomm.com> In-Reply-To: <20260107-kaanapali-mmcc-v3-v3-0-8e10adc236a8@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Maxime Coquelin , Alexandre Torgue , Vladimir Zapolskiy , Jagadeesh Kona , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-ORIG-GUID: YZKD40Q33OOHHSAXuk44A5SlbL9gCeL2 X-Proofpoint-GUID: YZKD40Q33OOHHSAXuk44A5SlbL9gCeL2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA3MDA3OCBTYWx0ZWRfX2W8F/cfiVJR7 +w+ZxlkszlmmOBQRN1WUwSX0RzYtmBqVyDDPO7wUS91+E20UBXrSxA1XMQGIvARtL5YZYxRNoE0 3AQNbKe8TEqW+dZH/MNwFLtd23EOX7c25bbYqsz7NA0ProwCZ08aRG/SQr9kyGLWfJRI8joXGeF tZTOJa37AlALvKBGpvUREB4P3dug1Vl3TK23L3JHEU4aWJojEei940QqMBJtjLlW6KNqVaxy7hJ Ua5MUrZ84Z2WOdgOrlaSWBRTjvR8P1SV1kZS7yKBnvFzFD2XngHDarylnDyLy/1JfgS5pxWSzP/ 0tQXcpy9rfdLAIkiWq31RF74P27tO5K/GygwZskxOJYNSf3z4/JaNShXt5Fgsi2Al5RbgusYZgI 3N2ejZFIrczmpu28LBXN8wwgy3VWvNC6OYVOZzq4edm/RTy24y44hpHzcLujWopR5vwNVeMPW8e soDcdRUxqFOW7ORCzkA== X-Authority-Analysis: v=2.4 cv=MtdfKmae c=1 sm=1 tr=0 ts=695e2afd cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=FXoFOq9PtT0JJl4RUvYA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-06_03,2026-01-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 phishscore=0 adultscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601070078 Enable Kaanapali video clock driver for video SW to be able to control the clocks from the Video SW driver. Signed-off-by: Taniya Das --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-kaanapali.c | 821 +++++++++++++++++++++++++++++++= ++++ 3 files changed, 831 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index e8abfe708aa437cb0f093fb3842ce5864888af92..a97e18703f20acbcd605a8c2479= 5b5073d7ad1b0 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -83,6 +83,15 @@ config CLK_KAANAPALI_TCSRCC Support for the TCSR clock controller on Kaanapali devices. Say Y if you want to use peripheral devices such as PCIe, USB, UFS. =20 +config CLK_KAANAPALI_VIDEOCC + tristate "Kaanapali Video Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_KAANAPALI_GCC + help + Support for the video clock controller on Kaanapali devices. + Say Y if you want to support video devices and functionality such as + video encode/decode. + config CLK_X1E80100_CAMCC tristate "X1E80100 Camera Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index ab0dbef3c63714c90a3496b1ee0921aee1ce9adc..781edb0bc9a3ea160d6755ccf2b= 04af815baa27d 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_KAANAPALI_CAMCC) +=3D cambistmclkcc-kaan= apali.o camcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_DISPCC) +=3D dispcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_GCC) +=3D gcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) +=3D tcsrcc-kaanapali.o +obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) +=3D videocc-kaanapali.o obj-$(CONFIG_CLK_X1E80100_CAMCC) +=3D camcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_DISPCC) +=3D dispcc-x1e80100.o obj-$(CONFIG_CLK_X1E80100_GCC) +=3D gcc-x1e80100.o diff --git a/drivers/clk/qcom/videocc-kaanapali.c b/drivers/clk/qcom/videoc= c-kaanapali.c new file mode 100644 index 0000000000000000000000000000000000000000..835a59536ba79c391d4a0a1e4ba= b0a66f253bef0 --- /dev/null +++ b/drivers/clk/qcom/videocc-kaanapali.c @@ -0,0 +1,821 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +#define ACCU_CFG_MASK GENMASK(25, 21) + +enum { + DT_BI_TCXO, + DT_AHB_CLK, +}; + +enum { + P_BI_TCXO, + P_VIDEO_CC_PLL0_OUT_MAIN, + P_VIDEO_CC_PLL1_OUT_MAIN, + P_VIDEO_CC_PLL2_OUT_MAIN, + P_VIDEO_CC_PLL3_OUT_MAIN, +}; + +static const struct pll_vco taycan_eko_t_vco[] =3D { + { 249600000, 2500000000, 0 }, +}; + +/* 360.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll0_config =3D { + .l =3D 0x12, + .cal_l =3D 0x48, + .alpha =3D 0xc000, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8062e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000008, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll video_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &video_cc_pll0_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +/* 480.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll1_config =3D { + .l =3D 0x19, + .cal_l =3D 0x48, + .alpha =3D 0x0, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8062e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000008, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll video_cc_pll1 =3D { + .offset =3D 0x1000, + .config =3D &video_cc_pll1_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +/* 480.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll2_config =3D { + .l =3D 0x19, + .cal_l =3D 0x48, + .alpha =3D 0x0, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8062e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000008, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll video_cc_pll2 =3D { + .offset =3D 0x2000, + .config =3D &video_cc_pll2_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_pll2", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +/* 480.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll3_config =3D { + .l =3D 0x19, + .cal_l =3D 0x48, + .alpha =3D 0x0, + .config_ctl_val =3D 0x25c400e7, + .config_ctl_hi_val =3D 0x0a8062e0, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000008, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll video_cc_pll3 =3D { + .offset =3D 0x3000, + .config =3D &video_cc_pll3_config, + .vco_table =3D taycan_eko_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eko_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_pll3", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eko_t_ops, + }, + }, +}; + +static const struct parent_map video_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map video_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL1_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_cc_pll1.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL3_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_cc_pll3.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL2_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_cc_pll2.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_4[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_4[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_cc_pll0.clkr.hw }, +}; + +static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_ahb_clk_src =3D { + .cmd_rcgr =3D 0x8060, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_ahb_clk_src", + .parent_data =3D video_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] =3D { + F(240000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(338000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(420000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(444000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(533000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(630000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(800000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(1000000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0_clk_src =3D { + .cmd_rcgr =3D 0x8030, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_1, + .freq_tbl =3D ftbl_video_cc_mvs0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_clk_src", + .parent_data =3D video_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0a_clk_src[] =3D { + F(240000000, P_VIDEO_CC_PLL3_OUT_MAIN, 2, 0, 0), + F(338000000, P_VIDEO_CC_PLL3_OUT_MAIN, 2, 0, 0), + F(420000000, P_VIDEO_CC_PLL3_OUT_MAIN, 2, 0, 0), + F(444000000, P_VIDEO_CC_PLL3_OUT_MAIN, 2, 0, 0), + F(533000000, P_VIDEO_CC_PLL3_OUT_MAIN, 2, 0, 0), + F(630000000, P_VIDEO_CC_PLL3_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0a_clk_src =3D { + .cmd_rcgr =3D 0x8000, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_2, + .freq_tbl =3D ftbl_video_cc_mvs0a_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0a_clk_src", + .parent_data =3D video_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0b_clk_src[] =3D { + F(240000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + F(338000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + F(420000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + F(444000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + F(533000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + F(630000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + F(850000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0b_clk_src =3D { + .cmd_rcgr =3D 0x8018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_3, + .freq_tbl =3D ftbl_video_cc_mvs0b_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0b_clk_src", + .parent_data =3D video_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0c_clk_src[] =3D { + F(360000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(507000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(630000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(666000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(800000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1104000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1260000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0c_clk_src =3D { + .cmd_rcgr =3D 0x8048, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_4, + .freq_tbl =3D ftbl_video_cc_mvs0c_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_clk_src", + .parent_data =3D video_cc_parent_data_4, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_4), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 video_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0x8194, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_xo_clk_src", + .parent_data =3D video_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_branch video_cc_mvs0_clk =3D { + .halt_reg =3D 0x80d0, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80d0, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80d0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_mem_branch video_cc_mvs0_freerun_clk =3D { + .mem_enable_reg =3D 0x80e4, + .mem_ack_reg =3D 0x80e4, + .mem_enable_mask =3D BIT(3), + .mem_enable_ack_mask =3D GENMASK(11, 10), + .mem_enable_invert =3D true, + .branch =3D { + .halt_reg =3D 0x80e0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80e0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_shift_clk =3D { + .halt_reg =3D 0x81b4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x81b4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x81b4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_vpp0_clk =3D { + .halt_reg =3D 0x8134, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8134, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8134, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_vpp0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_vpp0_freerun_clk =3D { + .halt_reg =3D 0x8144, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8144, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_vpp0_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_vpp1_clk =3D { + .halt_reg =3D 0x8108, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8108, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8108, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_vpp1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_vpp1_freerun_clk =3D { + .halt_reg =3D 0x8118, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8118, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_vpp1_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0a_clk =3D { + .halt_reg =3D 0x8090, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8090, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8090, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0a_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0a_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0a_freerun_clk =3D { + .halt_reg =3D 0x80a0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80a0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0a_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0a_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0b_clk =3D { + .halt_reg =3D 0x80bc, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80bc, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0b_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0b_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0b_freerun_clk =3D { + .halt_reg =3D 0x80cc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80cc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0b_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0b_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_clk =3D { + .halt_reg =3D 0x8164, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8164, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8164, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0c_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_freerun_clk =3D { + .halt_reg =3D 0x8174, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8174, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0c_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_shift_clk =3D { + .halt_reg =3D 0x81b8, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x81b8, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x81b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc video_cc_mvs0_vpp0_gdsc =3D { + .gdscr =3D 0x8120, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "video_cc_mvs0_vpp0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs0_vpp1_gdsc =3D { + .gdscr =3D 0x80f4, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "video_cc_mvs0_vpp1_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs0a_gdsc =3D { + .gdscr =3D 0x807c, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "video_cc_mvs0a_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs0c_gdsc =3D { + .gdscr =3D 0x814c, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs0c_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs0_gdsc =3D { + .gdscr =3D 0x80a8, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .parent =3D &video_cc_mvs0c_gdsc.pd, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *video_cc_kaanapali_clocks[] =3D { + [VIDEO_CC_AHB_CLK_SRC] =3D &video_cc_ahb_clk_src.clkr, + [VIDEO_CC_MVS0_CLK] =3D &video_cc_mvs0_clk.clkr, + [VIDEO_CC_MVS0_CLK_SRC] =3D &video_cc_mvs0_clk_src.clkr, + [VIDEO_CC_MVS0_FREERUN_CLK] =3D &video_cc_mvs0_freerun_clk.branch.clkr, + [VIDEO_CC_MVS0_SHIFT_CLK] =3D &video_cc_mvs0_shift_clk.clkr, + [VIDEO_CC_MVS0_VPP0_CLK] =3D &video_cc_mvs0_vpp0_clk.clkr, + [VIDEO_CC_MVS0_VPP0_FREERUN_CLK] =3D &video_cc_mvs0_vpp0_freerun_clk.clkr, + [VIDEO_CC_MVS0_VPP1_CLK] =3D &video_cc_mvs0_vpp1_clk.clkr, + [VIDEO_CC_MVS0_VPP1_FREERUN_CLK] =3D &video_cc_mvs0_vpp1_freerun_clk.clkr, + [VIDEO_CC_MVS0A_CLK] =3D &video_cc_mvs0a_clk.clkr, + [VIDEO_CC_MVS0A_CLK_SRC] =3D &video_cc_mvs0a_clk_src.clkr, + [VIDEO_CC_MVS0A_FREERUN_CLK] =3D &video_cc_mvs0a_freerun_clk.clkr, + [VIDEO_CC_MVS0B_CLK] =3D &video_cc_mvs0b_clk.clkr, + [VIDEO_CC_MVS0B_CLK_SRC] =3D &video_cc_mvs0b_clk_src.clkr, + [VIDEO_CC_MVS0B_FREERUN_CLK] =3D &video_cc_mvs0b_freerun_clk.clkr, + [VIDEO_CC_MVS0C_CLK] =3D &video_cc_mvs0c_clk.clkr, + [VIDEO_CC_MVS0C_CLK_SRC] =3D &video_cc_mvs0c_clk_src.clkr, + [VIDEO_CC_MVS0C_FREERUN_CLK] =3D &video_cc_mvs0c_freerun_clk.clkr, + [VIDEO_CC_MVS0C_SHIFT_CLK] =3D &video_cc_mvs0c_shift_clk.clkr, + [VIDEO_CC_PLL0] =3D &video_cc_pll0.clkr, + [VIDEO_CC_PLL1] =3D &video_cc_pll1.clkr, + [VIDEO_CC_PLL2] =3D &video_cc_pll2.clkr, + [VIDEO_CC_PLL3] =3D &video_cc_pll3.clkr, + [VIDEO_CC_XO_CLK_SRC] =3D &video_cc_xo_clk_src.clkr, +}; + +static struct gdsc *video_cc_kaanapali_gdscs[] =3D { + [VIDEO_CC_MVS0A_GDSC] =3D &video_cc_mvs0a_gdsc, + [VIDEO_CC_MVS0_GDSC] =3D &video_cc_mvs0_gdsc, + [VIDEO_CC_MVS0_VPP1_GDSC] =3D &video_cc_mvs0_vpp1_gdsc, + [VIDEO_CC_MVS0_VPP0_GDSC] =3D &video_cc_mvs0_vpp0_gdsc, + [VIDEO_CC_MVS0C_GDSC] =3D &video_cc_mvs0c_gdsc, +}; + +static const struct qcom_reset_map video_cc_kaanapali_resets[] =3D { + [VIDEO_CC_INTERFACE_BCR] =3D { 0x8178 }, + [VIDEO_CC_MVS0_BCR] =3D { 0x80a4 }, + [VIDEO_CC_MVS0_VPP0_BCR] =3D { 0x811c }, + [VIDEO_CC_MVS0_VPP1_BCR] =3D { 0x80f0 }, + [VIDEO_CC_MVS0A_BCR] =3D { 0x8078 }, + [VIDEO_CC_MVS0C_CLK_ARES] =3D { 0x8164, 2 }, + [VIDEO_CC_MVS0C_BCR] =3D { 0x8148 }, + [VIDEO_CC_MVS0_FREERUN_CLK_ARES] =3D { 0x80e0, 2 }, + [VIDEO_CC_MVS0C_FREERUN_CLK_ARES] =3D { 0x8174, 2 }, + [VIDEO_CC_XO_CLK_ARES] =3D { 0x81ac, 2 }, +}; + +static struct clk_alpha_pll *video_cc_kaanapali_plls[] =3D { + &video_cc_pll0, + &video_cc_pll1, + &video_cc_pll2, + &video_cc_pll3, +}; + +static u32 video_cc_kaanapali_critical_cbcrs[] =3D { + 0x817c, /* VIDEO_CC_AHB_CLK */ + 0x81bc, /* VIDEO_CC_SLEEP_CLK */ + 0x81b0, /* VIDEO_CC_TS_XO_CLK */ + 0x81ac, /* VIDEO_CC_XO_CLK */ +}; + +static const struct regmap_config video_cc_kaanapali_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xa010, + .fast_io =3D true, +}; + +static void clk_kaanapali_regs_configure(struct device *dev, struct regmap= *regmap) +{ + /* + * Enable clk_on sync for MVS0 and VPP clocks via VIDEO_CC_SPARE1 + * during core reset by default. + */ + regmap_set_bits(regmap, 0x9f24, BIT(0)); + + /* + * As per HW design recommendation + * Update DLY_ACCU_RED_SHIFTER_DONE to 0xF for the below GDSCs + * MVS0A CFG3, MVS0 CFG3, MVS0 VPP1 CFG3, MVS0 VPP0 CFG3, MVS0C CFG3 + */ + regmap_set_bits(regmap, 0x8088, ACCU_CFG_MASK); + regmap_set_bits(regmap, 0x80b4, ACCU_CFG_MASK); + regmap_set_bits(regmap, 0x8100, ACCU_CFG_MASK); + regmap_set_bits(regmap, 0x812c, ACCU_CFG_MASK); + regmap_set_bits(regmap, 0x8158, ACCU_CFG_MASK); +} + +static struct qcom_cc_driver_data video_cc_kaanapali_driver_data =3D { + .alpha_plls =3D video_cc_kaanapali_plls, + .num_alpha_plls =3D ARRAY_SIZE(video_cc_kaanapali_plls), + .clk_cbcrs =3D video_cc_kaanapali_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(video_cc_kaanapali_critical_cbcrs), + .clk_regs_configure =3D clk_kaanapali_regs_configure, +}; + +static const struct qcom_cc_desc video_cc_kaanapali_desc =3D { + .config =3D &video_cc_kaanapali_regmap_config, + .clks =3D video_cc_kaanapali_clocks, + .num_clks =3D ARRAY_SIZE(video_cc_kaanapali_clocks), + .resets =3D video_cc_kaanapali_resets, + .num_resets =3D ARRAY_SIZE(video_cc_kaanapali_resets), + .gdscs =3D video_cc_kaanapali_gdscs, + .num_gdscs =3D ARRAY_SIZE(video_cc_kaanapali_gdscs), + .use_rpm =3D true, + .driver_data =3D &video_cc_kaanapali_driver_data, +}; + +static const struct of_device_id video_cc_kaanapali_match_table[] =3D { + { .compatible =3D "qcom,kaanapali-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, video_cc_kaanapali_match_table); + +static int video_cc_kaanapali_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &video_cc_kaanapali_desc); +} + +static struct platform_driver video_cc_kaanapali_driver =3D { + .probe =3D video_cc_kaanapali_probe, + .driver =3D { + .name =3D "videocc-kaanapali", + .of_match_table =3D video_cc_kaanapali_match_table, + }, +}; + +module_platform_driver(video_cc_kaanapali_driver); + +MODULE_DESCRIPTION("QTI VIDEOCC Kaanapali Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1