From nobody Sat Feb 7 21:24:54 2026 Received: from out-188.mta1.migadu.com (out-188.mta1.migadu.com [95.215.58.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 071E1248F47 for ; Tue, 6 Jan 2026 17:10:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767719427; cv=none; b=uijz1KxiPb5Ev/9+lT8AVka2/czZAY2SLuTIswKW7oiDPtUVfjZk2Yr89V1xIw4W0Oscq+X728jWpWgXaTjNxSE1g4wVwgfmlSG9M+QpAlLKQdoZTX/GDz2ee/2/5PfnzBALHauzNojeoLAKkGmHwscRnwZ+MtmzvK0UC6m/ROs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767719427; c=relaxed/simple; bh=pXcMRwGNrhoqzJwzW9ZhkypUyszann526HktTwY3rsc=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=LO4a5FdZsPZbYWXbPPj5vNXaEcwP6x/TyG3zlXykhtnqy1cz66nFjifc6uKI9+ZJiLycsJJ08vJLpv/9uoge26x6QL2CQbrAOJWzKANJb1PHphj0obICJtB3qDl/+s5yI/oxfhiYB6CQ+lxr14kHR60+hqGtQUM5tTyz7kpOFiU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=DejvXBFS; arc=none smtp.client-ip=95.215.58.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="DejvXBFS" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1767719424; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=0foqleVVh6h4kTqU19T/D6SwtRaVNVJmPDXw4dAESSk=; b=DejvXBFSIXP54ESNGLGAAe5B6FL0EVb07QFG1/C7v3YlDw072ceGVPXOC4XTg3qtMVxYs5 n+UYwvFxtR5l+7ano0mL8gl1X+z3g3h4sY7oLJXYKcWucE9Zn5T00GVTaYx6qKjEO4Ff2B PGDQ+iB8ViQdYjsLQOB5MfrQJLIXITg= From: Sean Anderson To: Thinh Nguyen , linux-usb@vger.kernel.org (open list:DESIGNWARE USB3 DRD IP DRIVER) Cc: Neal Frager , Michal Simek , linux-kernel@vger.kernel.org (open list), linux-arm-kernel@lists.infradead.org (moderated list:ARM/ZYNQ ARCHITECTURE), Philipp Zabel , Radhey Shyam Pandey , Greg Kroah-Hartman , Sean Anderson Subject: [PATCH] usb: dwc3: Always deassert xilinx resets Date: Tue, 6 Jan 2026 12:10:18 -0500 Message-Id: <20260106171018.501612-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" If we don't have a usb3 phy we don't need to assert the core resets. Deassert them even if we didn't assert them to support booting when the bootloader never released the core from reset. Signed-off-by: Sean Anderson Acked-by: Thinh Nguyen --- drivers/usb/dwc3/dwc3-xilinx.c | 67 ++++++++++++++++------------------ 1 file changed, 32 insertions(+), 35 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c index 0a8c47876ff9..f41b0da5e89d 100644 --- a/drivers/usb/dwc3/dwc3-xilinx.c +++ b/drivers/usb/dwc3/dwc3-xilinx.c @@ -132,21 +132,6 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *pri= v_data) goto err; } =20 - /* - * The following core resets are not required unless a USB3 PHY - * is used, and the subsequent register settings are not required - * unless a core reset is performed (they should be set properly - * by the first-stage boot loader, but may be reverted by a core - * reset). They may also break the configuration if USB3 is actually - * in use but the usb3-phy entry is missing from the device tree. - * Therefore, skip these operations in this case. - */ - if (!priv_data->usb3_phy) { - /* Deselect the PIPE Clock Select bit in FPD PIPE Clock register */ - writel(PIPE_CLK_DESELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK); - goto skip_usb3_phy; - } - crst =3D devm_reset_control_get_exclusive(dev, "usb_crst"); if (IS_ERR(crst)) { ret =3D PTR_ERR(crst); @@ -171,22 +156,31 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *pr= iv_data) goto err; } =20 - ret =3D reset_control_assert(crst); - if (ret < 0) { - dev_err(dev, "Failed to assert core reset\n"); - goto err; - } + /* + * Asserting the core resets is not required unless a USB3 PHY is used. + * They may also break the configuration if USB3 is actually in use but + * the usb3-phy entry is missing from the device tree. Therefore, skip + * a full reset cycle and just deassert the resets if the phy is + * absent. + */ + if (priv_data->usb3_phy) { + ret =3D reset_control_assert(crst); + if (ret < 0) { + dev_err(dev, "Failed to assert core reset\n"); + goto err; + } =20 - ret =3D reset_control_assert(hibrst); - if (ret < 0) { - dev_err(dev, "Failed to assert hibernation reset\n"); - goto err; - } + ret =3D reset_control_assert(hibrst); + if (ret < 0) { + dev_err(dev, "Failed to assert hibernation reset\n"); + goto err; + } =20 - ret =3D reset_control_assert(apbrst); - if (ret < 0) { - dev_err(dev, "Failed to assert APB reset\n"); - goto err; + ret =3D reset_control_assert(apbrst); + if (ret < 0) { + dev_err(dev, "Failed to assert APB reset\n"); + goto err; + } } =20 ret =3D phy_init(priv_data->usb3_phy); @@ -201,11 +195,15 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *pr= iv_data) goto err; } =20 - /* Set PIPE Power Present signal in FPD Power Present Register*/ - writel(FPD_POWER_PRSNT_OPTION, priv_data->regs + XLNX_USB_FPD_POWER_PRSNT= ); - - /* Set the PIPE Clock Select bit in FPD PIPE Clock register */ - writel(PIPE_CLK_SELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK); + if (priv_data->usb3_phy) { + /* Set PIPE Power Present signal in FPD Power Present Register*/ + writel(FPD_POWER_PRSNT_OPTION, priv_data->regs + XLNX_USB_FPD_POWER_PRSN= T); + /* Set the PIPE Clock Select bit in FPD PIPE Clock register */ + writel(PIPE_CLK_SELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK); + } else { + /* Deselect the PIPE Clock Select bit in FPD PIPE Clock register */ + writel(PIPE_CLK_DESELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK); + } =20 ret =3D reset_control_deassert(crst); if (ret < 0) { @@ -225,7 +223,6 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv= _data) goto err; } =20 -skip_usb3_phy: /* ulpi reset via gpio-modepin or gpio-framework driver */ reset_gpio =3D devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); if (IS_ERR(reset_gpio)) { --=20 2.35.1.1320.gc452695387.dirty