From nobody Sat Feb 7 17:55:19 2026 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E47D7494 for ; Tue, 6 Jan 2026 13:01:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767704497; cv=none; b=AfaDGU2u2TZpXZVNK0S5BTw0ioZWUEbAYBZbWV8rrb7n+7vUvO1yUZO6zOuhcMJVFx3k9zU+1Ulzgse9Gybxp4vY/Px8+uAhCRrpmVclvSk7l7KSBF5BOTy3JCTUhl5/nMxoPzdqk2S+DJzSsS+q3826Y+mVdiY8nGnDRYjv7ng= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767704497; c=relaxed/simple; bh=xviw/0wK6ByHYiByOefJRUlDk1IdeC/oKTvkAdwPzMc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iVWuJqqKd+Af2p0u6SxjZVgT8UbeKF4UFgtIFTM43K9yy2uxRAvp6gkMYXACkPAKcNq3sq+7CN//oxRYz9wbUfnTE9cmUjtWq/hGEpiKjIbNuxfzTrobZBbucMOADznWk96mAzHdDBkEjMYAGCp1GYmFrMC928wKuUf/ahwDmPw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=DIHePOYh; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DIHePOYh" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-47d182a8c6cso5614965e9.1 for ; Tue, 06 Jan 2026 05:01:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1767704493; x=1768309293; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dSheufKc+UUOwl3UwE5ES46jacAULchaJm+bYEcyVi4=; b=DIHePOYhIHpVd8jwxy6yKpQEvK0GobosCXHhnx7lsjhUuSJxO+CtsY1X3hIy6k9SE3 egdrrniqtUEaLqiRlk2offv8NG0VntAjGOaUaAEg/ctUMYM9vvvKLKn2ofAk1wPkBMpH otxMyyNiOUhPkInfIS5j1SzIr076kO6D0RMZNkAJkXQzrPk0esIie/EGe3/sPYjUHqey PIPDTOZq+ksOK/e4mAUYG8oL2v4bUBtmO/fOYyQW390q4fptz38LAvU71h6/YvggksCM 3eZjgPkRSwk+5Quwbm3DXN04wXviQh/qvyxRTgb1LMmA95Kdawo7QT3vIphif8+WEoG5 9DJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767704493; x=1768309293; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=dSheufKc+UUOwl3UwE5ES46jacAULchaJm+bYEcyVi4=; b=nbyN4p1ntdJfZMH48iJ2EDooEsb9hABSjBu6V5AQaFZ+N1Q1UILPTv+i6xD9Tz+qjs B5nvTlp8SpzjEkfHKw5JVRFyuuqbd3IPKyZDATiG41QKOAW2IFRWxrEZTw2etMVQoknL 0hXtUzGSNAVIElKb2UDhGauU9YyJ+gwn98/gfM24csfaWOm9dwkZR/KPOxKebNibVXLm tsaOlWjC/m5NB3PfBJK/vUD9cX/vscUYKI13heanx/7GK/Aw+0u11jMyYacsVDEDs8pK N2cbyKSZY+Ng7NOFtdiBjMcnP0fwTJiz8IhqgDeWn2uc9ug5+ufTdK0LJ7KmuJ5zR96t mf+g== X-Forwarded-Encrypted: i=1; AJvYcCUfKAoqEeQ7Ig5By2YkHXZSZBk4fMiUtVtqJ0XroLODKAoxVaPh5OPqSn2A+JBhBG3Kf4mFGBO7gBr+OoI=@vger.kernel.org X-Gm-Message-State: AOJu0YzP3eT7IpZoaqzyV3ijnxsDQ9GwmlH74C9svgE16aHCc3UAxSoj v5NjRaYVAMZKYDyeF0RHRkm833XZ64efC9z+D4dyuNDCDHhnIevnj0Zv X-Gm-Gg: AY/fxX6zp/Tyd+BAiU07aTHFiwhCgirUJqN1jWvRw3bXsTAYzE5SIXHRLgitvqIoGGq tbudfCVwm0sgmDMiTGzmBIDCrpLN/eh3L49S4XW0+GZwf0l0CKybyQHqgEl2jTigAtJHvWNtvv9 Ry0nsMuE9xDg1HKIteihIQSp/kVXVi2GdTIgShRO1Cnu99OaCSn8uSfPnJSbXuGctRMlK3NkaSG pullVnxgsfuMExLlT4EAELYaJuAEvJytpSfkraz+XsS3QGYGneX2yWDocAI3Dkn959MyElLSGo+ iL9lkzt+p1Iv4mfpSeG8xNub+brzVCH7SJLC355yCkRY27iTfUJljxMy2y2DOYQM2Nnegt90XKB 9dFBWc5KxY29WSpXPmChR9/KfeP9ycsHbHXpPEm9tzbmJQ0lQV2uABv1RXo5HfZZeCVtaqvMLOe 0m8z5jh9uqpDoX/CzOLmB3vYSOmEQ+Y6i1WpuZCVc= X-Google-Smtp-Source: AGHT+IEen1tffLOVS9PvaIgplGvgYv0apDsv1cligNcSYLsf8i0OcV+jJyALYwNJooMKHM+mPmAwiw== X-Received: by 2002:a05:600c:3b27:b0:477:8a29:582c with SMTP id 5b1f17b1804b1-47d7f0a1804mr33634755e9.34.1767704493290; Tue, 06 Jan 2026 05:01:33 -0800 (PST) Received: from ionutnechita-arz2022.local ([2a02:2f0e:ca09:7000:33fc:5cce:3767:6b22]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47d7f68f69dsm42684065e9.1.2026.01.06.05.01.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jan 2026 05:01:32 -0800 (PST) From: "Ionut Nechita (Sunlight Linux)" To: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , Mario Limonciello , Ionut Nechita Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/1] drm/amdgpu: Fix TLB flush failures after hibernation resume Date: Tue, 6 Jan 2026 14:59:33 +0200 Message-ID: <20260106125929.25214-6-sunlightlinux@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260106125929.25214-3-sunlightlinux@gmail.com> References: <20260106125929.25214-3-sunlightlinux@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ionut Nechita After resume from hibernation, the amdgpu driver experiences TLB flush failures with errors: amdgpu: TLB flush failed for PASID xxxxx amdgpu: failed to write reg 28b4 wait reg 28c6 amdgpu: failed to write reg 1a6f4 wait reg 1a706 Root Cause: ----------- The KIQ (Kernel Interface Queue) ring is marked as ready (ring.sched.ready =3D true) during resume, but the hardware is not fully functional yet. When TLB invalidation attempts to use KIQ for register access, the commands fail because the GPU hasn't completed initialization. Solution: --------- 1. Add resume_gpu_stable flag (initially false on resume) 2. Force TLB invalidation to use direct MMIO path instead of KIQ when resume_gpu_stable is false 3. After ring tests pass in gfx_v9_0_cp_resume(), set resume_gpu_stable to true 4. From that point forward, use faster KIQ path for TLB invalidation This ensures TLB flushes work correctly during early resume while still benefiting from KIQ-based invalidation after the GPU is stable. Changes: -------- - amdgpu.h: Add resume_gpu_stable flag to amdgpu_device - amdgpu_device.c: Initialize resume_gpu_stable to false on resume - amdgpu_gmc.c: Check resume_gpu_stable in flush_gpu_tlb_pasid - gfx_v9_0.c: Set resume_gpu_stable after ring tests pass - gmc_v9_0.c: Check resume_gpu_stable before using KIQ path Tested on AMD Cezanne (Renoir) with ROCm workloads after hibernation. Result: Eliminates TLB flush failures on resume. Signed-off-by: Ionut Nechita --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 9 +++++++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++++++++++ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 +++++- 5 files changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdg= pu/amdgpu.h index 9f9774f58ce1c..6bf4f6c90164c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1225,6 +1225,7 @@ struct amdgpu_device { bool in_s4; bool in_s0ix; suspend_state_t last_suspend_state; + bool resume_gpu_stable; =20 enum pp_mp1_state mp1_state; struct amdgpu_doorbell_index doorbell_index; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_device.c index 12201b8e99b3f..440d86ed1e0d3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5457,6 +5457,12 @@ int amdgpu_device_resume(struct drm_device *dev, boo= l notify_clients) goto exit; } =20 + /* + * Set resume_gpu_stable to false BEFORE KFD resume to ensure + * extended timeouts are used for TLB flushes during hibernation recovery + */ + adev->resume_gpu_stable =3D false; + r =3D amdgpu_amdkfd_resume(adev, !amdgpu_sriov_vf(adev) && !adev->in_runp= m); if (r) goto exit; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_gmc.c index 869bceb0fe2c6..83fe30f0ada75 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -731,7 +731,12 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_devic= e *adev, uint16_t pasid, if (!down_read_trylock(&adev->reset_domain->sem)) return 0; =20 - if (!adev->gmc.flush_pasid_uses_kiq || !ring->sched.ready) { + /* + * After hibernation resume, KIQ may report as ready but not be fully + * functional. Use direct MMIO path until GPU is confirmed stable. + */ + if (!adev->gmc.flush_pasid_uses_kiq || !ring->sched.ready || + !adev->resume_gpu_stable) { if (adev->gmc.flush_tlb_needs_extra_type_2) adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid, 2, all_hub, @@ -835,9 +840,9 @@ void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_dev= ice *adev, goto failed_kiq; =20 might_sleep(); + while (r < 1 && cnt++ < MAX_KIQ_REG_TRY && !amdgpu_reset_pending(adev->reset_domain)) { - msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); r =3D amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/am= dgpu/gfx_v9_0.c index 0148d7ff34d99..fbd07b455b915 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -3985,6 +3985,16 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *= adev) amdgpu_ring_test_helper(ring); } =20 + /* + * After successful ring tests, mark GPU as stable for resume. + * This allows KIQ-based TLB invalidation to be used instead of + * slower direct MMIO path. + */ + if (!adev->resume_gpu_stable) { + adev->resume_gpu_stable =3D true; + dev_info(adev->dev, "GPU rings verified, enabling KIQ path\n"); + } + gfx_v9_0_enable_gui_idle_interrupt(adev, true); =20 return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/am= dgpu/gmc_v9_0.c index 8ad7519f7b581..8a0202f6b3e3c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -855,9 +855,13 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_devic= e *adev, uint32_t vmid, =20 /* This is necessary for SRIOV as well as for GFXOFF to function * properly under bare metal + * + * After hibernation resume, KIQ may report as ready but not be fully + * functional. Use direct MMIO path until GPU is confirmed stable. */ if (adev->gfx.kiq[inst].ring.sched.ready && - (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { + (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && + adev->resume_gpu_stable) { uint32_t req =3D hub->vm_inv_eng0_req + hub->eng_distance * eng; uint32_t ack =3D hub->vm_inv_eng0_ack + hub->eng_distance * eng; =20 --=20 2.52.0