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Tue, 6 Jan 2026 03:10:42 -0800 From: Kartik Rajput To: , , , , , , , , , CC: Kartik Rajput Subject: [PATCH v3 2/4] i2c: tegra: Move variant to tegra_i2c_hw_feature Date: Tue, 6 Jan 2026 16:40:31 +0530 Message-ID: <20260106111033.5556-3-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260106111033.5556-1-kkartik@nvidia.com> References: <20260106111033.5556-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB73:EE_|SN7PR12MB7980:EE_ X-MS-Office365-Filtering-Correlation-Id: 7656d51d-84c9-4417-7256-08de4d14465f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?CbsaVeDzXUjw73UouvXGNTGZYfxvVCidixeU/SgZMDUarUlnmuCyY7BuDfAE?= =?us-ascii?Q?mbjZFR+T40DDOa+/KsefDJ7GcmOh68QWMx25iT5RBTwB5BBTqpzU27d7O0bI?= =?us-ascii?Q?0VujKXOFLxOom0zyUN/Q42HIlFTBKVBE6WdisS6kipVD7xNeg3dKV+Dtz8bt?= =?us-ascii?Q?AAY46d9R/DtYEMPjqMHRYlpTWi9iGPlskT+5+4pn8jnNajlBExcLkpJAoUzg?= =?us-ascii?Q?gBWwn6ilKB0ysfwV3rQI/DuxEr9vnwXXqs669t/0/QszRVodI4vyvPCNYGLU?= =?us-ascii?Q?54cXzMCYd4KDb+lE8KCKVhsv6LWwU6ulq7hYf7xLSaYgrKsnl8/CsVCC2X78?= =?us-ascii?Q?5+YZdGg4Gymqtmg0AAeVXdsTfnhpNo6KzRnfvzQ710e5QC+ylX19VKVkWH3m?= =?us-ascii?Q?2Gbb+Xo1vwYCbb9CvFLSb0vxJso/tqh9W8n3ojDJvIYdChho2Oo17MogQuxZ?= =?us-ascii?Q?Jcav5d6KvedMUatJcTQUjqLOc2tIaaRoc5xrza7m0nkAjaAoKlKd2xV6fJK0?= =?us-ascii?Q?N61Gk622FAKpQetSM6mPis+k5Yp0Ehy9KBJulQzcWaCBo4CmTKcuzkSI2Vd9?= =?us-ascii?Q?AUDQlGLFA6DOIYESqFoWASQ9DP/MW5i7hEFYs7l88ZU/WvylPKuXOF8EZIJk?= =?us-ascii?Q?dxfO7U/mKonqjFepjELO5LgiTgPvOoPP50SCi4wDOp34P91sM1qBkZNBXYRT?= =?us-ascii?Q?Mc/NDomlUwocGo7i22feHQ+Bm+URczKQp6o9Mn4i8j+QDrRhOOvo0NnjYHQ+?= =?us-ascii?Q?8phOLD1qJ+KGvZ4QQ/r9RAYD2Gmr+rwVaW6Nfl2j/tkIF4tUcQxXPhmQbU1R?= =?us-ascii?Q?4hmFoK7vbhSMB0/awAi4xBI/sC5WiPQM0YXbXHPaz7fCWbWW24ntZZafsl1c?= =?us-ascii?Q?2e+Gn53n4v//r8+rSSfp4Z3h8HSkD7DeUMP+UFB7JU3dmZ6HPqYs1gI77f6K?= =?us-ascii?Q?uVFnuy8syybIXPA53L0GeKChjmZphLNiXSr6e1IDCn0eQkwefP1LY/TOqUMf?= =?us-ascii?Q?mEfcBiTC2V3vInHxQ6wJskW7OTkA1FjUsmCsWOMnosj/e3TQQ75Aas0ryLfK?= =?us-ascii?Q?IxReVWG1K61RWjWSuwazgoktDJLNIPyHztYf4kHcIkpN9ExNZSfVIxkj6Ndd?= =?us-ascii?Q?4cZUypQ0viSAcQQZbLw4ErJcOz1FQlSth/YrncCr2fwxdZzfgdx52VUS+Rbl?= =?us-ascii?Q?sb9jc2djfbVBz3kMkn+igVZXPmTtQjxd6ctsOF05WfRhy087+d0v8/TlPEKr?= =?us-ascii?Q?dExHoRTvw/7LfNeMEJx4B6z9l/S2TBsVOsrcYU2a8nwIuvJqT1sfX6dAMRgb?= =?us-ascii?Q?R0utSirhR26v8TwGH6vLOOtxJ76i5/IeqB3uza/RGaVMtiIJUEh90V0CKdGV?= =?us-ascii?Q?hCKItgxP1qAPk+4kTUFXisYN0KKj7DtE3E9T47I9KjMZ6XCCEE9eTUxJaD5J?= =?us-ascii?Q?i2eL6uh0Q85WIBjFsjwIPprjwOHtpQjFWUHPmXHqZeqxatCRR1HZsaNPzs9q?= =?us-ascii?Q?UaBL4pJCIreF2RNRmngFkKYk+pkYibupbjApneOlqTuhWUk03npXyRCPKvID?= =?us-ascii?Q?fkbFF0pQ4P1O3YM4vU9s4EoAyjLY5A7Yr9ZsHHRV?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jan 2026 11:11:00.6562 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7656d51d-84c9-4417-7256-08de4d14465f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB73.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7980 Content-Type: text/plain; charset="utf-8" Move the variant field into tegra_i2c_hw_feature and populate it for all SoCs. Add dedicated SoC data for "nvidia,tegra20-i2c-dvc" and "nvidia,tegra210-i2c-vi" compatibles. Drop the compatible-string checks from tegra_i2c_parse_dt to initialize the Tegra I2C variant. Also remove the redundant config checks from IS_VI and IS_DVC macros. Signed-off-by: Kartik Rajput --- drivers/i2c/busses/i2c-tegra.c | 100 ++++++++++++++++++++++++++------- 1 file changed, 81 insertions(+), 19 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 9a09079dcc9c..4ab991a22350 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -235,6 +235,7 @@ enum tegra_i2c_variant { * timing settings. * @enable_hs_mode_support: Enable support for high speed (HS) mode transf= ers. * @has_mutex: Has mutex register for mutual exclusion with other firmware= s or VMs. + * @variant: This represents the I2C controller variant. */ struct tegra_i2c_hw_feature { bool has_continue_xfer_support; @@ -266,6 +267,7 @@ struct tegra_i2c_hw_feature { bool has_interface_timing_reg; bool enable_hs_mode_support; bool has_mutex; + enum tegra_i2c_variant variant; }; =20 /** @@ -281,7 +283,6 @@ struct tegra_i2c_hw_feature { * @base_phys: physical base address of the I2C controller * @cont_id: I2C controller ID, used for packet header * @irq: IRQ number of transfer complete interrupt - * @variant: This represents the I2C controller variant. * @msg_complete: transfer completion notifier * @msg_buf_remaining: size of unsent data in the message buffer * @msg_len: length of message in current transfer @@ -334,13 +335,10 @@ struct tegra_i2c_dev { bool atomic_mode; bool dma_mode; bool msg_read; - enum tegra_i2c_variant variant; }; =20 -#define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && \ - (dev)->variant =3D=3D TEGRA_I2C_VARIANT_DVC) -#define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && \ - (dev)->variant =3D=3D TEGRA_I2C_VARIANT_VI) +#define IS_DVC(dev) ((dev)->hw->variant =3D=3D TEGRA_I2C_VARIANT_DVC) +#define IS_VI(dev) ((dev)->hw->variant =3D=3D TEGRA_I2C_VARIANT_VI) =20 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg) @@ -1649,8 +1647,42 @@ static const struct tegra_i2c_hw_feature tegra20_i2c= _hw =3D { .has_interface_timing_reg =3D false, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 +#if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) +static const struct tegra_i2c_hw_feature tegra20_dvc_i2c_hw =3D { + .has_continue_xfer_support =3D false, + .has_per_pkt_xfer_complete_irq =3D false, + .clk_divisor_hs_mode =3D 3, + .clk_divisor_std_mode =3D 0, + .clk_divisor_fast_mode =3D 0, + .clk_divisor_fast_plus_mode =3D 0, + .has_config_load_reg =3D false, + .has_multi_master_mode =3D false, + .has_slcg_override_reg =3D false, + .has_mst_fifo =3D false, + .has_mst_reset =3D false, + .quirks =3D &tegra_i2c_quirks, + .supports_bus_clear =3D false, + .has_apb_dma =3D true, + .tlow_std_mode =3D 0x4, + .thigh_std_mode =3D 0x2, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x2, + .setup_hold_time_std_mode =3D 0x0, + .setup_hold_time_fast_mode =3D 0x0, + .setup_hold_time_fastplus_mode =3D 0x0, + .setup_hold_time_hs_mode =3D 0x0, + .has_interface_timing_reg =3D false, + .enable_hs_mode_support =3D false, + .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DVC, +}; +#endif + static const struct tegra_i2c_hw_feature tegra30_i2c_hw =3D { .has_continue_xfer_support =3D true, .has_per_pkt_xfer_complete_irq =3D false, @@ -1679,6 +1711,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_= hw =3D { .has_interface_timing_reg =3D false, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra114_i2c_hw =3D { @@ -1709,6 +1742,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c= _hw =3D { .has_interface_timing_reg =3D false, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra124_i2c_hw =3D { @@ -1739,6 +1773,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra210_i2c_hw =3D { @@ -1769,8 +1804,42 @@ static const struct tegra_i2c_hw_feature tegra210_i2= c_hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 +#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) +static const struct tegra_i2c_hw_feature tegra210_vi_i2c_hw =3D { + .has_continue_xfer_support =3D true, + .has_per_pkt_xfer_complete_irq =3D true, + .clk_divisor_hs_mode =3D 1, + .clk_divisor_std_mode =3D 0x19, + .clk_divisor_fast_mode =3D 0x19, + .clk_divisor_fast_plus_mode =3D 0x10, + .has_config_load_reg =3D true, + .has_multi_master_mode =3D false, + .has_slcg_override_reg =3D true, + .has_mst_fifo =3D false, + .has_mst_reset =3D false, + .quirks =3D &tegra_i2c_quirks, + .supports_bus_clear =3D true, + .has_apb_dma =3D true, + .tlow_std_mode =3D 0x4, + .thigh_std_mode =3D 0x2, + .tlow_fast_mode =3D 0x4, + .thigh_fast_mode =3D 0x2, + .tlow_fastplus_mode =3D 0x4, + .thigh_fastplus_mode =3D 0x2, + .setup_hold_time_std_mode =3D 0, + .setup_hold_time_fast_mode =3D 0, + .setup_hold_time_fastplus_mode =3D 0, + .setup_hold_time_hs_mode =3D 0, + .has_interface_timing_reg =3D true, + .enable_hs_mode_support =3D false, + .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_VI, +}; +#endif + static const struct tegra_i2c_hw_feature tegra186_i2c_hw =3D { .has_continue_xfer_support =3D true, .has_per_pkt_xfer_complete_irq =3D true, @@ -1799,6 +1868,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D false, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra194_i2c_hw =3D { @@ -1831,6 +1901,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D true, .has_mutex =3D false, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra256_i2c_hw =3D { @@ -1863,6 +1934,7 @@ static const struct tegra_i2c_hw_feature tegra256_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D true, .has_mutex =3D true, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct tegra_i2c_hw_feature tegra264_i2c_hw =3D { @@ -1895,6 +1967,7 @@ static const struct tegra_i2c_hw_feature tegra264_i2c= _hw =3D { .has_interface_timing_reg =3D true, .enable_hs_mode_support =3D true, .has_mutex =3D true, + .variant =3D TEGRA_I2C_VARIANT_DEFAULT, }; =20 static const struct of_device_id tegra_i2c_of_match[] =3D { @@ -1903,7 +1976,7 @@ static const struct of_device_id tegra_i2c_of_match[]= =3D { { .compatible =3D "nvidia,tegra194-i2c", .data =3D &tegra194_i2c_hw, }, { .compatible =3D "nvidia,tegra186-i2c", .data =3D &tegra186_i2c_hw, }, #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) - { .compatible =3D "nvidia,tegra210-i2c-vi", .data =3D &tegra210_i2c_hw, }, + { .compatible =3D "nvidia,tegra210-i2c-vi", .data =3D &tegra210_vi_i2c_hw= , }, #endif { .compatible =3D "nvidia,tegra210-i2c", .data =3D &tegra210_i2c_hw, }, { .compatible =3D "nvidia,tegra124-i2c", .data =3D &tegra124_i2c_hw, }, @@ -1911,7 +1984,7 @@ static const struct of_device_id tegra_i2c_of_match[]= =3D { { .compatible =3D "nvidia,tegra30-i2c", .data =3D &tegra30_i2c_hw, }, { .compatible =3D "nvidia,tegra20-i2c", .data =3D &tegra20_i2c_hw, }, #if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) - { .compatible =3D "nvidia,tegra20-i2c-dvc", .data =3D &tegra20_i2c_hw, }, + { .compatible =3D "nvidia,tegra20-i2c-dvc", .data =3D &tegra20_dvc_i2c_hw= , }, #endif {}, }; @@ -1919,23 +1992,12 @@ MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); =20 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) { - struct device_node *np =3D i2c_dev->dev->of_node; bool multi_mode; =20 i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true); =20 multi_mode =3D device_property_read_bool(i2c_dev->dev, "multi-master"); i2c_dev->multimaster_mode =3D multi_mode; - - i2c_dev->variant =3D TEGRA_I2C_VARIANT_DEFAULT; - - if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && - of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc")) - i2c_dev->variant =3D TEGRA_I2C_VARIANT_DVC; - - if (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && - of_device_is_compatible(np, "nvidia,tegra210-i2c-vi")) - i2c_dev->variant =3D TEGRA_I2C_VARIANT_VI; } =20 static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev) --=20 2.43.0