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Tue, 6 Jan 2026 03:10:39 -0800 From: Kartik Rajput To: , , , , , , , , , CC: Kartik Rajput Subject: [PATCH v3 1/4] i2c: tegra: Introduce tegra_i2c_variant to identify DVC and VI Date: Tue, 6 Jan 2026 16:40:30 +0530 Message-ID: <20260106111033.5556-2-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260106111033.5556-1-kkartik@nvidia.com> References: <20260106111033.5556-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017098:EE_|BY5PR12MB4084:EE_ X-MS-Office365-Filtering-Correlation-Id: 3f538d12-0875-4cde-51fb-08de4d1443d5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?AC5qDILj1vsPuO1KtStHQN/yTXlVniHdIdKPYMs+CSDvUlSpKOEu8Uk+stG+?= =?us-ascii?Q?+lj7I3z/IhtvHCnml1wH/9H9iBSG6tUYPsKuYomJgEde9ncwkWbugjEzfe34?= =?us-ascii?Q?wzfasVsGUp1sxvGU/aljvZYE5F36Ihe5B7gTtkk3x6BCTH3fkLWEpTQL7ZGU?= =?us-ascii?Q?Fkr7wedugj/wsmNX0o6MObBjStZTMgni5Ynv1peN1+GZyDKZTlTeXhJwWA/h?= =?us-ascii?Q?FwTAET0zsuLMQaU8tGB1eT3h3liQ4tGkN+1iCXmuP5ZQ/rs9jAYBi40WZEJv?= =?us-ascii?Q?uEi9HeDQyjwB+1idxjAsQiLTULepuwUNvBIcHGVA28VGgAI6JJC9wEsFzhDA?= =?us-ascii?Q?WqXKBR6TuzraSfN9PoJFh5BMen2wwVv57zNRF90ygN0dR+puzymE7KG2lbtD?= =?us-ascii?Q?pbM4zz4TJ3R1k/jLm8xv01wB0hhWFVGxQOxRoyVSrgsEus7cGOFVQ1mLrGTR?= =?us-ascii?Q?K/dN/wYEOwjdPKtB1Sm+006x7jMjcYoPclRVBiDjodWdSuEQSFtaXHAcmVgX?= =?us-ascii?Q?BvZkbv2naigaRXiMe3kcdG8Kwbao6N5JJaY1JypX370DfMNioMMUlU0GMBJA?= =?us-ascii?Q?qtLfOf0x5BgNpiej2r8/6ju4YXqBZD7e/moXsmm+bOP4HmhH1ErQzII9qJJM?= =?us-ascii?Q?cJ57z2z4ugzBbGIZWHuvsu6EYXxQ37/X55NQCfo0/oh7j3nnN2liIFuL0KQM?= =?us-ascii?Q?SHdx7RZU7BZKJ1p8MoNlfNw7KQnf0wteMR+pnCtp8No6qswzuXtvj0dYo90Z?= =?us-ascii?Q?qnZQYr8bqvR7rgS2hnJMdloGVZCx8HE0ZLwgFZvYiwMqRf7sCVpqGmolbqpM?= =?us-ascii?Q?hKDudztpeLvekkEKEVXQBS3rHzgKVPfoIT9jfDZequFN/HPwqLdgp17fJNCK?= =?us-ascii?Q?qm/9fyHrjrkK1sbqedjz5fmRU0ZSXLgQKBn87qay7UI9VQl8udi4O6Qe3Rfm?= =?us-ascii?Q?bzY6dmxCqpI25GNuCZl2GyrtBr8Vr2kpon7+8kuOFR2p0CGpFzAThujcO2S2?= =?us-ascii?Q?sr3ZT7XqvtcIdgCVhDYwmhubBC8F1BYdTzv71dNcXq/l+dpQeUeYncwu1zlG?= =?us-ascii?Q?ZcOAIg1Y9Gk0fNJNgiFZHOKQH/j6Q50gMLxQgBw2isx0PNv9U7fIJuzJB3Xh?= =?us-ascii?Q?5yRkHps78KzkNYtMkILcX3rWO3FVNv2TXeNpv1oWg2b61XN328sNfkrhCHlc?= =?us-ascii?Q?0vGaP2Hf96bryEaxBfKWJIqeoTAsCxVeBCidPCYokRmsg83HAQysERPKD5yC?= =?us-ascii?Q?RMYQyv540ecXCC7y1RJkZ95woiEjdQZaBdtmOd5H2rwvaRMnKK+POv2vVC/B?= =?us-ascii?Q?WWSnsxLaTrZfVz9agf0STtMZjud7tqIkeMDVDyeC4eBgQfg4HldD60rZaRuT?= =?us-ascii?Q?zvgJQGD+4W061O7aiUrtqjFGIwAg58Es7c8zJeK+YREVEFLTVZghPpIWc/AE?= =?us-ascii?Q?D1j9m6/Qa/bA01wA75dkgZR2kfJLSloZOI3M9mEWld8lxkh0g85ke0BzBxSO?= =?us-ascii?Q?sUCnPVO/LncyrsQD0P4llKTISHTUmdyGDTShuvccuqaOq8iZ27ZvOcuPwkBL?= =?us-ascii?Q?rxNZNp5O4BwjP/4c5jItBbYaoa0Sizy/ghn+NDYM?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jan 2026 11:10:56.4378 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3f538d12-0875-4cde-51fb-08de4d1443d5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017098.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4084 Content-Type: text/plain; charset="utf-8" Replace the per-instance boolean flags with an enum tegra_i2c_variant since DVC and VI are mutually exclusive. Update IS_DVC/IS_VI and variant initialization accordingly. Suggested-by: Jon Hunter Signed-off-by: Kartik Rajput --- drivers/i2c/busses/i2c-tegra.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index d05015ef425d..9a09079dcc9c 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -171,6 +171,18 @@ enum msg_end_type { MSG_END_CONTINUE, }; =20 +/* + * tegra_i2c_variant: Identifies the variant of I2C controller. + * @TEGRA_I2C_VARIANT_DEFAULT: Identifies the default I2C controller. + * @TEGRA_I2C_VARIANT_DVC: Identifies the DVC I2C controller, has a differ= ent register layout. + * @TEGRA_I2C_VARIANT_VI: Identifies the VI I2C controller, has a differen= t register layout. + */ +enum tegra_i2c_variant { + TEGRA_I2C_VARIANT_DEFAULT, + TEGRA_I2C_VARIANT_DVC, + TEGRA_I2C_VARIANT_VI, +}; + /** * struct tegra_i2c_hw_feature : per hardware generation features * @has_continue_xfer_support: continue-transfer supported @@ -269,8 +281,7 @@ struct tegra_i2c_hw_feature { * @base_phys: physical base address of the I2C controller * @cont_id: I2C controller ID, used for packet header * @irq: IRQ number of transfer complete interrupt - * @is_dvc: identifies the DVC I2C controller, has a different register la= yout - * @is_vi: identifies the VI I2C controller, has a different register layo= ut + * @variant: This represents the I2C controller variant. * @msg_complete: transfer completion notifier * @msg_buf_remaining: size of unsent data in the message buffer * @msg_len: length of message in current transfer @@ -323,12 +334,13 @@ struct tegra_i2c_dev { bool atomic_mode; bool dma_mode; bool msg_read; - bool is_dvc; - bool is_vi; + enum tegra_i2c_variant variant; }; =20 -#define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && (dev)->is_dvc) -#define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && (dev)->is_vi) +#define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && \ + (dev)->variant =3D=3D TEGRA_I2C_VARIANT_DVC) +#define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && \ + (dev)->variant =3D=3D TEGRA_I2C_VARIANT_VI) =20 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg) @@ -1915,13 +1927,15 @@ static void tegra_i2c_parse_dt(struct tegra_i2c_dev= *i2c_dev) multi_mode =3D device_property_read_bool(i2c_dev->dev, "multi-master"); i2c_dev->multimaster_mode =3D multi_mode; =20 + i2c_dev->variant =3D TEGRA_I2C_VARIANT_DEFAULT; + if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc")) - i2c_dev->is_dvc =3D true; + i2c_dev->variant =3D TEGRA_I2C_VARIANT_DVC; =20 if (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && of_device_is_compatible(np, "nvidia,tegra210-i2c-vi")) - i2c_dev->is_vi =3D true; + i2c_dev->variant =3D TEGRA_I2C_VARIANT_VI; } =20 static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev) --=20 2.43.0