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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jan 2026 10:48:19.6003 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c117d0d8-f7cd-4ff4-20f1-08de4d111b10 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002315.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLAPR10MB5075 Content-Type: text/plain; charset="utf-8" The TI K3 AM62P and J722S SoCs have a HSM (High Security Module) M4F core in the MAIN Voltage Domain which could be used to run secure services like Authentication. Add Device Tree Node definitions for the HSM core in the respective SoC common main dtsi file. The corresponding reg ranges of HSM node has also been added to its parent node's (cbass_main bus) ranges property. Signed-off-by: Beleswar Padhi --- v2: Changelog: 1. None Link to v1: https://lore.kernel.org/all/20251231165102.950644-4-b-padhi@ti.com/ .../boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/ti/k3-am62p.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j722s.dtsi | 1 + 3 files changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/= arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index 3cf7c2b3ce2dd..28586cbc57613 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -1117,4 +1117,19 @@ vpu: video-codec@30210000 { clocks =3D <&k3_clks 204 2>; power-domains =3D <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; }; + + hsm_m4fss: m4fss@43c00000 { + compatible =3D "ti,hsm-m4fss"; + reg =3D <0x00 0x43c00000 0x00 0x20000>, + <0x00 0x43c20000 0x00 0x10000>, + <0x00 0x43c30000 0x00 0x10000>; + reg-names =3D "sram0_0", "sram0_1", "sram1"; + resets =3D <&k3_reset 225 1>; + firmware-name =3D "hsm.bin"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <225>; + ti,sci-proc-ids =3D <0x80 0xff>; + status =3D "disabled"; + bootph-pre-ram; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/= k3-am62p.dtsi index e2c01328eb298..9d6266d6ddb82 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi @@ -96,6 +96,7 @@ cbass_main: bus@f0000 { <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core w= indow */ <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data = */ + <0x00 0x43c00000 0x00 0x43c00000 0x00 0x00040000>, /* HSM SRAM ranges = */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy confi= g */ <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/= k3-j722s.dtsi index c8b634c346779..059c65ece183f 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -173,6 +173,7 @@ cbass_main: bus@f0000 { <0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core w= indow */ <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data = */ + <0x00 0x43c00000 0x00 0x43c00000 0x00 0x00040000>, /* HSM SRAM ranges = */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy confi= g */ <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ --=20 2.34.1