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(unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id 5AEC63F70C4; Mon, 5 Jan 2026 18:15:24 -0800 (PST) From: Ratheesh Kannoth To: , , CC: , , , , , Ratheesh Kannoth Subject: [PATCH net-next 05/10] octeontx2-af: switch: Enable Switch hw port for all channels Date: Tue, 6 Jan 2026 07:44:42 +0530 Message-ID: <20260106021447.2359108-6-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260106021447.2359108-1-rkannoth@marvell.com> References: <20260106021447.2359108-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA2MDAxOCBTYWx0ZWRfX/u/ulBUhJGRr zX/RSiT0k/WqltMP9bhnLEtToMi6v5PehvHnOws++F09zaEDwDhFgx+3VUoQZdQgZtavTUiTtE7 7vEGF8ZweID7Jih54dZdvT2Wmtnc5fYthqlrc1U8up0NIHI/F/J4J+W6Nj4fcblDu7eKHzE3Z+L B1xf3HLKibiziBCeeVmp5NoYVuHMXw7DgxNMqOw+efpklIeJkOvsoVR4NH3WzBqalGDhgFbQB9h ogbodPitwDmCn4xcid2WMzApRw+7Rpeo7j9e1PKS0iverXB8P9xzkcIemS46LOftcEpnO+0VYGx 2ZxWwRWB386wKSb1OY4eT/MfOwEh7/2RoP7JiDb0QPcYV44YT7Ypuq1ABKHa+Wa1cSfUJnKNBtg 25Qz3VRNGhmVdHzZKebjc371VQR/pUKzfaoHpBQH8abQuBqekUzgjefODJ7L/9QSSut6HkPB8az +NnrlcOmONUSYqoiihA== X-Proofpoint-ORIG-GUID: FbcLa9o5DrsiY1g86YGaC5Q5ckGqAxA- X-Authority-Analysis: v=2.4 cv=aLr9aL9m c=1 sm=1 tr=0 ts=695c7040 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=M5GUcnROAAAA:8 a=0Cqobd3ug1408HmlttkA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: FbcLa9o5DrsiY1g86YGaC5Q5ckGqAxA- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-05_02,2026-01-05_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Switch HW should be able to fwd packets to any link based on flow rules. Set txlink enable for all channels. Signed-off-by: Ratheesh Kannoth --- .../net/ethernet/marvell/octeontx2/af/mbox.h | 4 ++ .../ethernet/marvell/octeontx2/af/rvu_nix.c | 50 ++++++++++++++++--- .../marvell/octeontx2/af/rvu_npc_fs.c | 2 +- .../marvell/octeontx2/nic/otx2_txrx.h | 2 + 4 files changed, 51 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index bb38d06c925c..9404c935669d 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -1122,6 +1122,8 @@ struct nix_txsch_alloc_req { /* Scheduler queue count request at each level */ u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ +#define NIX_TXSCH_ALLOC_FLAG_PAN BIT_ULL(0) + u64 flags; }; =20 struct nix_txsch_alloc_rsp { @@ -1140,6 +1142,7 @@ struct nix_txsch_alloc_rsp { struct nix_txsch_free_req { struct mbox_msghdr hdr; #define TXSCHQ_FREE_ALL BIT_ULL(0) +#define TXSCHQ_FREE_PAN_TL1 BIT_ULL(1) u16 flags; /* Scheduler queue level to be freed */ u16 schq_lvl; @@ -1958,6 +1961,7 @@ struct npc_install_flow_req { u16 entry; u16 channel; u16 chan_mask; + u8 set_chanmask; u8 intf; u8 set_cntr; /* If counter is available set counter for this entry ? */ u8 default_rule; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_nix.c index e2cc33ad2b2c..9d9d59affd68 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -1586,7 +1586,7 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, if (err) goto free_mem; =20 - pfvf->sq_bmap =3D kcalloc(req->sq_cnt, sizeof(long), GFP_KERNEL); + pfvf->sq_bmap =3D kcalloc(req->sq_cnt, sizeof(long) * 16, GFP_KERNEL); if (!pfvf->sq_bmap) goto free_mem; =20 @@ -2106,11 +2106,14 @@ static int nix_check_txschq_alloc_req(struct rvu *r= vu, int lvl, u16 pcifunc, if (!req_schq) return 0; =20 - link =3D nix_get_tx_link(rvu, pcifunc); + if (req->flags & NIX_TXSCH_ALLOC_FLAG_PAN) + link =3D hw->cgx_links + hw->lbk_links + 1; + else + link =3D nix_get_tx_link(rvu, pcifunc); =20 /* For traffic aggregating scheduler level, one queue is enough */ if (lvl >=3D hw->cap.nix_tx_aggr_lvl) { - if (req_schq !=3D 1) + if (req_schq !=3D 1 && !(req->flags & NIX_TXSCH_ALLOC_FLAG_PAN)) return NIX_AF_ERR_TLX_ALLOC_FAIL; return 0; } @@ -2147,11 +2150,41 @@ static void nix_txsch_alloc(struct rvu *rvu, struct= nix_txsch *txsch, struct rvu_hwinfo *hw =3D rvu->hw; u16 pcifunc =3D rsp->hdr.pcifunc; int idx, schq; + bool alloc; =20 /* For traffic aggregating levels, queue alloc is based * on transmit link to which PF_FUNC is mapped to. */ if (lvl >=3D hw->cap.nix_tx_aggr_lvl) { + if (start !=3D end) { + idx =3D 0; + alloc =3D false; + for (schq =3D start; schq <=3D end; schq++, idx++) { + if (test_bit(schq, txsch->schq.bmap)) + continue; + + set_bit(schq, txsch->schq.bmap); + + /* A single TL queue is allocated each time */ + if (rsp->schq_contig[lvl]) { + alloc =3D true; + rsp->schq_contig_list[lvl][idx] =3D schq; + continue; + } + + if (rsp->schq[lvl]) { + alloc =3D true; + rsp->schq_list[lvl][idx] =3D schq; + continue; + } + } + + if (!alloc) + dev_err(rvu->dev, + "Could not allocate schq at lvl=3D%u start=3D%u end=3D%u\n", + lvl, start, end); + return; + } /* A single TL queue is allocated */ if (rsp->schq_contig[lvl]) { rsp->schq_contig[lvl] =3D 1; @@ -2268,11 +2301,14 @@ int rvu_mbox_handler_nix_txsch_alloc(struct rvu *rv= u, rsp->schq[lvl] =3D req->schq[lvl]; rsp->schq_contig[lvl] =3D req->schq_contig[lvl]; =20 - link =3D nix_get_tx_link(rvu, pcifunc); + if (req->flags & NIX_TXSCH_ALLOC_FLAG_PAN) + link =3D hw->cgx_links + hw->lbk_links + 1; + else + link =3D nix_get_tx_link(rvu, pcifunc); =20 if (lvl >=3D hw->cap.nix_tx_aggr_lvl) { start =3D link; - end =3D link; + end =3D link + !!(req->flags & NIX_TXSCH_ALLOC_FLAG_PAN); } else if (hw->cap.nix_fixed_txschq_mapping) { nix_get_txschq_range(rvu, pcifunc, link, &start, &end); } else { @@ -2637,7 +2673,9 @@ static int nix_txschq_free_one(struct rvu *rvu, schq =3D req->schq; txsch =3D &nix_hw->txsch[lvl]; =20 - if (lvl >=3D hw->cap.nix_tx_aggr_lvl || schq >=3D txsch->schq.max) + if ((lvl >=3D hw->cap.nix_tx_aggr_lvl && + !(req->flags & TXSCHQ_FREE_PAN_TL1)) || + schq >=3D txsch->schq.max) return 0; =20 pfvf_map =3D txsch->pfvf_map; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c b/drive= rs/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c index 3d6f780635a5..925b0b02279e 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c @@ -1469,7 +1469,7 @@ int rvu_mbox_handler_npc_install_flow(struct rvu *rvu, } =20 /* ignore chan_mask in case pf func is not AF, revisit later */ - if (!is_pffunc_af(req->hdr.pcifunc)) + if (!req->set_chanmask && !is_pffunc_af(req->hdr.pcifunc)) req->chan_mask =3D 0xFFF; =20 err =3D npc_check_unsupported_flows(rvu, req->features, req->intf); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h b/drive= rs/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h index acf259d72008..73a98b94426b 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h @@ -78,6 +78,8 @@ struct otx2_rcv_queue { struct sg_list { u16 num_segs; u16 flags; + u16 cq_idx; + u16 len; u64 skb; u64 size[OTX2_MAX_FRAGS_IN_SQE]; u64 dma_addr[OTX2_MAX_FRAGS_IN_SQE]; --=20 2.43.0