From nobody Sun Feb 8 12:14:17 2026 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92A082343BE; Tue, 6 Jan 2026 02:15:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767665726; cv=none; b=aaPl9aKzpOgrtmYpGksHVs6zjBM8jahx0f3M37gRFJPItoEUVTrzLMULrU9bqJMAIDjWDCXDrWsrbnDEXah5wBgfCOdFvYB4Zk0unJds7QvwlYRFx4lLUyFSSL/mz4YaZbxzJAqsFdXwUMNBGCwRECT/Yih1E+ugHwVWjZkGAO0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767665726; c=relaxed/simple; bh=jQcwTPqcQQpIjZbXoVf6SSnGha8SuAdfncXwMTBHMS4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ozh5Sl32RSKnEFxBH7Kboyop2UAFcgsFRTvh59o3lNds6eap0u9NmJ4cyd4j6AAjrPmSsm7YCCTj756ERw8S9NY6AdEZbhV6c96I62nJ6U3AMXqqbtC6FspRGq5QSQ6FwOf/ahY6VHe/Fi3W/+H7io88ho4d8LbxXWYc//QC1SI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=OCv+agJs; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="OCv+agJs" Received: from pps.filterd (m0431383.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 605HucXD2346980; Mon, 5 Jan 2026 18:15:15 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=I GjuRgsy2cNSmTUaT45wzryX6YkPfhw2RCH0EUk8U9M=; b=OCv+agJsRRuztVeCo tFn4dS/5vHVBsc8i0IwGV3aRoSpwvLMwF1skyHPpYUJZ93VcQfSSPcqagoqo2+J7 KIggVjCOkf7GPquCe/KoT3tiMuQd0M3E48jBhPPfnaPf7bCLjDnT8LBa10/T9jtr A4dMRMKMqxHJbtts3L6AtvTkPRNchUbm+yRyuT99erCnap9XyvxQ/cOkGpbAJF8u qmOdNroQljOLpuxKlfWMNM9MtClFsp5NtYUCK2e7hErdw5edYIBJZr8QUhpCyD+r 4e1aE7Cu1u8FyWo4Psr+JXk1LAWagW2ydcjEJFGM+kvsw15F02JT2SXG/vwWGAzd HGOfg== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 4bfmrbuefh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 05 Jan 2026 18:15:15 -0800 (PST) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Mon, 5 Jan 2026 18:15:14 -0800 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Mon, 5 Jan 2026 18:15:14 -0800 Received: from rkannoth-OptiPlex-7090.. (unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id B6FCC3F70C3; Mon, 5 Jan 2026 18:15:11 -0800 (PST) From: Ratheesh Kannoth To: , , CC: , , , , , Ratheesh Kannoth Subject: [PATCH net-next 01/10] octeontx2-af: switch: Add AF to switch mbox and skeleton files Date: Tue, 6 Jan 2026 07:44:38 +0530 Message-ID: <20260106021447.2359108-2-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260106021447.2359108-1-rkannoth@marvell.com> References: <20260106021447.2359108-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=bN0b4f+Z c=1 sm=1 tr=0 ts=695c7033 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=M5GUcnROAAAA:8 a=77CTF0lh-Qqp0iihmhoA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: RvR59krtIlaY0ZGsmFOGMDpZC5Exr83L X-Proofpoint-GUID: RvR59krtIlaY0ZGsmFOGMDpZC5Exr83L X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA2MDAxOCBTYWx0ZWRfX4RV2tyVOOlVC IHFl64PGnArXGyWXrJOtCGY6PsRufe92lwh6vHHtEXhdcyi35hsSafLJlfLd9LEqbC6/WMuahMx Sc/tzuj33nYCE59WrRd6jKLnA5BtaEQF/JpU2aKLBJvNPMlv5gyRdgxqUSDZWaIDVt248Er2IUW tqvQxwrk/82AVIlxyoWCCuqlWF1xpGo5A3gewVmMit7oao8zXwWPpY9MkHT/CkHzzIVB7nVDjTL xuESXk4RKQkTBDc+Bon8x7GmqYz6hlPrn0ykINnLDu1dlmYlmqaYstzzeP4Mdg/GzGXYY3u0RPu qeZtozgarotQcWwadti1h4tBzvGmGvV6xhgpLRmNgHN874QPzHlfzuQRRVtbuh4HP78HXEM428g iexHymxDexDAqGFlo9Zfb8UnJbZ0HHRkLwGsO7FfllpQ1WqnvaM8k+6ttZnUbja0NTVYumoUeVt Se/RlYJXO261WH6L4qw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-05_02,2026-01-05_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" The Marvell switch hardware runs on a Linux OS. This OS receives various messages, which are parsed to create flow rules that can be installed on HW. The switch is capable of accelerating both L2 and L3 flows. This commit adds various mailbox messages used by the Linux OS (on arm64) to send events to the switch hardware. fdb messages: Linux bridge FDB messages fib messages: Linux routing table messages status messages: Packet status updates sent to Host Linux to keep flows active for connection-tracked flows. Signed-off-by: Ratheesh Kannoth --- .../ethernet/marvell/octeontx2/af/Makefile | 2 + .../net/ethernet/marvell/octeontx2/af/mbox.h | 95 +++++++++++++++++++ .../marvell/octeontx2/af/switch/rvu_sw_fl.c | 21 ++++ .../marvell/octeontx2/af/switch/rvu_sw_fl.h | 11 +++ .../marvell/octeontx2/af/switch/rvu_sw_l2.c | 14 +++ .../marvell/octeontx2/af/switch/rvu_sw_l2.h | 11 +++ .../marvell/octeontx2/af/switch/rvu_sw_l3.c | 14 +++ .../marvell/octeontx2/af/switch/rvu_sw_l3.h | 11 +++ 8 files changed, 179 insertions(+) create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw= _fl.c create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw= _fl.h create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw= _l2.c create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw= _l2.h create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw= _l3.c create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw= _l3.h diff --git a/drivers/net/ethernet/marvell/octeontx2/af/Makefile b/drivers/n= et/ethernet/marvell/octeontx2/af/Makefile index 244de500963e..e28b1fc6dbc6 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/Makefile +++ b/drivers/net/ethernet/marvell/octeontx2/af/Makefile @@ -4,6 +4,7 @@ # =20 ccflags-y +=3D -I$(src) +ccflags-y +=3D -I$(src) -I$(src)/switch/ obj-$(CONFIG_OCTEONTX2_MBOX) +=3D rvu_mbox.o obj-$(CONFIG_OCTEONTX2_AF) +=3D rvu_af.o =20 @@ -12,5 +13,6 @@ rvu_af-y :=3D cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \ rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \ rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o rvu_switch.o \ rvu_sdp.o rvu_npc_hash.o mcs.o mcs_rvu_if.o mcs_cnf10kb.o \ + switch/rvu_sw_l2.o switch/rvu_sw_l3.o switch/rvu_sw_fl.o\ rvu_rep.o cn20k/mbox_init.o cn20k/nix.o cn20k/debugfs.o \ cn20k/npa.o diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index a3e273126e4e..968b5540f77b 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -156,6 +156,14 @@ M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_c= ap_rsp) \ M(GET_REP_CNT, 0x00d, get_rep_cnt, msg_req, get_rep_cnt_rsp) \ M(ESW_CFG, 0x00e, esw_cfg, esw_cfg_req, msg_rsp) \ M(REP_EVENT_NOTIFY, 0x00f, rep_event_notify, rep_event, msg_rsp) \ +M(FDB_NOTIFY, 0x010, fdb_notify, \ + fdb_notify_req, msg_rsp) \ +M(FIB_NOTIFY, 0x011, fib_notify, \ + fib_notify_req, msg_rsp) \ +M(FL_NOTIFY, 0x012, fl_notify, \ + fl_notify_req, msg_rsp) \ +M(FL_GET_STATS, 0x013, fl_get_stats, \ + fl_get_stats_req, fl_get_stats_rsp) \ /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ @@ -1694,6 +1702,93 @@ struct rep_event { struct rep_evt_data evt_data; }; =20 +#define FDB_ADD BIT_ULL(0) +#define FDB_DEL BIT_ULL(1) +#define FIB_CMD BIT_ULL(2) +#define FL_ADD BIT_ULL(3) +#define FL_DEL BIT_ULL(4) +#define DP_ADD BIT_ULL(5) + +struct fdb_notify_req { + struct mbox_msghdr hdr; + u64 flags; + u8 mac[ETH_ALEN]; +}; + +struct fib_entry { + u64 cmd; + u64 gw_valid : 1; + u64 mac_valid : 1; + u64 vlan_valid: 1; + u64 host : 1; + u64 bridge : 1; + u16 vlan_tag; + u32 dst; + u32 dst_len; + u32 gw; + u16 port_id; + u8 nud_state; + u8 mac[ETH_ALEN]; +}; + +struct fib_notify_req { + struct mbox_msghdr hdr; + u16 cnt; + struct fib_entry entry[16]; +}; + +struct fl_tuple { + u32 ip4src; + u32 m_ip4src; + u32 ip4dst; + u32 m_ip4dst; + u16 sport; + u16 m_sport; + u16 dport; + u16 m_dport; + u16 eth_type; + u16 m_eth_type; + u8 proto; + u8 smac[6]; + u8 m_smac[6]; + u8 dmac[6]; + u8 m_dmac[6]; + u64 is_xdev_br : 1; + u64 is_indev_br : 1; + u64 uni_di : 1; + u16 in_pf; + u16 xmit_pf; + u64 features; + struct { /* FLOW_ACTION_MANGLE */ + u8 offset; + u8 type; + u32 mask; + u32 val; +#define MANGLE_ARR_SZ 9 + } mangle[MANGLE_ARR_SZ]; /* 2 for ETH, 1 for VLAN, 4 for IPv6, 2 for L4. = */ +#define MANGLE_LAYER_CNT 4 + u8 mangle_map[MANGLE_LAYER_CNT]; /* 1 for ETH, 1 for VLAN, 1 for L3, 1 f= or L4 */ + u8 mangle_cnt; +}; + +struct fl_notify_req { + struct mbox_msghdr hdr; + unsigned long cookie; + u64 flags; + u64 features; + struct fl_tuple tuple; +}; + +struct fl_get_stats_req { + struct mbox_msghdr hdr; + unsigned long cookie; +}; + +struct fl_get_stats_rsp { + struct mbox_msghdr hdr; + u64 pkts_diff; +}; + struct flow_msg { unsigned char dmac[6]; unsigned char smac[6]; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.c b= /drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.c new file mode 100644 index 000000000000..1f8b82a84a5d --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Marvell RVU Admin Function driver + * + * Copyright (C) 2026 Marvell. + * + */ +#include "rvu.h" + +int rvu_mbox_handler_fl_get_stats(struct rvu *rvu, + struct fl_get_stats_req *req, + struct fl_get_stats_rsp *rsp) +{ + return 0; +} + +int rvu_mbox_handler_fl_notify(struct rvu *rvu, + struct fl_notify_req *req, + struct msg_rsp *rsp) +{ + return 0; +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.h b= /drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.h new file mode 100644 index 000000000000..cf3e5b884f77 --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Marvell RVU Admin Function driver + * + * Copyright (C) 2026 Marvell. + * + */ + +#ifndef RVU_SW_FL_H +#define RVU_SW_FL_H + +#endif diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.c b= /drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.c new file mode 100644 index 000000000000..5f805bfa81ed --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.c @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Marvell RVU Admin Function driver + * + * Copyright (C) 2026 Marvell. + * + */ +#include "rvu.h" + +int rvu_mbox_handler_fdb_notify(struct rvu *rvu, + struct fdb_notify_req *req, + struct msg_rsp *rsp) +{ + return 0; +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.h b= /drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.h new file mode 100644 index 000000000000..ff28612150c9 --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Marvell RVU Admin Function driver + * + * Copyright (C) 2026 Marvell. + * + */ + +#ifndef RVU_SW_L2_H +#define RVU_SW_L2_H + +#endif diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.c b= /drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.c new file mode 100644 index 000000000000..2b798d5f0644 --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.c @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Marvell RVU Admin Function driver + * + * Copyright (C) 2026 Marvell. + * + */ +#include "rvu.h" + +int rvu_mbox_handler_fib_notify(struct rvu *rvu, + struct fib_notify_req *req, + struct msg_rsp *rsp) +{ + return 0; +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.h b= /drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.h new file mode 100644 index 000000000000..ac8c4f9ba5ac --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Marvell RVU Admin Function driver + * + * Copyright (C) 2026 Marvell. + * + */ + +#ifndef RVU_SW_L3_H +#define RVU_SW_L3_H + +#endif --=20 2.43.0 From nobody Sun Feb 8 12:14:17 2026 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C0D614A60C; Tue, 6 Jan 2026 02:15:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767665730; cv=none; b=Zfpk+G8eoVqfH2o6n6Koi6xDTBmUJACfYo4fgpScsKDJRdoCLuDYY/4CiYu5hWXU49Ex/Rp/t4VQRIlmBVcAl0ao5Y5CNEmX0OxVTKadrBISMcw4zqCiBWvsIVadU/lupoO1FN4YhLzqeJjdiD4i/H6gmm+U9SDMrHrwhIvJGqA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767665730; c=relaxed/simple; bh=sluuNilkipBhVDwAI4Fi80yHfNqJTaIMk9D9pzsCOZo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FO2tHIB6PiCGHf/9DMpJRBYPZvH+/AG109yd6eDfpP6Wemr51iPjbwycXmNWzOWLxmp5o/Wkhc1jl3NorPmPQdfqc4Za3Z9A0FsTLbD6KBS5pzYmpMtqagom2tjw7a7YKxgbxTgia2XgaAECHxEZMnXrSL3KRooX7VTxzUuxM+M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=YEZuGmD/; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="YEZuGmD/" Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 605ESYOO2795403; Mon, 5 Jan 2026 18:15:19 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=T AYcZ/vnvp/ZqT8+vaHyxie4mK0APnkPh1Vk0kRKg2A=; b=YEZuGmD/paBxi1a54 uZmbhuihssad8yTuMPmitgrxMsv6oYgI3nLZRbU16t/ZHQEM0HC7b8FKkyVRTUtM DJ+VWda7tLug5x796ezYoVR8I2uZi5p5Eg2DDBjp0gIlkq01HNFquIjM8FaQUPIs pHQn1D6Hx0AJ5IZrLnhvFaANjIrRtgp82qiFOPgietprU90excGj64Gt136GE7d/ aHxevWHZIga0smjOcQZih2S+aVsLTwL+MTigPgYs1Ny2lXTzGEHT1CbiMhoFchkg lhQl01ielhq9wAPaPL/p0Zhv/5taE9h42pt5ARpCNFP+RDVazsXx5+jBO8baFvZ3 JXRNw== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 4bgf3fsa4w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 05 Jan 2026 18:15:18 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Mon, 5 Jan 2026 18:15:32 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Mon, 5 Jan 2026 18:15:32 -0800 Received: from rkannoth-OptiPlex-7090.. (unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id DDBA33F70C3; Mon, 5 Jan 2026 18:15:14 -0800 (PST) From: Ratheesh Kannoth To: , , CC: , , , , , Ratheesh Kannoth Subject: [PATCH net-next 02/10] octeontx2-af: switch: Add switch dev to AF mboxes Date: Tue, 6 Jan 2026 07:44:39 +0530 Message-ID: <20260106021447.2359108-3-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260106021447.2359108-1-rkannoth@marvell.com> References: <20260106021447.2359108-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=PLgCOPqC c=1 sm=1 tr=0 ts=695c7036 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=M5GUcnROAAAA:8 a=WBe6_t-ORFUBTklN5yIA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA2MDAxOCBTYWx0ZWRfX4vPx+lT4+Wcg m9MrKMCoYHDj3txgq3vt+lGKgid85khJxeVmYANv+DlFEBdDDivIHxwhoDzYrnT1AYx4vy5lWwU iSxDzxsE7ePWnXc776WUBa11K2O6V6/0mnTHuEbt7eh/KgiJAVLd4gygsWc/pYCHydqoRJw6y30 fZOszER3QdmkMEcr/diMA5kPm2RQYbwemOo/CiAJD1NB7JE+DtS0cidBYGknkz4QFHd7BlaKAjH mPUfcoOpQPYTtDs049zO030v8uqlb/mG90DxPQdLT+FsYZPkdZQe7+ulMUIgs+x0kMkqIt61yFY eZDHarhM3R88RVpC7sqadhtPFmAMj+2MDVWHwbo+shTJeba0VfCDEK7hoQXWgjNR2WI2+dGgMpn SGl+Nx77McSRDniIqTY2Xka3w0OvzSyoui45GQyHZWZsyyMs6uFOuuTVO11TjXf13xgQecSFQMy aAnZ+K007qhnoq7X8LA== X-Proofpoint-GUID: kqFW7HpRJQjo6x5QKz0cgPxxZv0ttdHT X-Proofpoint-ORIG-GUID: kqFW7HpRJQjo6x5QKz0cgPxxZv0ttdHT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-05_02,2026-01-05_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" The Marvell switch hardware runs on a Linux OS. Switch needs various information from AF driver. These mboxes are defined to query those from AF driver. Signed-off-by: Ratheesh Kannoth --- .../ethernet/marvell/octeontx2/af/Makefile | 2 +- .../net/ethernet/marvell/octeontx2/af/mbox.h | 119 ++++++++++++++++++ .../net/ethernet/marvell/octeontx2/af/rvu.c | 110 +++++++++++++++- .../net/ethernet/marvell/octeontx2/af/rvu.h | 1 + .../ethernet/marvell/octeontx2/af/rvu_nix.c | 4 +- .../ethernet/marvell/octeontx2/af/rvu_npc.c | 77 +++++++++++- .../marvell/octeontx2/af/rvu_npc_fs.c | 11 ++ .../marvell/octeontx2/af/switch/rvu_sw.c | 15 +++ .../marvell/octeontx2/af/switch/rvu_sw.h | 11 ++ 9 files changed, 344 insertions(+), 6 deletions(-) create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw= .c create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw= .h diff --git a/drivers/net/ethernet/marvell/octeontx2/af/Makefile b/drivers/n= et/ethernet/marvell/octeontx2/af/Makefile index e28b1fc6dbc6..cd49b3fa5810 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/Makefile +++ b/drivers/net/ethernet/marvell/octeontx2/af/Makefile @@ -13,6 +13,6 @@ rvu_af-y :=3D cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \ rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \ rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o rvu_switch.o \ rvu_sdp.o rvu_npc_hash.o mcs.o mcs_rvu_if.o mcs_cnf10kb.o \ - switch/rvu_sw_l2.o switch/rvu_sw_l3.o switch/rvu_sw_fl.o\ + switch/rvu_sw.o switch/rvu_sw_l2.o switch/rvu_sw_l3.o switch/rvu_sw_fl= .o \ rvu_rep.o cn20k/mbox_init.o cn20k/nix.o cn20k/debugfs.o \ cn20k/npa.o diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index 968b5540f77b..a8b87097074b 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -164,6 +164,10 @@ M(FL_NOTIFY, 0x012, fl_notify, \ fl_notify_req, msg_rsp) \ M(FL_GET_STATS, 0x013, fl_get_stats, \ fl_get_stats_req, fl_get_stats_rsp) \ +M(GET_IFACE_GET_INFO, 0x014, iface_get_info, msg_req, \ + iface_get_info_rsp) \ +M(SWDEV2AF_NOTIFY, 0x015, swdev2af_notify, \ + swdev2af_notify_req, msg_rsp) \ /* CGX mbox IDs (range 0x200 - 0x3FF) */ \ M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \ M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \ @@ -283,6 +287,14 @@ M(NPC_GET_FIELD_HASH_INFO, 0x6013, npc_get_field_hash_= info, M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \ npc_get_field_status_req, \ npc_get_field_status_rsp) \ +M(NPC_MCAM_FLOW_DEL_N_FREE, 0x6020, npc_flow_del_n_free, \ + npc_flow_del_n_free_req, msg_rsp) \ +M(NPC_MCAM_GET_MUL_STATS, 0x6021, npc_mcam_mul_stats, \ + npc_mcam_get_mul_stats_req, \ + npc_mcam_get_mul_stats_rsp) \ +M(NPC_MCAM_GET_FEATURES, 0x6022, npc_mcam_get_features, \ + msg_req, \ + npc_mcam_get_features_rsp) \ /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \ nix_lf_alloc_req, nix_lf_alloc_rsp) \ @@ -412,6 +424,12 @@ M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_in= fo, msg_rsp) #define MBOX_UP_REP_MESSAGES \ M(REP_EVENT_UP_NOTIFY, 0xEF0, rep_event_up_notify, rep_event, msg_rsp) \ =20 +#define MBOX_UP_AF2SWDEV_MESSAGES \ +M(AF2SWDEV, 0xEF1, af2swdev_notify, af2swdev_notify_req, msg_rsp) + +#define MBOX_UP_AF2PF_FDB_REFRESH_MESSAGES \ +M(AF2PF_FDB_REFRESH, 0xEF2, af2pf_fdb_refresh, af2pf_fdb_refresh_req, msg= _rsp) + enum { #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name =3D _id, MBOX_MESSAGES @@ -419,6 +437,8 @@ MBOX_UP_CGX_MESSAGES MBOX_UP_CPT_MESSAGES MBOX_UP_MCS_MESSAGES MBOX_UP_REP_MESSAGES +MBOX_UP_AF2SWDEV_MESSAGES +MBOX_UP_AF2PF_FDB_REFRESH_MESSAGES #undef M }; =20 @@ -1550,6 +1570,30 @@ struct npc_mcam_alloc_entry_rsp { u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES]; }; =20 +struct npc_flow_del_n_free_req { + struct mbox_msghdr hdr; + u16 cnt; + u16 entry[256]; /* Entry index to be freed */ +}; + +struct npc_mcam_get_features_rsp { + struct mbox_msghdr hdr; + u64 rx_features; + u64 tx_features; +}; + +struct npc_mcam_get_mul_stats_req { + struct mbox_msghdr hdr; + int cnt; + u16 entry[256]; /* mcam entry */ +}; + +struct npc_mcam_get_mul_stats_rsp { + struct mbox_msghdr hdr; + int cnt; + u64 stat[256]; /* counter stats */ +}; + struct npc_mcam_free_entry_req { struct mbox_msghdr hdr; u16 entry; /* Entry index to be freed */ @@ -1789,6 +1833,81 @@ struct fl_get_stats_rsp { u64 pkts_diff; }; =20 +struct af2swdev_notify_req { + struct mbox_msghdr hdr; + u64 flags; + u32 port_id; + u32 switch_id; + union { + struct { + u8 mac[6]; + }; + struct { + u8 cnt; + struct fib_entry entry[16]; + }; + + struct { + unsigned long cookie; + u64 features; + struct fl_tuple tuple; + }; + }; +}; + +struct af2pf_fdb_refresh_req { + struct mbox_msghdr hdr; + u16 pcifunc; + u8 mac[6]; +}; + +struct iface_info { + u64 is_vf :1; + u64 is_sdp :1; + u16 pcifunc; + u16 rx_chan_base; + u16 tx_chan_base; + u16 sq_cnt; + u16 cq_cnt; + u16 rq_cnt; + u8 rx_chan_cnt; + u8 tx_chan_cnt; + u8 tx_link; + u8 nix; +}; + +struct iface_get_info_rsp { + struct mbox_msghdr hdr; + int cnt; + struct iface_info info[256 + 32]; /* 32 PFs + 256 Vs */ +}; + +struct fl_info { + unsigned long cookie; + u16 mcam_idx[2]; + u8 dis : 1; + u8 uni_di : 1; +}; + +struct swdev2af_notify_req { + struct mbox_msghdr hdr; + u64 msg_type; +#define SWDEV2AF_MSG_TYPE_FW_STATUS BIT_ULL(0) +#define SWDEV2AF_MSG_TYPE_REFRESH_FDB BIT_ULL(1) +#define SWDEV2AF_MSG_TYPE_REFRESH_FL BIT_ULL(2) + u16 pcifunc; + union { + bool fw_up; // FW_STATUS message + + u8 mac[ETH_ALEN]; // fdb refresh message + + struct { // fl refresh message + int cnt; + struct fl_info fl[64]; + }; + }; +}; + struct flow_msg { unsigned char dmac[6]; unsigned char smac[6]; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.c index 2d78e08f985f..6b61742a61b1 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c @@ -1396,7 +1396,6 @@ static void rvu_detach_block(struct rvu *rvu, int pci= func, int blktype) if (blkaddr < 0) return; =20 - block =3D &hw->block[blkaddr]; =20 num_lfs =3D rvu_get_rsrc_mapcount(pfvf, block->addr); @@ -1907,6 +1906,115 @@ int rvu_mbox_handler_msix_offset(struct rvu *rvu, s= truct msg_req *req, return 0; } =20 +int rvu_mbox_handler_iface_get_info(struct rvu *rvu, struct msg_req *req, + struct iface_get_info_rsp *rsp) +{ + struct iface_info *info; + struct rvu_pfvf *pfvf; + int pf, vf, numvfs; + u16 pcifunc; + int tot =3D 0; + u64 cfg; + + info =3D rsp->info; + for (pf =3D 0; pf < rvu->hw->total_pfs; pf++) { + cfg =3D rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf)); + numvfs =3D (cfg >> 12) & 0xFF; + + /* Skip not enabled PFs */ + if (!(cfg & BIT_ULL(20))) + goto chk_vfs; + + /* If Admin function, check on VFs */ + if (cfg & BIT_ULL(21)) + goto chk_vfs; + + pcifunc =3D rvu_make_pcifunc(rvu->pdev, pf, 0); + pfvf =3D rvu_get_pfvf(rvu, pcifunc); + + /* Populate iff at least one Tx channel */ + if (!pfvf->tx_chan_cnt) + goto chk_vfs; + + info->is_vf =3D 0; + info->pcifunc =3D pcifunc; + info->rx_chan_base =3D pfvf->rx_chan_base; + info->rx_chan_cnt =3D pfvf->rx_chan_cnt; + info->tx_chan_base =3D pfvf->tx_chan_base; + info->tx_chan_cnt =3D pfvf->tx_chan_cnt; + info->tx_link =3D nix_get_tx_link(rvu, pcifunc); + if (is_sdp_pfvf(rvu, pcifunc)) + info->is_sdp =3D 1; + + /* If interfaces are not UP, there are no queues */ + info->sq_cnt =3D 0; + info->cq_cnt =3D 0; + info->rq_cnt =3D 0; + + if (pfvf->sq_bmap) + info->sq_cnt =3D bitmap_weight(pfvf->sq_bmap, BITS_PER_LONG * 16); + + if (pfvf->cq_bmap) + info->cq_cnt =3D bitmap_weight(pfvf->cq_bmap, BITS_PER_LONG); + + if (pfvf->rq_bmap) + info->rq_cnt =3D bitmap_weight(pfvf->rq_bmap, BITS_PER_LONG); + + if (pfvf->nix_blkaddr =3D=3D BLKADDR_NIX0) + info->nix =3D 0; + else + info->nix =3D 1; + + info++; + tot++; + +chk_vfs: + for (vf =3D 0; vf < numvfs; vf++) { + pcifunc =3D rvu_make_pcifunc(rvu->pdev, pf, vf + 1); + pfvf =3D rvu_get_pfvf(rvu, pcifunc); + + if (!pfvf->tx_chan_cnt) + continue; + + info->is_vf =3D 1; + info->pcifunc =3D pcifunc; + info->rx_chan_base =3D pfvf->rx_chan_base; + info->rx_chan_cnt =3D pfvf->rx_chan_cnt; + info->tx_chan_base =3D pfvf->tx_chan_base; + info->tx_chan_cnt =3D pfvf->tx_chan_cnt; + info->tx_link =3D nix_get_tx_link(rvu, pcifunc); + if (is_sdp_pfvf(rvu, pcifunc)) + info->is_sdp =3D 1; + + /* If interfaces are not UP, there are no queues */ + info->sq_cnt =3D 0; + info->cq_cnt =3D 0; + info->rq_cnt =3D 0; + + if (pfvf->sq_bmap) + info->sq_cnt =3D bitmap_weight(pfvf->sq_bmap, BITS_PER_LONG * 16); + + if (pfvf->cq_bmap) + info->cq_cnt =3D bitmap_weight(pfvf->cq_bmap, BITS_PER_LONG); + + if (pfvf->rq_bmap) + info->rq_cnt =3D bitmap_weight(pfvf->rq_bmap, BITS_PER_LONG); + + if (pfvf->nix_blkaddr =3D=3D BLKADDR_NIX0) + info->nix =3D 0; + else + info->nix =3D 1; + + info++; + + tot++; + } + } + rsp->cnt =3D tot; + + return 0; +} + int rvu_mbox_handler_free_rsrc_cnt(struct rvu *rvu, struct msg_req *req, struct free_rsrcs_rsp *rsp) { diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.h index e85dac2c806d..4e11cdf5df63 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -1147,6 +1147,7 @@ void rvu_program_channels(struct rvu *rvu); =20 /* CN10K NIX */ void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw); +int nix_get_tx_link(struct rvu *rvu, u16 pcifunc); =20 /* CN10K RVU - LMT*/ void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_nix.c index 2f485a930edd..e2cc33ad2b2c 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -31,7 +31,6 @@ static int nix_free_all_bandprof(struct rvu *rvu, u16 pci= func); static void nix_clear_ratelimit_aggr(struct rvu *rvu, struct nix_hw *nix_h= w, u32 leaf_prof); static const char *nix_get_ctx_name(int ctype); -static int nix_get_tx_link(struct rvu *rvu, u16 pcifunc); =20 enum mc_tbl_sz { MC_TBL_SZ_256, @@ -2055,7 +2054,7 @@ static void nix_clear_tx_xoff(struct rvu *rvu, int bl= kaddr, rvu_write64(rvu, blkaddr, reg, 0x0); } =20 -static int nix_get_tx_link(struct rvu *rvu, u16 pcifunc) +int nix_get_tx_link(struct rvu *rvu, u16 pcifunc) { struct rvu_hwinfo *hw =3D rvu->hw; int pf =3D rvu_get_pf(rvu->pdev, pcifunc); @@ -5283,7 +5282,6 @@ int rvu_mbox_handler_nix_lf_stop_rx(struct rvu *rvu, = struct msg_req *req, /* Disable the interface if it is in any multicast list */ nix_mcast_update_mce_entry(rvu, pcifunc, 0); =20 - pfvf =3D rvu_get_pfvf(rvu, pcifunc); clear_bit(NIXLF_INITIALIZED, &pfvf->flags); =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_npc.c index c7c70429eb6c..4e2d24069d88 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c @@ -2815,6 +2815,42 @@ int rvu_mbox_handler_npc_mcam_free_entry(struct rvu = *rvu, return rc; } =20 +int rvu_mbox_handler_npc_flow_del_n_free(struct rvu *rvu, + struct npc_flow_del_n_free_req *mreq, + struct msg_rsp *rsp) +{ + struct npc_mcam_free_entry_req sreq =3D { 0 }; + struct npc_delete_flow_req dreq =3D { 0 }; + struct npc_delete_flow_rsp drsp =3D { 0 }; + int err, ret =3D 0; + + sreq.hdr.pcifunc =3D mreq->hdr.pcifunc; + dreq.hdr.pcifunc =3D mreq->hdr.pcifunc; + + if (!mreq->cnt || mreq->cnt > 256) { + dev_err(rvu->dev, "Invalid cnt=3D%d\n", mreq->cnt); + return -EINVAL; + } + + for (int i =3D 0; i < mreq->cnt; i++) { + dreq.entry =3D mreq->entry[i]; + err =3D rvu_mbox_handler_npc_delete_flow(rvu, &dreq, &drsp); + if (err) + dev_err(rvu->dev, "delete flow error for i=3D%d entry=3D%d\n", + i, mreq->entry[i]); + ret |=3D err; + + sreq.entry =3D mreq->entry[i]; + err =3D rvu_mbox_handler_npc_mcam_free_entry(rvu, &sreq, rsp); + if (err) + dev_err(rvu->dev, "free entry error for i=3D%d entry=3D%d\n", + i, mreq->entry[i]); + ret |=3D err; + } + + return ret; +} + int rvu_mbox_handler_npc_mcam_read_entry(struct rvu *rvu, struct npc_mcam_read_entry_req *req, struct npc_mcam_read_entry_rsp *rsp) @@ -3029,7 +3065,6 @@ static int __npc_mcam_alloc_counter(struct rvu *rvu, if (!req->contig && req->count > NPC_MAX_NONCONTIG_COUNTERS) return NPC_MCAM_INVALID_REQ; =20 - /* Check if unused counters are available or not */ if (!rvu_rsrc_free_count(&mcam->counters)) { return NPC_MCAM_ALLOC_FAILED; @@ -3577,6 +3612,46 @@ int rvu_mbox_handler_npc_mcam_entry_stats(struct rvu= *rvu, return 0; } =20 +int rvu_mbox_handler_npc_mcam_mul_stats(struct rvu *rvu, + struct npc_mcam_get_mul_stats_req *req, + struct npc_mcam_get_mul_stats_rsp *rsp) +{ + struct npc_mcam *mcam =3D &rvu->hw->mcam; + u16 index, cntr; + int blkaddr; + u64 regval; + u32 bank; + + if (!req->cnt || req->cnt > 256) { + dev_err(rvu->dev, "%s invalid request cnt=3D%d\n", + __func__, req->cnt); + return -EINVAL; + } + + blkaddr =3D rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); + if (blkaddr < 0) + return NPC_MCAM_INVALID_REQ; + + mutex_lock(&mcam->lock); + + for (int i =3D 0; i < req->cnt; i++) { + index =3D req->entry[i] & (mcam->banksize - 1); + bank =3D npc_get_bank(mcam, req->entry[i]); + + /* read MCAM entry STAT_ACT register */ + regval =3D rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_STAT_ACT(index, = bank)); + cntr =3D regval & 0x1FF; + + rsp->stat[i] =3D rvu_read64(rvu, blkaddr, NPC_AF_MATCH_STATX(cntr)); + rsp->stat[i] &=3D BIT_ULL(48) - 1; + } + + rsp->cnt =3D req->cnt; + + mutex_unlock(&mcam->lock); + return 0; +} + void rvu_npc_clear_ucast_entry(struct rvu *rvu, int pcifunc, int nixlf) { struct npc_mcam *mcam =3D &rvu->hw->mcam; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c b/drive= rs/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c index b56395ac5a74..3d6f780635a5 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c @@ -1549,6 +1549,17 @@ static int npc_delete_flow(struct rvu *rvu, struct r= vu_npc_mcam_rule *rule, return rvu_mbox_handler_npc_mcam_dis_entry(rvu, &dis_req, &dis_rsp); } =20 +int rvu_mbox_handler_npc_mcam_get_features(struct rvu *rvu, + struct msg_req *req, + struct npc_mcam_get_features_rsp *rsp) +{ + struct npc_mcam *mcam =3D &rvu->hw->mcam; + + rsp->rx_features =3D mcam->rx_features; + rsp->tx_features =3D mcam->tx_features; + return 0; +} + int rvu_mbox_handler_npc_delete_flow(struct rvu *rvu, struct npc_delete_flow_req *req, struct npc_delete_flow_rsp *rsp) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c b/dr= ivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c new file mode 100644 index 000000000000..fe143ad3f944 --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Marvell RVU Admin Function driver + * + * Copyright (C) 2026 Marvell. + * + */ + +#include "rvu.h" + +int rvu_mbox_handler_swdev2af_notify(struct rvu *rvu, + struct swdev2af_notify_req *req, + struct msg_rsp *rsp) +{ + return 0; +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.h b/dr= ivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.h new file mode 100644 index 000000000000..f28dba556d80 --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Marvell RVU Admin Function driver + * + * Copyright (C) 2026 Marvell. + * + */ + +#ifndef RVU_SWITCH_H +#define RVU_SWITCH_H + +#endif --=20 2.43.0 From nobody Sun Feb 8 12:14:17 2026 Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3988D6A33B; Tue, 6 Jan 2026 02:15:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767665732; cv=none; b=qPdutBqbMkM0J0gu55M6P+HOjH4NlQoM++U5tisrXAupIdUdUgvTjlrEfjAmrFf4DC2htI+eWz9ap5NYBj0v7dpxBTc4NMNhDmuk/WZjgQT7MuHZtU8H0WjwMw4kLs7e64RndxcsAkO2nwVBEewwHc4hzCfiiqgOkMEhzIrx6WI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767665732; c=relaxed/simple; bh=VPL7cY5hXj3FpxTvpOsbsODW83prXCZ0lMzheuXz8Fs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DQf1YXDtCUgcmJKYZ1hgllBIeBkXOUNtS/eqMnsf7JQukjjGiTY2bMZeaEaLIYiHAJNkmKgjgDsQbf1wCSZTtcvPzOdPTtSbCVlteT3pQoF6yseotIfdveUfZ9fxW8/sQj1Ngvmn5Pki3Ego04NMzJy/QLZ8lS2GhTAwrTRvT+U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=C006j4Ey; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="C006j4Ey" Received: from pps.filterd (m0431384.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 605HTIWg2641688; Mon, 5 Jan 2026 18:15:21 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=T gBybVPPCOIc6IngKgSVGMqcbXcX2DK8HxdJjFvtc7E=; b=C006j4EyS8N89YB86 2ZbPUFTgj8Y88hQUrdn08sneqRlGvFzv5AEWdYEs6CW1tnrLHJk8m7cJ5H3MFS/M WutdFVEiWD0a7YwHqiA0m5x/HaH253/gPIrNgbwhlmDoL9bDVHQl6Ap+71PNdX1N p7XgOXyXRHBnGYGn7lpntsn7X1BTlbtXXNQXuyoSSGm8nlGWh2h5ePdd1KeDmT9V 9YdIQJJeen8FS4vmLRQrtB9mVe51e+FyaFFRdjIINbtugTsZpISe6lFf9F8BKaAU DfsCF/NZOspzt49fiZld1egW7ZklvE8InGD+WueVbzHoMe+5eYI8bDf7f9gyHNgH bbmiQ== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 4bfr8bk7ye-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 05 Jan 2026 18:15:21 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Mon, 5 Jan 2026 18:15:35 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Mon, 5 Jan 2026 18:15:35 -0800 Received: from rkannoth-OptiPlex-7090.. (unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id 0F2273F70C4; Mon, 5 Jan 2026 18:15:17 -0800 (PST) From: Ratheesh Kannoth To: , , CC: , , , , , Ratheesh Kannoth Subject: [PATCH net-next 03/10] octeontx2-pf: switch: Add pf files hierarchy Date: Tue, 6 Jan 2026 07:44:40 +0530 Message-ID: <20260106021447.2359108-4-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260106021447.2359108-1-rkannoth@marvell.com> References: <20260106021447.2359108-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: upjjShMv1994MdZ78AFaazzrEylAC5Ph X-Proofpoint-GUID: upjjShMv1994MdZ78AFaazzrEylAC5Ph X-Authority-Analysis: v=2.4 cv=P/I3RyAu c=1 sm=1 tr=0 ts=695c7039 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=M5GUcnROAAAA:8 a=rErRu6woPkWivxaahN8A:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA2MDAxOCBTYWx0ZWRfX7ISvLJNn8M/I RlmcyWVMahxKo9MQtoshNMLyD+/VIYy5KqeoEktq7ZRxf2FdEHNvD1UvlfrSnhZQ4RGjAZj/11U TvQfKJn0vAbv7STNT+9CaYnyl7Xj86gNN3HkHcthPdWKZ4cpHKSTDD44DedFuX8lWjn5mKx+btj /D3455HhUzRWUb/JHWcgeyW2lP0mrfCC3pZ4p6bmMY+LUjuku0zb5uboIngzBItrVzM2RRO5Q4m QJF8g11/ahWRekmb6ix87qvNKNIaWbb8FzuNnYZ+HXgQpf2jXlLnShKib7OkYTZHPlbgMlmq2Ms eoEpLtqjJ9KFGEu3S7ubRv2SC6BhVa9L4HHpYsr7TINLK90Xm0obRPLqIP4U9VxY3njJP4HeZwg xmvp5V1qczySzG0rctkDpKZmCbrYVB22Wz+yU7+GRwQMK/8OTWvRkBgHhd8y58oSYj+eG5snd5n IQ3maeukZbQZ8q6ex5w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-05_02,2026-01-05_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" PF driver skeleton files. Follow up patches add meat to these files. sw_nb* : Implements various notifier callbacks for linux events sw_fdb* : L2 offload sw_fib* : L3 offload sw_fl* : Flow based offload (ovs, nft etc) Signed-off-by: Ratheesh Kannoth --- drivers/net/ethernet/marvell/octeontx2/Kconfig | 12 ++++++++++++ .../net/ethernet/marvell/octeontx2/nic/Makefile | 8 +++++++- .../marvell/octeontx2/nic/switch/sw_fdb.c | 16 ++++++++++++++++ .../marvell/octeontx2/nic/switch/sw_fdb.h | 13 +++++++++++++ .../marvell/octeontx2/nic/switch/sw_fib.c | 16 ++++++++++++++++ .../marvell/octeontx2/nic/switch/sw_fib.h | 13 +++++++++++++ .../marvell/octeontx2/nic/switch/sw_fl.c | 16 ++++++++++++++++ .../marvell/octeontx2/nic/switch/sw_fl.h | 13 +++++++++++++ .../marvell/octeontx2/nic/switch/sw_nb.c | 17 +++++++++++++++++ .../marvell/octeontx2/nic/switch/sw_nb.h | 13 +++++++++++++ 10 files changed, 136 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fd= b.c create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fd= b.h create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fi= b.c create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fi= b.h create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl= .c create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl= .h create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb= .c create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb= .h diff --git a/drivers/net/ethernet/marvell/octeontx2/Kconfig b/drivers/net/e= thernet/marvell/octeontx2/Kconfig index 35c4f5f64f58..a883efc9d9dd 100644 --- a/drivers/net/ethernet/marvell/octeontx2/Kconfig +++ b/drivers/net/ethernet/marvell/octeontx2/Kconfig @@ -28,6 +28,18 @@ config NDC_DIS_DYNAMIC_CACHING , NPA stack pages etc in NDC. Also locks down NIX SQ/CQ/RQ/RSS and NPA Aura/Pool contexts. =20 +config OCTEONTX_SWITCH + tristate "Marvell OcteonTX2 switch driver" + select OCTEONTX2_MBOX + select NET_DEVLINK + default n + select PAGE_POOL + depends on (64BIT && COMPILE_TEST) || ARM64 + help + This driver supports Marvell's OcteonTX2 switch driver. + Marvell SW HW can offload L2, L3 offload. ARM core interacts + with Marvell SW HW thru mbox. + config OCTEONTX2_PF tristate "Marvell OcteonTX2 NIC Physical Function driver" select OCTEONTX2_MBOX diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/Makefile b/drivers/= net/ethernet/marvell/octeontx2/nic/Makefile index 883e9f4d601c..da87e952c187 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/Makefile +++ b/drivers/net/ethernet/marvell/octeontx2/nic/Makefile @@ -9,7 +9,13 @@ obj-$(CONFIG_RVU_ESWITCH) +=3D rvu_rep.o =20 rvu_nicpf-y :=3D otx2_pf.o otx2_common.o otx2_txrx.o otx2_ethtool.o \ otx2_flows.o otx2_tc.o cn10k.o cn20k.o otx2_dmac_flt.o \ - otx2_devlink.o qos_sq.o qos.o otx2_xsk.o + otx2_devlink.o qos_sq.o qos.o otx2_xsk.o \ + switch/sw_fdb.o switch/sw_fl.o + +ifdef CONFIG_OCTEONTX_SWITCH +rvu_nicpf-y +=3D switch/sw_nb.o switch/sw_fib.o +endif + rvu_nicvf-y :=3D otx2_vf.o rvu_rep-y :=3D rep.o =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.c b/d= rivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.c new file mode 100644 index 000000000000..6842c8d91ffc --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Marvell RVU switch driver + * + * Copyright (C) 2026 Marvell. + * + */ +#include "sw_fdb.h" + +int sw_fdb_init(void) +{ + return 0; +} + +void sw_fdb_deinit(void) +{ +} diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.h b/d= rivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.h new file mode 100644 index 000000000000..d4314d6d3ee4 --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Marvell switch driver + * + * Copyright (C) 2026 Marvell. + * + */ +#ifndef SW_FDB_H_ +#define SW_FDB_H_ + +void sw_fdb_deinit(void); +int sw_fdb_init(void); + +#endif // SW_FDB_H diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.c b/d= rivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.c new file mode 100644 index 000000000000..12ddf8119372 --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Marvell RVU switch driver + * + * Copyright (C) 2026 Marvell. + * + */ +#include "sw_fib.h" + +int sw_fib_init(void) +{ + return 0; +} + +void sw_fib_deinit(void) +{ +} diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.h b/d= rivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.h new file mode 100644 index 000000000000..a51d15c2b80e --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Marvell switch driver + * + * Copyright (C) 2026 Marvell. + * + */ +#ifndef SW_FIB_H_ +#define SW_FIB_H_ + +void sw_fib_deinit(void); +int sw_fib_init(void); + +#endif // SW_FIB_H diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.c b/dr= ivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.c new file mode 100644 index 000000000000..36a2359a0a48 --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Marvell RVU switch driver + * + * Copyright (C) 2026 Marvell. + * + */ +#include "sw_fl.h" + +int sw_fl_init(void) +{ + return 0; +} + +void sw_fl_deinit(void) +{ +} diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.h b/dr= ivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.h new file mode 100644 index 000000000000..cd018d770a8a --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Marvell switch driver + * + * Copyright (C) 2026 Marvell. + * + */ +#ifndef SW_FL_H_ +#define SW_FL_H_ + +void sw_fl_deinit(void); +int sw_fl_init(void); + +#endif // SW_FL_H diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c b/dr= ivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c new file mode 100644 index 000000000000..2d14a0590c5d --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Marvell RVU switch driver + * + * Copyright (C) 2026 Marvell. + * + */ +#include "sw_nb.h" + +int sw_nb_unregister(void) +{ + return 0; +} + +int sw_nb_register(void) +{ + return 0; +} diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.h b/dr= ivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.h new file mode 100644 index 000000000000..503a0e18cfd7 --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Marvell switch driver + * + * Copyright (C) 2026 Marvell. + * + */ +#ifndef SW_NB_H_ +#define SW_NB_H_ + +int sw_nb_register(void); +int sw_nb_unregister(void); + +#endif // SW_NB_H__ --=20 2.43.0 From nobody Sun Feb 8 12:14:17 2026 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F57D23D7D8; Tue, 6 Jan 2026 02:15:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767665734; cv=none; b=NCfgQfn9ZzVaxGdEkxXCkE5XarjewvW5HRlpWutmuvr8TEEUmXVprAWS8jEV1JGMjGTM9RSIWORg1RbCoSLg6ilMi2U4Jhs10vGT6JRpu9X0vjGkDIW1xCJMpnSa2+8EgUVSDMelEx8TBV+jdxhg/PYtPHRb5wYYIsnLH5OztKY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767665734; c=relaxed/simple; bh=hoKXE4lLTAg13Kf793kjnvzidmCdtx+Lfe+6rOSs2e4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GsksXrXM6cndukFV10PG7Ffwr8maqHRwTsI07oEyFX6XrDed4w/UOsOI28FAimJiX63g7825R8e8jazkGOr/HnWcs+TMktZbvNXgXX/FP3P7BkryPGl/DZlEnAdgQdl/CuFdxS5rxWoOf5MlRmVCdR2/NBOZCxl1c/RQRfTjhRw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=T4i0TORY; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="T4i0TORY" Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 605ESk0G2795732; Mon, 5 Jan 2026 18:15:24 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=Q GoF17njsUrCfD1lvK4vrRFPeuxX53XZxnCm0J+oisk=; b=T4i0TORYvhANctxrF u9gzP59l/JVUpbkxSUUvpEEZlJT4I63HY6id19++MaLusSOfI4mnPgQiOtUDQnW6 NXsl2IIuJ7pUFho4o63rds4ybf2gR+WcPX2sJw4tAB1wEjmuQY4WdScrU+npZvvy ljmqM/mqZg450pl4E486ZhhHdJvCzzB4QYncRIgNPmWQZAQQqy0jM6BHgcdJvsS5 Z7eSQOq1cqKhRc3WqVlihVihgJd9NH9bLVltAW21dN3m+uOtEVO49YWmLmDX6qMF yupbkP2OQI1fQ6/BNd5D813kCvQ3lDD2Yn3gIRG7XY3LtmOZIUtTN+jr2ylOAQh6 KKNjA== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 4bgf3fsa58-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 05 Jan 2026 18:15:24 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Mon, 5 Jan 2026 18:15:38 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Mon, 5 Jan 2026 18:15:38 -0800 Received: from rkannoth-OptiPlex-7090.. (unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id 3530E3F70C3; Mon, 5 Jan 2026 18:15:20 -0800 (PST) From: Ratheesh Kannoth To: , , CC: , , , , , Ratheesh Kannoth Subject: [PATCH net-next 04/10] octeontx2-af: switch: Representor for switch port Date: Tue, 6 Jan 2026 07:44:41 +0530 Message-ID: <20260106021447.2359108-5-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260106021447.2359108-1-rkannoth@marvell.com> References: <20260106021447.2359108-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=PLgCOPqC c=1 sm=1 tr=0 ts=695c703c cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=M5GUcnROAAAA:8 a=xXrhxGPyklmKcrYTpSYA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA2MDAxOCBTYWx0ZWRfXypnjgLqhLn3u czxqPEPg8rODxLv5poFH4jgUcI9LhT6NzT3uJBPXIkqVS1yZC2Y9xvqJ+B8E4p9kQyJ2Vp7/kq9 RA2PxHkszvdsK42KiUo96N2E5ooDEz3ghfQ+GoJCP+vl262VEVEtz0YDYZso8I0xWg0zA/M0fXr ErzE09zDwvrmn6zU7BivunYFbi8GlLCjUaACWBjlR/PBw4FV95TsiEpb/Gz+K5VslYnznSwV14b AXNkE8ChEBgDFnT3ek27XaFSLXGGXYr59rsBzA0IloMfNpkqFeUYCDzk2gwfCL8aUTJombbVH+f ZX9TLUnZLX0uaeI8jKliC04CFQ4k6P6dgrGSoLx5ShrV7Aommed25Iz13HbmHopHYIaULEZ2xur Za5Zc7evqcg56kJDuy4xZa0HUetTKdhz/goDwkodLRIagXwUGWk7YiuxPpSrjwR3O0423QWsQNe 55O04HziWwdFRjuitEw== X-Proofpoint-GUID: 4KNgm2Csmq0rFjWWqbTC8XTtqqC6GSq2 X-Proofpoint-ORIG-GUID: 4KNgm2Csmq0rFjWWqbTC8XTtqqC6GSq2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-05_02,2026-01-05_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Representor support is already available in AF driver. When Representors are enabled through devlink, switch id and various information are collected from AF driver and sent to switchdev thru mbox message. This message enables switchdev HW. Signed-off-by: Ratheesh Kannoth --- drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 1 + drivers/net/ethernet/marvell/octeontx2/af/rvu.h | 5 +++++ .../net/ethernet/marvell/octeontx2/af/rvu_rep.c | 3 ++- .../ethernet/marvell/octeontx2/af/switch/rvu_sw.c | 14 ++++++++++++++ .../ethernet/marvell/octeontx2/af/switch/rvu_sw.h | 3 +++ drivers/net/ethernet/marvell/octeontx2/nic/rep.c | 4 ++++ 6 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index a8b87097074b..bb38d06c925c 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -1721,6 +1721,7 @@ struct get_rep_cnt_rsp { struct esw_cfg_req { struct mbox_msghdr hdr; u8 ena; + unsigned char switch_id[MAX_PHYS_ITEM_ID_LEN]; u64 rsvd; }; =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.h index 4e11cdf5df63..0f3d1b38a7dd 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -567,6 +567,10 @@ struct rvu_switch { u16 *entry2pcifunc; u16 mode; u16 start_entry; + unsigned char switch_id[MAX_PHYS_ITEM_ID_LEN]; +#define RVU_SWITCH_FLAG_FW_READY BIT_ULL(0) + u64 flags; + u16 pcifunc; }; =20 struct rep_evtq_ent { @@ -1185,4 +1189,5 @@ int rvu_rep_pf_init(struct rvu *rvu); int rvu_rep_install_mcam_rules(struct rvu *rvu); void rvu_rep_update_rules(struct rvu *rvu, u16 pcifunc, bool ena); int rvu_rep_notify_pfvf_state(struct rvu *rvu, u16 pcifunc, bool enable); +u16 rvu_rep_get_vlan_id(struct rvu *rvu, u16 pcifunc); #endif /* RVU_H */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_rep.c index 4415d0ce9aef..078ba5bd2369 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_rep.c @@ -181,7 +181,7 @@ int rvu_mbox_handler_nix_lf_stats(struct rvu *rvu, return 0; } =20 -static u16 rvu_rep_get_vlan_id(struct rvu *rvu, u16 pcifunc) +u16 rvu_rep_get_vlan_id(struct rvu *rvu, u16 pcifunc) { int id; =20 @@ -428,6 +428,7 @@ int rvu_mbox_handler_esw_cfg(struct rvu *rvu, struct es= w_cfg_req *req, return 0; =20 rvu->rep_mode =3D req->ena; + memcpy(rvu->rswitch.switch_id, req->switch_id, MAX_PHYS_ITEM_ID_LEN); =20 if (!rvu->rep_mode) rvu_npc_free_mcam_entries(rvu, req->hdr.pcifunc, -1); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c b/dr= ivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c index fe143ad3f944..533ee8725e38 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c @@ -6,6 +6,20 @@ */ =20 #include "rvu.h" +#include "rvu_sw.h" + +u32 rvu_sw_port_id(struct rvu *rvu, u16 pcifunc) +{ + u16 port_id; + u16 rep_id; + + rep_id =3D rvu_rep_get_vlan_id(rvu, pcifunc); + + port_id =3D FIELD_PREP(GENMASK_ULL(31, 16), rep_id) | + FIELD_PREP(GENMASK_ULL(15, 0), pcifunc); + + return port_id; +} =20 int rvu_mbox_handler_swdev2af_notify(struct rvu *rvu, struct swdev2af_notify_req *req, diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.h b/dr= ivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.h index f28dba556d80..847a8da60d0a 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.h @@ -8,4 +8,7 @@ #ifndef RVU_SWITCH_H #define RVU_SWITCH_H =20 +/* RVU Switch */ +u32 rvu_sw_port_id(struct rvu *rvu, u16 pcifunc); + #endif diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c b/drivers/net= /ethernet/marvell/octeontx2/nic/rep.c index b476733a0234..9200198be71f 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/rep.c @@ -399,8 +399,11 @@ static void rvu_rep_get_stats64(struct net_device *dev, =20 static int rvu_eswitch_config(struct otx2_nic *priv, u8 ena) { + struct devlink_port_attrs attrs =3D {}; struct esw_cfg_req *req; =20 + rvu_rep_devlink_set_switch_id(priv, &attrs.switch_id); + mutex_lock(&priv->mbox.lock); req =3D otx2_mbox_alloc_msg_esw_cfg(&priv->mbox); if (!req) { @@ -408,6 +411,7 @@ static int rvu_eswitch_config(struct otx2_nic *priv, u8= ena) return -ENOMEM; } req->ena =3D ena; + memcpy(req->switch_id, attrs.switch_id.id, attrs.switch_id.id_len); otx2_sync_mbox_msg(&priv->mbox); mutex_unlock(&priv->mbox.lock); return 0; --=20 2.43.0 From nobody Sun Feb 8 12:14:17 2026 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3909023DEB6; Tue, 6 Jan 2026 02:15:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767665737; cv=none; b=gbBd5rmfh4z1dcB/rLsCgENi0+a9uB7Z/R4mVcWRNdfmZjvnE9pZUnb01wtM3xl/vbAGSaeM9fLsmh4RziaoAZprRpKICzd4ZInKojbtlGjrLxSiy9k6dMRJyorJ7iaoktwRw9HiFLhn91xwmvF7xnodHzusGpPPULlvdD/Rsvo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767665737; c=relaxed/simple; bh=KrddKFBgrXZxHMEBNbnPqOAzC9ngSOSJaBlHj0DTtFo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=o7RKVVy05JEXrYcwQNUoxE4/+1z6zd4svHt9pICwi80vAUW7JAYwzD9Vd0qmLUVUk+3tg2jQtCZeVAERJJaFTbj+tIJgueiR0TjFerS6r0VcstDG7phD8GFcdc9LJnZ8QmQ7X38n2dPiWDEfdtX/oUp7Orpwm6JCpidEaJsox7Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=jOJjs3En; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="jOJjs3En" Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6060stHK128574; Mon, 5 Jan 2026 18:15:28 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=+ 5B4ivlektTw++wrQS8Gey0M8ADHtIHURu6ogo3oI08=; b=jOJjs3EnhWqFwZTjb Es3qNj4+KsYH2+vYJyaEedJ3ZkaBSXR5+QDGWz+nW1QSrYOJf6FqS7g0RiseWZLo CTDxF69kSikYJLK9XYd1P9KeWcClQLbORPyZ+DdT5+UVrDUu1PjFjqjj8U3UoNX7 qdbUzgRfHYGh0a3MC4/fOVBGwSP4Q+U8QteslWSOUFLa76D9K36ZX7/JpOs1jmU/ waHNt0RhiOzGEaJcMMLuad+BsglLd68+6DxZaOvgdX2T2ZvNui69fu0cuE7c40bF /TF2HG8i0fbC4G8LB1WbOYSqRNpH44r98Vdc0Slw2fB7XszuEqkTsFV6Nbp1AhRP YkioQ== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 4bg9crhvx6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 05 Jan 2026 18:15:28 -0800 (PST) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Mon, 5 Jan 2026 18:15:27 -0800 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Mon, 5 Jan 2026 18:15:27 -0800 Received: from rkannoth-OptiPlex-7090.. (unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id 5AEC63F70C4; Mon, 5 Jan 2026 18:15:24 -0800 (PST) From: Ratheesh Kannoth To: , , CC: , , , , , Ratheesh Kannoth Subject: [PATCH net-next 05/10] octeontx2-af: switch: Enable Switch hw port for all channels Date: Tue, 6 Jan 2026 07:44:42 +0530 Message-ID: <20260106021447.2359108-6-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260106021447.2359108-1-rkannoth@marvell.com> References: <20260106021447.2359108-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA2MDAxOCBTYWx0ZWRfX/u/ulBUhJGRr zX/RSiT0k/WqltMP9bhnLEtToMi6v5PehvHnOws++F09zaEDwDhFgx+3VUoQZdQgZtavTUiTtE7 7vEGF8ZweID7Jih54dZdvT2Wmtnc5fYthqlrc1U8up0NIHI/F/J4J+W6Nj4fcblDu7eKHzE3Z+L B1xf3HLKibiziBCeeVmp5NoYVuHMXw7DgxNMqOw+efpklIeJkOvsoVR4NH3WzBqalGDhgFbQB9h ogbodPitwDmCn4xcid2WMzApRw+7Rpeo7j9e1PKS0iverXB8P9xzkcIemS46LOftcEpnO+0VYGx 2ZxWwRWB386wKSb1OY4eT/MfOwEh7/2RoP7JiDb0QPcYV44YT7Ypuq1ABKHa+Wa1cSfUJnKNBtg 25Qz3VRNGhmVdHzZKebjc371VQR/pUKzfaoHpBQH8abQuBqekUzgjefODJ7L/9QSSut6HkPB8az +NnrlcOmONUSYqoiihA== X-Proofpoint-ORIG-GUID: FbcLa9o5DrsiY1g86YGaC5Q5ckGqAxA- X-Authority-Analysis: v=2.4 cv=aLr9aL9m c=1 sm=1 tr=0 ts=695c7040 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=M5GUcnROAAAA:8 a=0Cqobd3ug1408HmlttkA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: FbcLa9o5DrsiY1g86YGaC5Q5ckGqAxA- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-05_02,2026-01-05_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Switch HW should be able to fwd packets to any link based on flow rules. Set txlink enable for all channels. Signed-off-by: Ratheesh Kannoth --- .../net/ethernet/marvell/octeontx2/af/mbox.h | 4 ++ .../ethernet/marvell/octeontx2/af/rvu_nix.c | 50 ++++++++++++++++--- .../marvell/octeontx2/af/rvu_npc_fs.c | 2 +- .../marvell/octeontx2/nic/otx2_txrx.h | 2 + 4 files changed, 51 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net= /ethernet/marvell/octeontx2/af/mbox.h index bb38d06c925c..9404c935669d 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -1122,6 +1122,8 @@ struct nix_txsch_alloc_req { /* Scheduler queue count request at each level */ u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */ u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */ +#define NIX_TXSCH_ALLOC_FLAG_PAN BIT_ULL(0) + u64 flags; }; =20 struct nix_txsch_alloc_rsp { @@ -1140,6 +1142,7 @@ struct nix_txsch_alloc_rsp { struct nix_txsch_free_req { struct mbox_msghdr hdr; #define TXSCHQ_FREE_ALL BIT_ULL(0) +#define TXSCHQ_FREE_PAN_TL1 BIT_ULL(1) u16 flags; /* Scheduler queue level to be freed */ u16 schq_lvl; @@ -1958,6 +1961,7 @@ struct npc_install_flow_req { u16 entry; u16 channel; u16 chan_mask; + u8 set_chanmask; u8 intf; u8 set_cntr; /* If counter is available set counter for this entry ? */ u8 default_rule; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_nix.c index e2cc33ad2b2c..9d9d59affd68 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -1586,7 +1586,7 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu, if (err) goto free_mem; =20 - pfvf->sq_bmap =3D kcalloc(req->sq_cnt, sizeof(long), GFP_KERNEL); + pfvf->sq_bmap =3D kcalloc(req->sq_cnt, sizeof(long) * 16, GFP_KERNEL); if (!pfvf->sq_bmap) goto free_mem; =20 @@ -2106,11 +2106,14 @@ static int nix_check_txschq_alloc_req(struct rvu *r= vu, int lvl, u16 pcifunc, if (!req_schq) return 0; =20 - link =3D nix_get_tx_link(rvu, pcifunc); + if (req->flags & NIX_TXSCH_ALLOC_FLAG_PAN) + link =3D hw->cgx_links + hw->lbk_links + 1; + else + link =3D nix_get_tx_link(rvu, pcifunc); =20 /* For traffic aggregating scheduler level, one queue is enough */ if (lvl >=3D hw->cap.nix_tx_aggr_lvl) { - if (req_schq !=3D 1) + if (req_schq !=3D 1 && !(req->flags & NIX_TXSCH_ALLOC_FLAG_PAN)) return NIX_AF_ERR_TLX_ALLOC_FAIL; return 0; } @@ -2147,11 +2150,41 @@ static void nix_txsch_alloc(struct rvu *rvu, struct= nix_txsch *txsch, struct rvu_hwinfo *hw =3D rvu->hw; u16 pcifunc =3D rsp->hdr.pcifunc; int idx, schq; + bool alloc; =20 /* For traffic aggregating levels, queue alloc is based * on transmit link to which PF_FUNC is mapped to. */ if (lvl >=3D hw->cap.nix_tx_aggr_lvl) { + if (start !=3D end) { + idx =3D 0; + alloc =3D false; + for (schq =3D start; schq <=3D end; schq++, idx++) { + if (test_bit(schq, txsch->schq.bmap)) + continue; + + set_bit(schq, txsch->schq.bmap); + + /* A single TL queue is allocated each time */ + if (rsp->schq_contig[lvl]) { + alloc =3D true; + rsp->schq_contig_list[lvl][idx] =3D schq; + continue; + } + + if (rsp->schq[lvl]) { + alloc =3D true; + rsp->schq_list[lvl][idx] =3D schq; + continue; + } + } + + if (!alloc) + dev_err(rvu->dev, + "Could not allocate schq at lvl=3D%u start=3D%u end=3D%u\n", + lvl, start, end); + return; + } /* A single TL queue is allocated */ if (rsp->schq_contig[lvl]) { rsp->schq_contig[lvl] =3D 1; @@ -2268,11 +2301,14 @@ int rvu_mbox_handler_nix_txsch_alloc(struct rvu *rv= u, rsp->schq[lvl] =3D req->schq[lvl]; rsp->schq_contig[lvl] =3D req->schq_contig[lvl]; =20 - link =3D nix_get_tx_link(rvu, pcifunc); + if (req->flags & NIX_TXSCH_ALLOC_FLAG_PAN) + link =3D hw->cgx_links + hw->lbk_links + 1; + else + link =3D nix_get_tx_link(rvu, pcifunc); =20 if (lvl >=3D hw->cap.nix_tx_aggr_lvl) { start =3D link; - end =3D link; + end =3D link + !!(req->flags & NIX_TXSCH_ALLOC_FLAG_PAN); } else if (hw->cap.nix_fixed_txschq_mapping) { nix_get_txschq_range(rvu, pcifunc, link, &start, &end); } else { @@ -2637,7 +2673,9 @@ static int nix_txschq_free_one(struct rvu *rvu, schq =3D req->schq; txsch =3D &nix_hw->txsch[lvl]; =20 - if (lvl >=3D hw->cap.nix_tx_aggr_lvl || schq >=3D txsch->schq.max) + if ((lvl >=3D hw->cap.nix_tx_aggr_lvl && + !(req->flags & TXSCHQ_FREE_PAN_TL1)) || + schq >=3D txsch->schq.max) return 0; =20 pfvf_map =3D txsch->pfvf_map; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c b/drive= rs/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c index 3d6f780635a5..925b0b02279e 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c @@ -1469,7 +1469,7 @@ int rvu_mbox_handler_npc_install_flow(struct rvu *rvu, } =20 /* ignore chan_mask in case pf func is not AF, revisit later */ - if (!is_pffunc_af(req->hdr.pcifunc)) + if (!req->set_chanmask && !is_pffunc_af(req->hdr.pcifunc)) req->chan_mask =3D 0xFFF; =20 err =3D npc_check_unsupported_flows(rvu, req->features, req->intf); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h b/drive= rs/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h index acf259d72008..73a98b94426b 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h @@ -78,6 +78,8 @@ struct otx2_rcv_queue { struct sg_list { u16 num_segs; u16 flags; + u16 cq_idx; + u16 len; u64 skb; u64 size[OTX2_MAX_FRAGS_IN_SQE]; u64 dma_addr[OTX2_MAX_FRAGS_IN_SQE]; --=20 2.43.0 From nobody Sun Feb 8 12:14:17 2026 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40ACA240611; Tue, 6 Jan 2026 02:15:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767665741; cv=none; b=X0tMNSZg5L2Kwsso+NIM23tkBK2z2OrnE/LPKEbSHjTFSD0Jb6j0td6aZPIKj21/PPTtQqYJ7M79IDPdUG5YSTUFRvxFkKjFu5wF+WCjUFJAg6Bxlzm8LVlY3FJnayCHKWOnT85it8hOcTXViS+/JPL07b9s4/ki6t+kuAmOi68= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767665741; c=relaxed/simple; bh=meRJ889qyEoviOlRetICW0KmvUiu7ErJ59wh0g4D+gY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ddKAETmjrcKghvXYkqYBmXkhbn4ktewzn//0vxCj8ih3e/ko76do+1u8Y991qpPlDcfU9y3Nbsvm84NzmCls6bNWYJ4fxpcLbs/ICRWYtCda7bZfoEZoEMWZmoZvOkzkbErqYdDdqo3gAJzOrZ01abv2/o3ISiLYN/m42376px8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=WYnq+j/i; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="WYnq+j/i" Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6060m4FS129384; Mon, 5 Jan 2026 18:15:31 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=5 GOiJxKTrZ/tGJATZOPsF+MLqfg4MXi7siMEV0E2qeU=; b=WYnq+j/i3WQFxFi7t 1+XgUEYKIyAoTU+W4gO5kpI0O0UQlTyQhMsCwCaCRKzG+OxZ0v0uNbRh1ifBLOTL huXq3LvogYOmVCLr/MxEoIcY982Si6EE+ejo/tCEJjw9ODmYmw9xtUhseLCvj7Dy UYPhUv/iPhcu0ix/cJvg6rbUuZppEHYOuwGN2z3uyTbU/165dVBFsQUB3OF35bFc OOQbbbglX3rwlZaTFuU603oYYJpOQSqs9nO3bhA+FdQwtt09+lLq2TJ/yIa/A1/8 84Swldfp8x+H/zf+0//k4Fbx0sdDu0ND/GxXPf3deJ7CTU6TJSDXH48R2P3KASW1 QlvNQ== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 4bg9crhvx8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 05 Jan 2026 18:15:30 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Mon, 5 Jan 2026 18:15:44 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Mon, 5 Jan 2026 18:15:44 -0800 Received: from rkannoth-OptiPlex-7090.. (unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id 80E0C3F70C3; Mon, 5 Jan 2026 18:15:27 -0800 (PST) From: Ratheesh Kannoth To: , , CC: , , , , , Ratheesh Kannoth Subject: [PATCH net-next 06/10] octeontx2-pf: switch: Register for notifier chains. Date: Tue, 6 Jan 2026 07:44:43 +0530 Message-ID: <20260106021447.2359108-7-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260106021447.2359108-1-rkannoth@marvell.com> References: <20260106021447.2359108-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA2MDAxOCBTYWx0ZWRfX1VLzJ70/3kms o/SRae/aUc8WzSelr5GZJS3JfexAM3rpgPbugJAhLqBbFHxfoNRWKi1KzUGho6SQRXTlPKDn+CR Z6ac9UfcwxPCSMfdA4XWRzhGnzhGJkHcc7Vgdptad8qMLFs2O/bFjKZIA/zkDEJEJdRekS8YgLs /gYsrBXVQl6WGcuiYeebR3df2uZv5jniI+7X4aA8cM39/E35CpMQI1LVOI5XDMPRRBHjiKY/EXL emTMJL4Ha/2cMKRaPPwSacpcn96l+/+lPBd4JpsOHcPEEUSf1FA1l/dzfEM+vf3TqY+4I0Ud/6d GEarqRzXPxKTXN9bibSlKEgjJwgCFaweEnTVr1JKwgDylre0uO1V5qtYGg13RrxMPkNp+LVlN4W mWf1d87Sg4fZBWI4+qCDsltGlnV0Uu8WTZgWzNrJHj5y/PwX8B4rgkMJrPIJHegPywPhjoiNfkm JIPcMGm74t4fEwB5B7A== X-Proofpoint-ORIG-GUID: jHTAOVhGq1alC2DnyLNgzKGV3IOyVP00 X-Authority-Analysis: v=2.4 cv=aLr9aL9m c=1 sm=1 tr=0 ts=695c7042 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=M5GUcnROAAAA:8 a=MhupNYNnZBQ_oHQzngMA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: jHTAOVhGq1alC2DnyLNgzKGV3IOyVP00 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-05_02,2026-01-05_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Switchdev flow table needs information on 5tuple information to mangle/to find egress ports etc. PF driver registers for fdb/fib/netdev notifier chains to listen to events. These events are parsed and sent to switchdev HW through mbox events. Signed-off-by: Ratheesh Kannoth --- .../net/ethernet/marvell/octeontx2/nic/rep.c | 6 + .../marvell/octeontx2/nic/switch/sw_nb.c | 603 ++++++++++++++++++ .../marvell/octeontx2/nic/switch/sw_nb.h | 18 + 3 files changed, 627 insertions(+) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c b/drivers/net= /ethernet/marvell/octeontx2/nic/rep.c index 9200198be71f..fabbf045f473 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/rep.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/rep.c @@ -15,6 +15,7 @@ #include "cn10k.h" #include "otx2_reg.h" #include "rep.h" +#include "switch/sw_nb.h" =20 #define DRV_NAME "rvu_rep" #define DRV_STRING "Marvell RVU Representor Driver" @@ -414,6 +415,11 @@ static int rvu_eswitch_config(struct otx2_nic *priv, u= 8 ena) memcpy(req->switch_id, attrs.switch_id.id, attrs.switch_id.id_len); otx2_sync_mbox_msg(&priv->mbox); mutex_unlock(&priv->mbox.lock); + +#if IS_ENABLED(CONFIG_OCTEONTX_SWITCH) + ena ? sw_nb_register() : sw_nb_unregister(); +#endif + return 0; } =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c b/dr= ivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c index 2d14a0590c5d..f5886e8c9b03 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c @@ -4,14 +4,617 @@ * Copyright (C) 2026 Marvell. * */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../otx2_reg.h" +#include "../otx2_common.h" +#include "../otx2_struct.h" +#include "../cn10k.h" #include "sw_nb.h" +#include "sw_fdb.h" +#include "sw_fib.h" +#include "sw_fl.h" + +static const char *sw_nb_cmd2str[OTX2_CMD_MAX] =3D { + [OTX2_DEV_UP] =3D "OTX2_DEV_UP", + [OTX2_DEV_DOWN] =3D "OTX2_DEV_DOWN", + [OTX2_DEV_CHANGE] =3D "OTX2_DEV_CHANGE", + [OTX2_NEIGH_UPDATE] =3D "OTX2_NEIGH_UPDATE", + [OTX2_FIB_ENTRY_REPLACE] =3D "OTX2_FIB_ENTRY_REPLACE", + [OTX2_FIB_ENTRY_ADD] =3D "OTX2_FIB_ENTRY_ADD", + [OTX2_FIB_ENTRY_DEL] =3D "OTX2_FIB_ENTRY_DEL", + [OTX2_FIB_ENTRY_APPEND] =3D "OTX2_FIB_ENTRY_APPEND", +}; + +const char *sw_nb_get_cmd2str(int cmd) +{ + return sw_nb_cmd2str[cmd]; +} +EXPORT_SYMBOL(sw_nb_get_cmd2str); + +static bool sw_nb_is_cavium_dev(struct net_device *netdev) +{ + struct pci_dev *pdev; + struct device *dev; + + dev =3D netdev->dev.parent; + if (!dev) + return false; + + pdev =3D container_of(dev, struct pci_dev, dev); + if (pdev->vendor !=3D PCI_VENDOR_ID_CAVIUM) + return false; + + return true; +} + +static int sw_nb_check_slaves(struct net_device *dev, + struct netdev_nested_priv *priv) +{ + int *cnt; + + if (!priv->flags) + return 0; + + priv->flags &=3D sw_nb_is_cavium_dev(dev); + if (priv->flags) { + cnt =3D priv->data; + (*cnt)++; + } + + return 0; +} + +bool sw_nb_is_valid_dev(struct net_device *netdev) +{ + struct netdev_nested_priv priv; + struct net_device *br; + int cnt =3D 0; + + priv.flags =3D true; + priv.data =3D &cnt; + + if (netif_is_bridge_master(netdev) || is_vlan_dev(netdev)) { + netdev_walk_all_lower_dev(netdev, sw_nb_check_slaves, &priv); + return priv.flags && !!*(int *)priv.data; + } + + if (netif_is_bridge_port(netdev)) { + br =3D netdev_master_upper_dev_get_rcu(netdev); + if (!br) + return false; + + netdev_walk_all_lower_dev(br, sw_nb_check_slaves, &priv); + return priv.flags && !!*(int *)priv.data; + } + + return sw_nb_is_cavium_dev(netdev); +} + +static int sw_nb_fdb_event(struct notifier_block *unused, + unsigned long event, void *ptr) +{ + struct net_device *dev =3D switchdev_notifier_info_to_dev(ptr); + struct switchdev_notifier_fdb_info *fdb_info =3D ptr; + + if (!sw_nb_is_valid_dev(dev)) + return NOTIFY_DONE; + + switch (event) { + case SWITCHDEV_FDB_ADD_TO_DEVICE: + if (fdb_info->is_local) + break; + break; + + case SWITCHDEV_FDB_DEL_TO_DEVICE: + if (fdb_info->is_local) + break; + break; + + default: + return NOTIFY_DONE; + } + + return NOTIFY_DONE; +} + +static struct notifier_block sw_nb_fdb =3D { + .notifier_call =3D sw_nb_fdb_event, +}; + +static void __maybe_unused +sw_nb_fib_event_dump(unsigned long event, void *ptr) +{ + struct fib_entry_notifier_info *fen_info =3D ptr; + struct fib_nh *fib_nh; + struct fib_info *fi; + int i; + + pr_info("%s:%d FIB event=3D%lu dst=3D%#x dstlen=3D%u type=3D%u\n", + __func__, __LINE__, + event, fen_info->dst, fen_info->dst_len, + fen_info->type); + + fi =3D fen_info->fi; + if (!fi) + return; + + fib_nh =3D fi->fib_nh; + for (i =3D 0; i < fi->fib_nhs; i++, fib_nh++) + pr_info("%s:%d dev=3D%s saddr=3D%#x gw=3D%#x\n", + __func__, __LINE__, + fib_nh->fib_nh_dev->name, + fib_nh->nh_saddr, fib_nh->fib_nh_gw4); +} + +#define SWITCH_NB_FIB_EVENT_DUMP(...) \ + sw_nb_fib_event_dump(__VA_ARGS__) + +static int sw_nb_fib_event_to_otx2_event(int event) +{ + switch (event) { + case FIB_EVENT_ENTRY_REPLACE: + return OTX2_FIB_ENTRY_REPLACE; + case FIB_EVENT_ENTRY_ADD: + return OTX2_FIB_ENTRY_ADD; + case FIB_EVENT_ENTRY_DEL: + return OTX2_FIB_ENTRY_DEL; + default: + break; + } + + pr_err("Wrong FIB event %d\n", event); + return -1; +} + +static int sw_nb_fib_event(struct notifier_block *nb, + unsigned long event, void *ptr) +{ + struct fib_entry_notifier_info *fen_info =3D ptr; + struct fib_entry *entries, *iter; + struct net_device *dev, *pf_dev =3D NULL; + struct fib_notifier_info *info =3D ptr; + struct netdev_hw_addr *dev_addr; + struct net_device *lower; + struct list_head *lh; + struct neighbour *neigh; + struct fib_nh *fib_nh; + struct fib_info *fi; + struct otx2_nic *pf; + u32 *haddr; + int hcnt =3D 0; + int cnt, i; + + if (info->family !=3D AF_INET) + return NOTIFY_DONE; + + switch (event) { + case FIB_EVENT_ENTRY_REPLACE: + case FIB_EVENT_ENTRY_ADD: + case FIB_EVENT_ENTRY_DEL: + break; + default: + pr_debug("%s:%d Won't process FIB event %lu\n", + __func__, __LINE__, event); + return NOTIFY_DONE; + } + + /* Process only UNICAST routes add or del */ + if (fen_info->type !=3D RTN_UNICAST) + return NOTIFY_DONE; + + fi =3D fen_info->fi; + if (!fi) + return NOTIFY_DONE; + + if (fi->fib_nh_is_v6) { + pr_debug("%s:%d Received v6 notification\n", __func__, __LINE__); + return NOTIFY_DONE; + } + + entries =3D kcalloc(fi->fib_nhs, sizeof(*entries), GFP_ATOMIC); + if (!entries) + return NOTIFY_DONE; + + haddr =3D kcalloc(fi->fib_nhs, sizeof(u32), GFP_ATOMIC); + + iter =3D entries; + fib_nh =3D fi->fib_nh; + for (i =3D 0; i < fi->fib_nhs; i++, fib_nh++) { + dev =3D fib_nh->fib_nh_dev; + + if (!dev) + continue; + + if (dev->type !=3D ARPHRD_ETHER) + continue; + + if (!sw_nb_is_valid_dev(dev)) + continue; + + iter->cmd =3D sw_nb_fib_event_to_otx2_event(event); + iter->dst =3D fen_info->dst; + iter->dst_len =3D fen_info->dst_len; + iter->gw =3D htonl(fib_nh->fib_nh_gw4); + + pr_debug("%s:%d FIB route Rule cmd=3D%lld dst=3D%#x dst_len=3D%d gw=3D%#= x\n", + __func__, __LINE__, + iter->cmd, iter->dst, iter->dst_len, iter->gw); + + pf_dev =3D dev; + if (netif_is_bridge_master(dev)) { + iter->bridge =3D 1; + netdev_for_each_lower_dev(dev, lower, lh) { + pf_dev =3D lower; + break; + } + } else if (is_vlan_dev(dev)) { + iter->vlan_valid =3D 1; + pf_dev =3D vlan_dev_real_dev(dev); + iter->vlan_tag =3D vlan_dev_vlan_id(dev); + } + + pf =3D netdev_priv(pf_dev); + iter->port_id =3D pf->pcifunc; + + if (!fib_nh->fib_nh_gw4) { + if (iter->dst || iter->dst_len) + iter++; + + continue; + } + iter->gw_valid =3D 1; + + if (fib_nh->nh_saddr) + haddr[hcnt++] =3D fib_nh->nh_saddr; + + rcu_read_lock(); + neigh =3D ip_neigh_gw4(fib_nh->fib_nh_dev, fib_nh->fib_nh_gw4); + if (!neigh) { + rcu_read_unlock(); + iter++; + continue; + } + + if (is_valid_ether_addr(neigh->ha)) { + iter->mac_valid =3D 1; + ether_addr_copy(iter->mac, neigh->ha); + } + + iter++; + rcu_read_unlock(); + } + + cnt =3D iter - entries; + if (!cnt) + return NOTIFY_DONE; + + pr_debug("pf_dev is %s cnt=3D%d\n", pf_dev->name, cnt); + + if (!hcnt) + return NOTIFY_DONE; + + entries =3D kcalloc(hcnt, sizeof(*entries), GFP_ATOMIC); + if (!entries) + return NOTIFY_DONE; + + iter =3D entries; + + for (i =3D 0; i < hcnt; i++, iter++) { + iter->cmd =3D sw_nb_fib_event_to_otx2_event(event); + iter->dst =3D htonl(haddr[i]); + iter->dst_len =3D 32; + iter->mac_valid =3D 1; + iter->host =3D 1; + iter->port_id =3D pf->pcifunc; + + for_each_dev_addr(pf_dev, dev_addr) { + ether_addr_copy(iter->mac, dev_addr->addr); + break; + } + + pr_debug("%s:%d FIB host Rule cmd=3D%lld dst=3D%#x dst_len=3D%d gw=3D%#= x %s\n", + __func__, __LINE__, + iter->cmd, iter->dst, iter->dst_len, iter->gw, dev->name); + } + + kfree(haddr); + return NOTIFY_DONE; +} + +static struct notifier_block sw_nb_fib =3D { + .notifier_call =3D sw_nb_fib_event, +}; + +static int sw_nb_net_event(struct notifier_block *nb, + unsigned long event, void *ptr) +{ + struct net_device *lower, *pf_dev; + struct neighbour *n =3D ptr; + struct fib_entry *entry; + struct list_head *iter; + struct otx2_nic *pf; + + switch (event) { + case NETEVENT_NEIGH_UPDATE: + if (n->tbl->family !=3D AF_INET) + break; + + if (n->tbl !=3D &arp_tbl) + break; + + if (!sw_nb_is_valid_dev(n->dev)) + break; + + entry =3D kcalloc(1, sizeof(*entry), GFP_ATOMIC); + entry->cmd =3D OTX2_NEIGH_UPDATE; + entry->dst =3D htonl(*(u32 *)n->primary_key); + entry->dst_len =3D n->tbl->key_len * 8; + entry->mac_valid =3D 1; + entry->nud_state =3D n->nud_state; + ether_addr_copy(entry->mac, n->ha); + + pf_dev =3D n->dev; + if (netif_is_bridge_master(n->dev)) { + entry->bridge =3D 1; + netdev_for_each_lower_dev(n->dev, lower, iter) { + pf_dev =3D lower; + break; + } + } else if (is_vlan_dev(n->dev)) { + entry->vlan_valid =3D 1; + pf_dev =3D vlan_dev_real_dev(n->dev); + entry->vlan_tag =3D vlan_dev_vlan_id(n->dev); + } + + pf =3D netdev_priv(pf_dev); + entry->port_id =3D pf->pcifunc; + break; + } + + return NOTIFY_DONE; +} + +static struct notifier_block sw_nb_netevent =3D { + .notifier_call =3D sw_nb_net_event, + +}; + +static int sw_nb_inetaddr_event_to_otx2_event(int event) +{ + switch (event) { + case NETDEV_CHANGE: + return OTX2_DEV_CHANGE; + case NETDEV_UP: + return OTX2_DEV_UP; + case NETDEV_DOWN: + return OTX2_DEV_DOWN; + default: + break; + } + pr_debug("%s:%d Wrong interaddr event %d\n", __func__, __LINE__, event); + return -1; +} + +static int sw_nb_inetaddr_event(struct notifier_block *nb, + unsigned long event, void *ptr) +{ + struct in_ifaddr *ifa =3D (struct in_ifaddr *)ptr; + struct net_device *dev =3D ifa->ifa_dev->dev; + struct net_device *lower, *pf_dev; + struct netdev_hw_addr *dev_addr; + struct fib_entry *entry; + struct in_device *idev; + struct list_head *iter; + struct otx2_nic *pf; + + if (event !=3D NETDEV_CHANGE && + event !=3D NETDEV_UP && + event !=3D NETDEV_DOWN) { + return NOTIFY_DONE; + } + + if (!sw_nb_is_valid_dev(dev)) + return NOTIFY_DONE; + + idev =3D __in_dev_get_rtnl(dev); + if (!idev || !idev->ifa_list) + return NOTIFY_DONE; + + entry =3D kcalloc(1, sizeof(*entry), GFP_ATOMIC); + entry->cmd =3D sw_nb_inetaddr_event_to_otx2_event(event); + entry->dst =3D htonl(ifa->ifa_address); + entry->dst_len =3D 32; + entry->mac_valid =3D 1; + entry->host =3D 1; + + pf_dev =3D dev; + if (netif_is_bridge_master(dev)) { + entry->bridge =3D 1; + netdev_for_each_lower_dev(dev, lower, iter) { + pf_dev =3D lower; + break; + } + } else if (is_vlan_dev(dev)) { + entry->vlan_valid =3D 1; + pf_dev =3D vlan_dev_real_dev(dev); + entry->vlan_tag =3D vlan_dev_vlan_id(dev); + } + + pf =3D netdev_priv(pf_dev); + entry->port_id =3D pf->pcifunc; + + for_each_dev_addr(dev, dev_addr) { + ether_addr_copy(entry->mac, dev_addr->addr); + break; + } + + pr_debug("%s:%d pushing inetaddr event from HOST interface address %#x, %= pM, %s\n", + __func__, __LINE__, entry->dst, entry->mac, dev->name); + + return NOTIFY_DONE; +} + +struct notifier_block sw_nb_inetaddr =3D { + .notifier_call =3D sw_nb_inetaddr_event, +}; + +static int sw_nb_netdev_event(struct notifier_block *unused, + unsigned long event, void *ptr) +{ + struct net_device *dev =3D netdev_notifier_info_to_dev(ptr); + struct netdev_hw_addr *dev_addr; + struct net_device *pf_dev; + struct in_ifaddr *ifa; + struct fib_entry *entry; + struct in_device *idev; + struct otx2_nic *pf; + struct list_head *iter; + struct net_device *lower; + + if (event !=3D NETDEV_CHANGE && + event !=3D NETDEV_UP && + event !=3D NETDEV_DOWN) { + return NOTIFY_DONE; + } + + if (!sw_nb_is_valid_dev(dev)) + return NOTIFY_DONE; + + idev =3D __in_dev_get_rtnl(dev); + if (!idev || !idev->ifa_list) + return NOTIFY_DONE; + + ifa =3D rtnl_dereference(idev->ifa_list); + + entry =3D kcalloc(1, sizeof(*entry), GFP_KERNEL); + entry->cmd =3D sw_nb_inetaddr_event_to_otx2_event(event); + entry->dst =3D htonl(ifa->ifa_address); + entry->dst_len =3D 32; + entry->mac_valid =3D 1; + entry->host =3D 1; + + pf_dev =3D dev; + if (netif_is_bridge_master(dev)) { + entry->bridge =3D 1; + netdev_for_each_lower_dev(dev, lower, iter) { + pf_dev =3D lower; + break; + } + } else if (is_vlan_dev(dev)) { + entry->vlan_valid =3D 1; + pf_dev =3D vlan_dev_real_dev(dev); + entry->vlan_tag =3D vlan_dev_vlan_id(dev); + } + + pf =3D netdev_priv(pf_dev); + entry->port_id =3D pf->pcifunc; + + for_each_dev_addr(dev, dev_addr) { + ether_addr_copy(entry->mac, dev_addr->addr); + break; + } + + pr_debug("%s:%d pushing netdev event from HOST interface address %#x, %pM= , dev=3D%s\n", + __func__, __LINE__, entry->dst, entry->mac, dev->name); + + return NOTIFY_DONE; +} + +static struct notifier_block sw_nb_netdev =3D { + .notifier_call =3D sw_nb_netdev_event, +}; =20 int sw_nb_unregister(void) { + int err; + + sw_fl_deinit(); + sw_fib_deinit(); + sw_fdb_deinit(); + + err =3D unregister_switchdev_notifier(&sw_nb_fdb); + + if (err) + pr_err("Failed to unregister switchdev nb\n"); + + err =3D unregister_fib_notifier(&init_net, &sw_nb_fib); + if (err) + pr_err("Failed to unregister fib nb\n"); + + err =3D unregister_netevent_notifier(&sw_nb_netevent); + if (err) + pr_err("Failed to unregister netevent\n"); + + err =3D unregister_inetaddr_notifier(&sw_nb_inetaddr); + if (err) + pr_err("Failed to unregister addr event\n"); + + err =3D unregister_netdevice_notifier(&sw_nb_netdev); + if (err) + pr_err("Failed to unregister netdev notifier\n"); return 0; } +EXPORT_SYMBOL(sw_nb_unregister); =20 int sw_nb_register(void) { + int err; + + sw_fdb_init(); + sw_fib_init(); + sw_fl_init(); + + err =3D register_switchdev_notifier(&sw_nb_fdb); + if (err) { + pr_err("Failed to register switchdev nb\n"); + return err; + } + + err =3D register_fib_notifier(&init_net, &sw_nb_fib, NULL, NULL); + if (err) { + pr_err("Failed to register fb notifier block"); + goto err1; + } + + err =3D register_netevent_notifier(&sw_nb_netevent); + if (err) { + pr_err("Failed to register netevent\n"); + goto err2; + } + + err =3D register_inetaddr_notifier(&sw_nb_inetaddr); + if (err) { + pr_err("Failed to register addr event\n"); + goto err3; + } + + err =3D register_netdevice_notifier(&sw_nb_netdev); + if (err) { + pr_err("Failed to register netdevice nb\n"); + goto err4; + } + return 0; + +err4: + unregister_inetaddr_notifier(&sw_nb_inetaddr); + +err3: + unregister_netevent_notifier(&sw_nb_netevent); + +err2: + unregister_fib_notifier(&init_net, &sw_nb_fib); + +err1: + unregister_switchdev_notifier(&sw_nb_fdb); + return err; } +EXPORT_SYMBOL(sw_nb_register); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.h b/dr= ivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.h index 503a0e18cfd7..0a7a3b64f691 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.h @@ -7,7 +7,25 @@ #ifndef SW_NB_H_ #define SW_NB_H_ =20 +enum { + OTX2_DEV_UP =3D 1, + OTX2_DEV_DOWN, + OTX2_DEV_CHANGE, + OTX2_NEIGH_UPDATE, + OTX2_FIB_ENTRY_REPLACE, + OTX2_FIB_ENTRY_ADD, + OTX2_FIB_ENTRY_DEL, + OTX2_FIB_ENTRY_APPEND, + OTX2_CMD_MAX, +}; + int sw_nb_register(void); int sw_nb_unregister(void); +bool sw_nb_is_valid_dev(struct net_device *netdev); + +int otx2_mbox_up_handler_af2pf_fdb_refresh(struct otx2_nic *pf, + struct af2pf_fdb_refresh_req *req, + struct msg_rsp *rsp); =20 +const char *sw_nb_get_cmd2str(int cmd); #endif // SW_NB_H__ --=20 2.43.0 From nobody Sun Feb 8 12:14:17 2026 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3014A259C84; Tue, 6 Jan 2026 02:15:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767665744; cv=none; b=GdVmXPf6hHFT9xYsWV6dWs+94FwJ9GBliB0my/zVmmYpJK1caXJZKnLhDxMngGgX+xx4qqUkmtcMU/7xpQz6WA33dx5mkq6u4jenlhjYv2oF1kI0BYCfPf2lZo1U6BYx1WIt3F17AH+yL2eaKGjKkMNUtYwT8nfX3rrZaC54OIw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767665744; c=relaxed/simple; bh=MwRqg0HMzwZq9eQJG8OECKB5RyPpHYu6QHGPqobbVkk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jIzUM9oXIIkx+PZ/BZW4ls2h8RyXW0L0kdPyhRHAKeRm0e4WHT4qpKF+eKtrGCyZ01aoR4wZCSC1rhByhZuGMfU2ssc3qU1pLiX3+nzs/PCDM6sdvbKvmBrN8m6PekBHA8ZYGf565G32ouKI1BfMkCpfMSfpGG0s2SgJt6kCESg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=MjlNdAmC; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="MjlNdAmC" Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 605ESk0I2795732; Mon, 5 Jan 2026 18:15:34 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=E SJOKyp59N+psgB2zPx9qXPPEQLZXae8W7VsQOn+p8k=; b=MjlNdAmCAQjukQK7s WQ3Gwdk9NWVD0TeFOsta+reORfIy6hWZiQ23nKBmo1fexNHr8usDaFCIy8sOLfAk i5m1wgRyt+3UHqGgEy7J0VTv8zT0y8WkPO7C6euRQR74kaJkzRH5ijVHqln0DrEb 6ZDXJH4kGJE1sngK8sKlb+pyQ9Ko8U2vftirBjSMu0kRqzqmmi3Ow0H1D9vCLfuQ 2SdNn5kg3fvel9cj6Sx9+sfXh8AMJBo4PEu5BvlmBa2sK2RKzkE/opp/KcXbpqTh +wjS1fHlCCzLgceglFuhCDEyZz3G3EcMeiBROxWiVPoyS7UxfP3tBJ1v8ZwRZDEJ 4735Q== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 4bgf3fsa5m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 05 Jan 2026 18:15:34 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Mon, 5 Jan 2026 18:15:47 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Mon, 5 Jan 2026 18:15:47 -0800 Received: from rkannoth-OptiPlex-7090.. (unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id B22E43F70C5; Mon, 5 Jan 2026 18:15:30 -0800 (PST) From: Ratheesh Kannoth To: , , CC: , , , , , Ratheesh Kannoth Subject: [PATCH net-next 07/10] octeontx2: switch: L2 offload support Date: Tue, 6 Jan 2026 07:44:44 +0530 Message-ID: <20260106021447.2359108-8-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260106021447.2359108-1-rkannoth@marvell.com> References: <20260106021447.2359108-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=PLgCOPqC c=1 sm=1 tr=0 ts=695c7046 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=M5GUcnROAAAA:8 a=zjSZ3cS-AAAA:8 a=GBmGYfCpY8dhzgydGg8A:9 a=OBjm3rFKGHvpk9ecZwUJ:22 a=ZdzWmiyDu4ucoLeQK2uw:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA2MDAxOCBTYWx0ZWRfX+kyGM6FDysZg 4S+bXdNGMWqJW39bTe/f8Q6dPvIkR2Y+anzZMEuWbS8juPuD+ogFDF5HAmdGGC4uBrByifhYbih d4nshHvd/ZJkCuHjpHujT/1xQypCxed3wV2nMTgWH9cEVujE+2p3S8O6Tzl0t0F4WFrg1F7pUpe 0bjnxAcAERkOtjc1SewjFaLwfYTdyUk+sJAxnaYEkIUTKzRCzco7KZa2ES1ONShX2Fge3snPOB0 1crlYmxYB7NpCRf1TntGRjLSfDDy5O9PN3oY0O14C9uSXyNXZGzpK1J9mlvYy4GAFldGdoplJlt LyUT/uYG0vXH8O8BlQWjR4SJgG5mZZqesgHiStrZ1PM7P9w2XcaLf+RSBsTPY5S7q2SvtgedQVN 3ktgEcbhv2d8MSBMuKeR1/ZDUS4GBNo+MhcqhY39FLav4VDIBkNZGKnrKVegdZbccx0k3DlBXEu 1T7z0yUU03xoe4N+iDA== X-Proofpoint-GUID: 26xIVyMHuRhmjItct6vR9or96X2M4DkU X-Proofpoint-ORIG-GUID: 26xIVyMHuRhmjItct6vR9or96X2M4DkU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-05_02,2026-01-05_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Linux bridge fdb events are parsed to decide on DMAC to fwd packets. Switchdev HW flow table is filled with this information. Once populated, all packet with DMAC will be accelerated. Signed-off-by: Ratheesh Kannoth --- .../net/ethernet/marvell/octeontx2/af/rvu.c | 1 + .../marvell/octeontx2/af/switch/rvu_sw.c | 18 +- .../marvell/octeontx2/af/switch/rvu_sw_l2.c | 270 ++++++++++++++++++ .../marvell/octeontx2/af/switch/rvu_sw_l2.h | 2 + .../ethernet/marvell/octeontx2/nic/otx2_vf.c | 8 + .../marvell/octeontx2/nic/switch/sw_fdb.c | 127 ++++++++ .../marvell/octeontx2/nic/switch/sw_fdb.h | 5 + .../marvell/octeontx2/nic/switch/sw_nb.c | 15 +- 8 files changed, 438 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.c index 6b61742a61b1..95decbc5fc0d 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c @@ -2460,6 +2460,7 @@ static void __rvu_mbox_up_handler(struct rvu_work *mw= ork, int type) =20 switch (msg->id) { case MBOX_MSG_CGX_LINK_EVENT: + case MBOX_MSG_AF2PF_FDB_REFRESH: break; default: if (msg->rc) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c b/dr= ivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c index 533ee8725e38..b66f9c2eb981 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c @@ -7,6 +7,8 @@ =20 #include "rvu.h" #include "rvu_sw.h" +#include "rvu_sw_l2.h" +#include "rvu_sw_fl.h" =20 u32 rvu_sw_port_id(struct rvu *rvu, u16 pcifunc) { @@ -16,7 +18,7 @@ u32 rvu_sw_port_id(struct rvu *rvu, u16 pcifunc) rep_id =3D rvu_rep_get_vlan_id(rvu, pcifunc); =20 port_id =3D FIELD_PREP(GENMASK_ULL(31, 16), rep_id) | - FIELD_PREP(GENMASK_ULL(15, 0), pcifunc); + FIELD_PREP(GENMASK_ULL(15, 0), pcifunc); =20 return port_id; } @@ -25,5 +27,17 @@ int rvu_mbox_handler_swdev2af_notify(struct rvu *rvu, struct swdev2af_notify_req *req, struct msg_rsp *rsp) { - return 0; + int rc =3D 0; + + switch (req->msg_type) { + case SWDEV2AF_MSG_TYPE_FW_STATUS: + rc =3D rvu_sw_l2_init_offl_wq(rvu, req->pcifunc, req->fw_up); + break; + + case SWDEV2AF_MSG_TYPE_REFRESH_FDB: + rc =3D rvu_sw_l2_fdb_list_entry_add(rvu, req->pcifunc, req->mac); + break; + } + + return rc; } diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.c b= /drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.c index 5f805bfa81ed..88c4ef93812f 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.c @@ -4,11 +4,281 @@ * Copyright (C) 2026 Marvell. * */ + +#include #include "rvu.h" +#include "rvu_sw.h" +#include "rvu_sw_l2.h" + +#define M(_name, _id, _fn_name, _req_type, _rsp_type) \ +static struct _req_type __maybe_unused \ +*otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid) \ +{ \ + struct _req_type *req; \ + \ + req =3D (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ + &rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \ + sizeof(struct _rsp_type)); \ + if (!req) \ + return NULL; \ + req->hdr.sig =3D OTX2_MBOX_REQ_SIG; \ + req->hdr.id =3D _id; \ + return req; \ +} + +MBOX_UP_AF2SWDEV_MESSAGES +MBOX_UP_AF2PF_FDB_REFRESH_MESSAGES +#undef M + +struct l2_entry { + struct list_head list; + u64 flags; + u32 port_id; + u8 mac[ETH_ALEN]; +}; + +static DEFINE_MUTEX(l2_offl_list_lock); +static LIST_HEAD(l2_offl_lh); + +static DEFINE_MUTEX(fdb_refresh_list_lock); +static LIST_HEAD(fdb_refresh_lh); + +struct rvu_sw_l2_work { + struct rvu *rvu; + struct work_struct work; +}; + +static struct rvu_sw_l2_work l2_offl_work; +struct workqueue_struct *rvu_sw_l2_offl_wq; + +static struct rvu_sw_l2_work fdb_refresh_work; +struct workqueue_struct *fdb_refresh_wq; + +static void rvu_sw_l2_offl_cancel_add_if_del_reqs_exist(u8 *mac) +{ + struct l2_entry *entry, *tmp; + + mutex_lock(&l2_offl_list_lock); + list_for_each_entry_safe(entry, tmp, &l2_offl_lh, list) { + if (!ether_addr_equal(mac, entry->mac)) + continue; + + if (!(entry->flags & FDB_DEL)) + continue; + + list_del_init(&entry->list); + kfree(entry); + break; + } + mutex_unlock(&l2_offl_list_lock); +} + +static int rvu_sw_l2_offl_rule_push(struct rvu *rvu, struct l2_entry *l2_e= ntry) +{ + struct af2swdev_notify_req *req; + int swdev_pf; + + swdev_pf =3D rvu_get_pf(rvu->pdev, rvu->rswitch.pcifunc); + + mutex_lock(&rvu->mbox_lock); + req =3D otx2_mbox_alloc_msg_af2swdev_notify(rvu, swdev_pf); + if (!req) { + mutex_unlock(&rvu->mbox_lock); + return -ENOMEM; + } + + ether_addr_copy(req->mac, l2_entry->mac); + req->flags =3D l2_entry->flags; + req->port_id =3D l2_entry->port_id; + + otx2_mbox_wait_for_zero(&rvu->afpf_wq_info.mbox_up, swdev_pf); + otx2_mbox_msg_send_up(&rvu->afpf_wq_info.mbox_up, swdev_pf); + + mutex_unlock(&rvu->mbox_lock); + return 0; +} + +static int rvu_sw_l2_fdb_refresh(struct rvu *rvu, u16 pcifunc, u8 *mac) +{ + struct af2pf_fdb_refresh_req *req; + int pf, vidx; + + pf =3D rvu_get_pf(rvu->pdev, pcifunc); + + mutex_lock(&rvu->mbox_lock); + + if (pf) { + req =3D otx2_mbox_alloc_msg_af2pf_fdb_refresh(rvu, pf); + if (!req) { + mutex_unlock(&rvu->mbox_lock); + return -ENOMEM; + } + + req->hdr.pcifunc =3D pcifunc; + ether_addr_copy(req->mac, mac); + req->pcifunc =3D pcifunc; + + otx2_mbox_wait_for_zero(&rvu->afpf_wq_info.mbox_up, pf); + otx2_mbox_msg_send_up(&rvu->afpf_wq_info.mbox_up, pf); + } else { + vidx =3D pcifunc - 1; + + req =3D (struct af2pf_fdb_refresh_req *) + otx2_mbox_alloc_msg_rsp(&rvu->afvf_wq_info.mbox_up, vidx, + sizeof(*req), sizeof(struct msg_rsp)); + if (!req) { + mutex_unlock(&rvu->mbox_lock); + return -ENOMEM; + } + req->hdr.sig =3D OTX2_MBOX_REQ_SIG; + req->hdr.id =3D MBOX_MSG_AF2PF_FDB_REFRESH; + + req->hdr.pcifunc =3D pcifunc; + ether_addr_copy(req->mac, mac); + req->pcifunc =3D pcifunc; + + otx2_mbox_wait_for_zero(&rvu->afvf_wq_info.mbox_up, vidx); + otx2_mbox_msg_send_up(&rvu->afvf_wq_info.mbox_up, vidx); + } + + mutex_unlock(&rvu->mbox_lock); + + return 0; +} + +static void rvu_sw_l2_fdb_refresh_wq_handler(struct work_struct *work) +{ + struct rvu_sw_l2_work *fdb_work; + struct l2_entry *l2_entry; + + fdb_work =3D container_of(work, struct rvu_sw_l2_work, work); + + while (1) { + mutex_lock(&fdb_refresh_list_lock); + l2_entry =3D list_first_entry_or_null(&fdb_refresh_lh, + struct l2_entry, list); + if (!l2_entry) { + mutex_unlock(&fdb_refresh_list_lock); + return; + } + + list_del_init(&l2_entry->list); + mutex_unlock(&fdb_refresh_list_lock); + + rvu_sw_l2_fdb_refresh(fdb_work->rvu, l2_entry->port_id, l2_entry->mac); + kfree(l2_entry); + } +} + +static void rvu_sw_l2_offl_rule_wq_handler(struct work_struct *work) +{ + struct rvu_sw_l2_work *offl_work; + struct l2_entry *l2_entry; + int budget =3D 16; + bool add_fdb; + + offl_work =3D container_of(work, struct rvu_sw_l2_work, work); + + while (budget--) { + mutex_lock(&l2_offl_list_lock); + l2_entry =3D list_first_entry_or_null(&l2_offl_lh, struct l2_entry, list= ); + if (!l2_entry) { + mutex_unlock(&l2_offl_list_lock); + return; + } + + list_del_init(&l2_entry->list); + mutex_unlock(&l2_offl_list_lock); + + add_fdb =3D !!(l2_entry->flags & FDB_ADD); + + if (add_fdb) + rvu_sw_l2_offl_cancel_add_if_del_reqs_exist(l2_entry->mac); + + rvu_sw_l2_offl_rule_push(offl_work->rvu, l2_entry); + kfree(l2_entry); + } + + if (!list_empty(&l2_offl_lh)) + queue_work(rvu_sw_l2_offl_wq, &l2_offl_work.work); +} + +int rvu_sw_l2_init_offl_wq(struct rvu *rvu, u16 pcifunc, bool fw_up) +{ + struct rvu_switch *rswitch; + + rswitch =3D &rvu->rswitch; + + if (fw_up) { + rswitch->flags |=3D RVU_SWITCH_FLAG_FW_READY; + rswitch->pcifunc =3D pcifunc; + + l2_offl_work.rvu =3D rvu; + INIT_WORK(&l2_offl_work.work, rvu_sw_l2_offl_rule_wq_handler); + rvu_sw_l2_offl_wq =3D alloc_workqueue("swdev_rvu_sw_l2_offl_wq", 0, 0); + if (!rvu_sw_l2_offl_wq) { + dev_err(rvu->dev, "L2 offl workqueue allocation failed\n"); + return -ENOMEM; + } + + fdb_refresh_work.rvu =3D rvu; + INIT_WORK(&fdb_refresh_work.work, rvu_sw_l2_fdb_refresh_wq_handler); + fdb_refresh_wq =3D alloc_workqueue("swdev_fdb_refresg_wq", 0, 0); + if (!rvu_sw_l2_offl_wq) { + dev_err(rvu->dev, "L2 offl workqueue allocation failed\n"); + return -ENOMEM; + } + + return 0; + } + + rswitch->flags &=3D ~RVU_SWITCH_FLAG_FW_READY; + rswitch->pcifunc =3D -1; + flush_work(&l2_offl_work.work); + return 0; +} + +int rvu_sw_l2_fdb_list_entry_add(struct rvu *rvu, u16 pcifunc, u8 *mac) +{ + struct l2_entry *l2_entry; + + l2_entry =3D kcalloc(1, sizeof(*l2_entry), GFP_KERNEL); + if (!l2_entry) + return -ENOMEM; + + l2_entry->port_id =3D pcifunc; + ether_addr_copy(l2_entry->mac, mac); + + mutex_lock(&fdb_refresh_list_lock); + list_add_tail(&l2_entry->list, &fdb_refresh_lh); + mutex_unlock(&fdb_refresh_list_lock); + + queue_work(fdb_refresh_wq, &fdb_refresh_work.work); + return 0; +} =20 int rvu_mbox_handler_fdb_notify(struct rvu *rvu, struct fdb_notify_req *req, struct msg_rsp *rsp) { + struct l2_entry *l2_entry; + + if (!(rvu->rswitch.flags & RVU_SWITCH_FLAG_FW_READY)) + return 0; + + l2_entry =3D kcalloc(1, sizeof(*l2_entry), GFP_KERNEL); + if (!l2_entry) + return -ENOMEM; + + ether_addr_copy(l2_entry->mac, req->mac); + l2_entry->flags =3D req->flags; + l2_entry->port_id =3D rvu_sw_port_id(rvu, req->hdr.pcifunc); + + mutex_lock(&l2_offl_list_lock); + list_add_tail(&l2_entry->list, &l2_offl_lh); + mutex_unlock(&l2_offl_list_lock); + + queue_work(rvu_sw_l2_offl_wq, &l2_offl_work.work); + return 0; } diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.h b= /drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.h index ff28612150c9..56786768880e 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l2.h @@ -8,4 +8,6 @@ #ifndef RVU_SW_L2_H #define RVU_SW_L2_H =20 +int rvu_sw_l2_init_offl_wq(struct rvu *rvu, u16 pcifunc, bool fw_up); +int rvu_sw_l2_fdb_list_entry_add(struct rvu *rvu, u16 pcifunc, u8 *mac); #endif diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_vf.c index f4fdbfba8667..dac065456a8e 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c @@ -15,6 +15,7 @@ #include "otx2_ptp.h" #include "cn10k.h" #include "cn10k_ipsec.h" +#include "switch/sw_nb.h" =20 #define DRV_NAME "rvu_nicvf" #define DRV_STRING "Marvell RVU NIC Virtual Function Driver" @@ -141,6 +142,13 @@ static int otx2vf_process_mbox_msg_up(struct otx2_nic = *vf, err =3D otx2_mbox_up_handler_cgx_link_event( vf, (struct cgx_link_info_msg *)req, rsp); return err; + + case MBOX_MSG_AF2PF_FDB_REFRESH: + err =3D otx2_mbox_up_handler_af2pf_fdb_refresh(vf, + (struct af2pf_fdb_refresh_req *)req, + rsp); + return err; + default: otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id); return -ENODEV; diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.c b/d= rivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.c index 6842c8d91ffc..71aec9628eb2 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.c @@ -4,13 +4,140 @@ * Copyright (C) 2026 Marvell. * */ +#include +#include +#include +#include +#include +#include + +#include "../otx2_reg.h" +#include "../otx2_common.h" +#include "../otx2_struct.h" +#include "../cn10k.h" #include "sw_fdb.h" =20 +#if !IS_ENABLED(CONFIG_OCTEONTX_SWITCH) + +int otx2_mbox_up_handler_af2pf_fdb_refresh(struct otx2_nic *pf, + struct af2pf_fdb_refresh_req *req, + struct msg_rsp *rsp) +{ + return 0; +} + +#else + +static DEFINE_SPINLOCK(sw_fdb_llock); +static LIST_HEAD(sw_fdb_lh); + +struct sw_fdb_list_entry { + struct list_head list; + u64 flags; + struct otx2_nic *pf; + u8 mac[ETH_ALEN]; + bool add_fdb; +}; + +static struct workqueue_struct *sw_fdb_wq; +static struct work_struct sw_fdb_work; + +static int sw_fdb_add_or_del(struct otx2_nic *pf, + const unsigned char *addr, + bool add_fdb) +{ + struct fdb_notify_req *req; + int rc; + + mutex_lock(&pf->mbox.lock); + req =3D otx2_mbox_alloc_msg_fdb_notify(&pf->mbox); + if (!req) { + rc =3D -ENOMEM; + goto out; + } + + ether_addr_copy(req->mac, addr); + req->flags =3D add_fdb ? FDB_ADD : FDB_DEL; + + rc =3D otx2_sync_mbox_msg(&pf->mbox); +out: + mutex_unlock(&pf->mbox.lock); + return rc; +} + +static void sw_fdb_wq_handler(struct work_struct *work) +{ + struct sw_fdb_list_entry *entry; + LIST_HEAD(tlist); + + spin_lock(&sw_fdb_llock); + list_splice_init(&sw_fdb_lh, &tlist); + spin_unlock(&sw_fdb_llock); + + while ((entry =3D + list_first_entry_or_null(&tlist, + struct sw_fdb_list_entry, + list)) !=3D NULL) { + list_del_init(&entry->list); + sw_fdb_add_or_del(entry->pf, entry->mac, entry->add_fdb); + kfree(entry); + } + + spin_lock(&sw_fdb_llock); + if (!list_empty(&sw_fdb_lh)) + queue_work(sw_fdb_wq, &sw_fdb_work); + spin_unlock(&sw_fdb_llock); +} + +int sw_fdb_add_to_list(struct net_device *dev, u8 *mac, bool add_fdb) +{ + struct otx2_nic *pf =3D netdev_priv(dev); + struct sw_fdb_list_entry *entry; + + entry =3D kcalloc(1, sizeof(*entry), GFP_ATOMIC); + if (!entry) + return -ENOMEM; + + ether_addr_copy(entry->mac, mac); + entry->add_fdb =3D add_fdb; + entry->pf =3D pf; + + spin_lock(&sw_fdb_llock); + list_add_tail(&entry->list, &sw_fdb_lh); + queue_work(sw_fdb_wq, &sw_fdb_work); + spin_unlock(&sw_fdb_llock); + + return 0; +} + int sw_fdb_init(void) { + INIT_WORK(&sw_fdb_work, sw_fdb_wq_handler); + sw_fdb_wq =3D alloc_workqueue("sw_fdb_wq", 0, 0); + if (!sw_fdb_wq) + return -ENOMEM; + return 0; } =20 void sw_fdb_deinit(void) { + cancel_work_sync(&sw_fdb_work); + destroy_workqueue(sw_fdb_wq); +} + +int otx2_mbox_up_handler_af2pf_fdb_refresh(struct otx2_nic *pf, + struct af2pf_fdb_refresh_req *req, + struct msg_rsp *rsp) +{ + struct switchdev_notifier_fdb_info item =3D {0}; + + item.addr =3D req->mac; + item.info.dev =3D pf->netdev; + call_switchdev_notifiers(SWITCHDEV_FDB_ADD_TO_BRIDGE, + item.info.dev, &item.info, NULL); + + return 0; } +#endif +EXPORT_SYMBOL(otx2_mbox_up_handler_af2pf_fdb_refresh); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.h b/d= rivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.h index d4314d6d3ee4..f8705083418c 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fdb.h @@ -7,7 +7,12 @@ #ifndef SW_FDB_H_ #define SW_FDB_H_ =20 +int sw_fdb_add_to_list(struct net_device *dev, u8 *mac, bool add_fdb); void sw_fdb_deinit(void); int sw_fdb_init(void); =20 +int otx2_mbox_up_handler_af2pf_fdb_refresh(struct otx2_nic *pf, + struct af2pf_fdb_refresh_req *req, + struct msg_rsp *rsp); + #endif // SW_FDB_H diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c b/dr= ivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c index f5886e8c9b03..b295940ab8c7 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c @@ -21,6 +21,7 @@ #include "sw_fdb.h" #include "sw_fib.h" #include "sw_fl.h" +#include "sw_nb.h" =20 static const char *sw_nb_cmd2str[OTX2_CMD_MAX] =3D { [OTX2_DEV_UP] =3D "OTX2_DEV_UP", @@ -59,7 +60,6 @@ static int sw_nb_check_slaves(struct net_device *dev, struct netdev_nested_priv *priv) { int *cnt; - if (!priv->flags) return 0; =20 @@ -103,6 +103,7 @@ static int sw_nb_fdb_event(struct notifier_block *unuse= d, { struct net_device *dev =3D switchdev_notifier_info_to_dev(ptr); struct switchdev_notifier_fdb_info *fdb_info =3D ptr; + int rc; =20 if (!sw_nb_is_valid_dev(dev)) return NOTIFY_DONE; @@ -111,11 +112,13 @@ static int sw_nb_fdb_event(struct notifier_block *unu= sed, case SWITCHDEV_FDB_ADD_TO_DEVICE: if (fdb_info->is_local) break; + rc =3D sw_fdb_add_to_list(dev, (u8 *)fdb_info->addr, true); break; =20 case SWITCHDEV_FDB_DEL_TO_DEVICE: if (fdb_info->is_local) break; + rc =3D sw_fdb_add_to_list(dev, (u8 *)fdb_info->addr, false); break; =20 default: @@ -304,7 +307,6 @@ static int sw_nb_fib_event(struct notifier_block *nb, entries =3D kcalloc(hcnt, sizeof(*entries), GFP_ATOMIC); if (!entries) return NOTIFY_DONE; - iter =3D entries; =20 for (i =3D 0; i < hcnt; i++, iter++) { @@ -536,10 +538,6 @@ int sw_nb_unregister(void) { int err; =20 - sw_fl_deinit(); - sw_fib_deinit(); - sw_fdb_deinit(); - err =3D unregister_switchdev_notifier(&sw_nb_fdb); =20 if (err) @@ -560,6 +558,11 @@ int sw_nb_unregister(void) err =3D unregister_netdevice_notifier(&sw_nb_netdev); if (err) pr_err("Failed to unregister netdev notifier\n"); + + sw_fl_deinit(); + sw_fib_deinit(); + sw_fdb_deinit(); + return 0; } EXPORT_SYMBOL(sw_nb_unregister); --=20 2.43.0 From nobody Sun Feb 8 12:14:17 2026 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1383323E23C; Tue, 6 Jan 2026 02:15:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767665747; cv=none; b=oZw/xcYg0KugyjO90ZUP+Llgd+zXe3PUO2TUNYkqiz8mt2P/lo3tTVpgHou2gOChHcikwLUCUxzJ8KeXMKge6RdNj5vJABNuuxRFc3C6u0+WuSg87Ox5aMCInP7J6sl2mWo91kXoUMNlhYlOsnG4aJd6t9xSvTTOZoSGEGgZZxs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767665747; c=relaxed/simple; bh=/O8eRm/ccvirbwSqQuLLQMC+v0tbiPmJHEwIzRIZ+jA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cqXCS2+J60fesulI62xyc8VJ0Ml2l2D6uVg0ZEKjyhhdeT04Xv8LT6aX3NXO0FNQwULtXeBycRJV89YLd7oIJxF9zHtoU8atHbwhBSNWUhWyzLz+nJLtHk/7F5jlcJAhg/KYTer/GLmiqH/7yfExFDa3sCCQQjkepcgVMhj2K1c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=f4XF2thW; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="f4XF2thW" Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6061ip7T128579; Mon, 5 Jan 2026 18:15:37 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=P UeK9vcJZbg4vvIfH/vVdGpTRn3GzLM/VVmZiYdNZWM=; b=f4XF2thWSchkNkJ9Y /QOADIV6loQ5MnZ9Jy4K9cID7y7IplPsxn9/Y/TeMzcdQ2kld6w40fdrGwFVpxjy Nd0h+jGTwLKckNLIHkQr5SILycG1m6raNGuPkY2KiLNWmMBjEXa0WA9CIXKmIqHo CrybJRJ8yt2pBglrF0KlQ18r+iI6OQylNtlLic67vud9cG6XI8Nch+wbgjXmVSni c49yYhttB1Pf9BvQS02Rb0dOcwx6P3gNSXmpJJzb04OMZW6HaCdTi6BUSQLUPTq+ q20oA1b0VSQI0Fx6zvh6JoBQfKeXmX9qtm/dscj7SZwF7MYrcmoazZyzu5lm5Dma /5Z3A== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 4bg9crhvxc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 05 Jan 2026 18:15:36 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Mon, 5 Jan 2026 18:15:51 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Mon, 5 Jan 2026 18:15:50 -0800 Received: from rkannoth-OptiPlex-7090.. (unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id D68743F70C6; Mon, 5 Jan 2026 18:15:33 -0800 (PST) From: Ratheesh Kannoth To: , , CC: , , , , , Ratheesh Kannoth Subject: [PATCH net-next 08/10] octeontx2: switch: L3 offload support Date: Tue, 6 Jan 2026 07:44:45 +0530 Message-ID: <20260106021447.2359108-9-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260106021447.2359108-1-rkannoth@marvell.com> References: <20260106021447.2359108-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA2MDAxOCBTYWx0ZWRfXx87Sak1USqOi qjN0wtpJ4BlF/vrGAIrrXSHDbTs0QMcNdrq4yXjYgl39mVCodo2Gy7v/IQZSva2NsqiPPP10hMA oCItFDv6lSmELunGbAQ8BDKjmfyldCBhBPW9AOAjuPmb1C14kiGWoVcoRl/OJhO+BPVRvwHsgS+ OF7JGRhOn77zi2zNgGQe8inT3sDVQZVY45SIhlRC1ZIfwV5iERv7MpipFLDyMmRnXiCKEAk4Db5 cHvg5vDOH6xE9VuzADQGZJDuvFv0JeK1U7tzd0XgahZOifIvtKh5lbRPg7S9KuhgmHdfjWVdimh KVPAw0L9HmAspu3rKGIXVE+5vYQ31Otq0M9r3amBUOiwzXa0y2WEY2DRCIwOpxJC1T69fumW2U1 qt9NfeUtFKymZvQdcEVTCQB7nwrgLWhmn7m+4Ndy2Gc53oTewQOa8hLvDJdOEdMP3oS1LqKNr2+ DmLiZVEtdYUNbIEeDKA== X-Proofpoint-ORIG-GUID: 5xEe9nGzIkmpVTHorXo9W3NoQ3rDQfEA X-Authority-Analysis: v=2.4 cv=aLr9aL9m c=1 sm=1 tr=0 ts=695c7049 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=M5GUcnROAAAA:8 a=tTGoQvCruEYILLHsEjQA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: 5xEe9nGzIkmpVTHorXo9W3NoQ3rDQfEA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-05_02,2026-01-05_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Linux route events are parsed to decide on destination DIP/MASK to fwd packets. Switchdev HW flow table is filled with this information. Once populated, all packet with DIP/MASK will be accelerated. Signed-off-by: Ratheesh Kannoth --- .../marvell/octeontx2/af/switch/rvu_sw.c | 2 +- .../marvell/octeontx2/af/switch/rvu_sw_l3.c | 201 ++++++++++++++++++ .../marvell/octeontx2/nic/switch/sw_fib.c | 117 ++++++++++ .../marvell/octeontx2/nic/switch/sw_fib.h | 3 + .../marvell/octeontx2/nic/switch/sw_nb.c | 7 + 5 files changed, 329 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c b/dr= ivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c index b66f9c2eb981..fe91b0a6baf5 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c @@ -6,9 +6,9 @@ */ =20 #include "rvu.h" -#include "rvu_sw.h" #include "rvu_sw_l2.h" #include "rvu_sw_fl.h" +#include "rvu_sw.h" =20 u32 rvu_sw_port_id(struct rvu *rvu, u16 pcifunc) { diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.c b= /drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.c index 2b798d5f0644..0daad60ca949 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_l3.c @@ -4,11 +4,212 @@ * Copyright (C) 2026 Marvell. * */ + +#include #include "rvu.h" +#include "rvu_sw.h" +#include "rvu_sw_l3.h" + +#define M(_name, _id, _fn_name, _req_type, _rsp_type) \ +static struct _req_type __maybe_unused \ +*otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid) \ +{ \ + struct _req_type *req; \ + \ + req =3D (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ + &rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \ + sizeof(struct _rsp_type)); \ + if (!req) \ + return NULL; \ + req->hdr.sig =3D OTX2_MBOX_REQ_SIG; \ + req->hdr.id =3D _id; \ + return req; \ +} + +MBOX_UP_AF2SWDEV_MESSAGES +#undef M + +static struct workqueue_struct *sw_l3_offl_wq; + +struct l3_entry { + struct list_head list; + struct rvu *rvu; + u32 port_id; + int cnt; + struct fib_entry entry[]; +}; + +static DEFINE_MUTEX(l3_offl_llock); +static LIST_HEAD(l3_offl_lh); +static bool l3_offl_work_running; + +static struct workqueue_struct *sw_l3_offl_wq; +static void sw_l3_offl_work_handler(struct work_struct *work); +static DECLARE_DELAYED_WORK(l3_offl_work, sw_l3_offl_work_handler); + +static void sw_l3_offl_dump(struct l3_entry *l3_entry) +{ + struct fib_entry *entry =3D l3_entry->entry; + int i; + + for (i =3D 0; i < l3_entry->cnt; i++) { + pr_debug("%s:%d cmd=3D%llu port_id=3D%#x dst=3D%#x dst_len=3D%d gw=3D%#= x\n", + __func__, __LINE__, entry->cmd, entry->port_id, entry->dst, + entry->dst_len, entry->gw); + } +} + +static int rvu_sw_l3_offl_rule_push(struct list_head *lh) +{ + struct af2swdev_notify_req *req; + struct fib_entry *entry, *dst; + struct l3_entry *l3_entry; + struct rvu *rvu; + int swdev_pf; + int sz, cnt; + int tot_cnt =3D 0; + + l3_entry =3D list_first_entry_or_null(lh, struct l3_entry, list); + if (!l3_entry) + return 0; + + rvu =3D l3_entry->rvu; + swdev_pf =3D rvu_get_pf(rvu->pdev, rvu->rswitch.pcifunc); + + mutex_lock(&rvu->mbox_lock); + req =3D otx2_mbox_alloc_msg_af2swdev_notify(rvu, swdev_pf); + if (!req) { + mutex_unlock(&rvu->mbox_lock); + return -ENOMEM; + } + + dst =3D &req->entry[0]; + while ((l3_entry =3D + list_first_entry_or_null(lh, + struct l3_entry, list)) !=3D NULL) { + entry =3D l3_entry->entry; + cnt =3D l3_entry->cnt; + sz =3D sizeof(*entry) * cnt; + + memcpy(dst, entry, sz); + tot_cnt +=3D cnt; + dst +=3D cnt; + + sw_l3_offl_dump(l3_entry); + + list_del_init(&l3_entry->list); + kfree(l3_entry); + } + req->flags =3D FIB_CMD; + req->cnt =3D tot_cnt; + + otx2_mbox_wait_for_zero(&rvu->afpf_wq_info.mbox_up, swdev_pf); + otx2_mbox_msg_send_up(&rvu->afpf_wq_info.mbox_up, swdev_pf); + + mutex_unlock(&rvu->mbox_lock); + return 0; +} + +static atomic64_t req_cnt; +static atomic64_t ack_cnt; +static atomic64_t req_processed; +static LIST_HEAD(l3_local_lh); +static int lcnt; + +static void sw_l3_offl_work_handler(struct work_struct *work) +{ + struct l3_entry *l3_entry; + struct list_head l3lh; + u64 req, ack, proc; + + INIT_LIST_HEAD(&l3lh); + + mutex_lock(&l3_offl_llock); + while (1) { + l3_entry =3D list_first_entry_or_null(&l3_offl_lh, struct l3_entry, list= ); + + if (!l3_entry) + break; + + if (lcnt + l3_entry->cnt > 16) { + req =3D atomic64_read(&req_cnt); + atomic64_set(&ack_cnt, req); + atomic64_set(&req_processed, req); + mutex_unlock(&l3_offl_llock); + goto process; + } + + lcnt +=3D l3_entry->cnt; + + atomic64_inc(&req_cnt); + list_del_init(&l3_entry->list); + list_add_tail(&l3_entry->list, &l3_local_lh); + } + mutex_unlock(&l3_offl_llock); + + req =3D atomic64_read(&req_cnt); + ack =3D atomic64_read(&ack_cnt); + + if (req > ack) { + atomic64_set(&ack_cnt, req); + queue_delayed_work(sw_l3_offl_wq, &l3_offl_work, + msecs_to_jiffies(100)); + return; + } + + proc =3D atomic64_read(&req_processed); + if (req =3D=3D proc) { + queue_delayed_work(sw_l3_offl_wq, &l3_offl_work, + msecs_to_jiffies(1000)); + return; + } + + atomic64_set(&req_processed, req); + +process: + lcnt =3D 0; + + mutex_lock(&l3_offl_llock); + list_splice_init(&l3_local_lh, &l3lh); + mutex_unlock(&l3_offl_llock); + + rvu_sw_l3_offl_rule_push(&l3lh); + + queue_delayed_work(sw_l3_offl_wq, &l3_offl_work, msecs_to_jiffies(100)); +} =20 int rvu_mbox_handler_fib_notify(struct rvu *rvu, struct fib_notify_req *req, struct msg_rsp *rsp) { + struct l3_entry *l3_entry; + int sz; + + if (!(rvu->rswitch.flags & RVU_SWITCH_FLAG_FW_READY)) + return 0; + + sz =3D req->cnt * sizeof(struct fib_entry); + + l3_entry =3D kcalloc(1, sizeof(*l3_entry) + sz, GFP_KERNEL); + if (!l3_entry) + return -ENOMEM; + + l3_entry->port_id =3D rvu_sw_port_id(rvu, req->hdr.pcifunc); + l3_entry->rvu =3D rvu; + l3_entry->cnt =3D req->cnt; + INIT_LIST_HEAD(&l3_entry->list); + memcpy(l3_entry->entry, req->entry, sz); + + mutex_lock(&l3_offl_llock); + list_add_tail(&l3_entry->list, &l3_offl_lh); + mutex_unlock(&l3_offl_llock); + + if (!l3_offl_work_running) { + sw_l3_offl_wq =3D alloc_workqueue("sw_af_fib_wq", 0, 0); + l3_offl_work_running =3D true; + queue_delayed_work(sw_l3_offl_wq, &l3_offl_work, + msecs_to_jiffies(1000)); + } + return 0; } diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.c b/d= rivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.c index 12ddf8119372..662b0daf31d5 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.c @@ -4,13 +4,130 @@ * Copyright (C) 2026 Marvell. * */ +#include +#include +#include +#include +#include +#include +#include + +#include "../otx2_reg.h" +#include "../otx2_common.h" +#include "../otx2_struct.h" +#include "../cn10k.h" +#include "sw_nb.h" #include "sw_fib.h" =20 +static DEFINE_SPINLOCK(sw_fib_llock); +static LIST_HEAD(sw_fib_lh); + +static struct workqueue_struct *sw_fib_wq; +static void sw_fib_work_handler(struct work_struct *work); +static DECLARE_DELAYED_WORK(sw_fib_work, sw_fib_work_handler); + +struct sw_fib_list_entry { + struct list_head lh; + struct otx2_nic *pf; + int cnt; + struct fib_entry *entry; +}; + +static void sw_fib_dump(struct fib_entry *entry, int cnt) +{ + int i; + + for (i =3D 0; i < cnt; i++, entry++) { + pr_debug("%s:%d cmd=3D%s gw_valid=3D%d mac_valid=3D%d dst=3D%#x len=3D%d= gw=3D%#x mac=3D%pM nud_state=3D%#x\n", + __func__, __LINE__, + sw_nb_get_cmd2str(entry->cmd), + entry->gw_valid, entry->mac_valid, entry->dst, entry->dst_len, + entry->gw, entry->mac, entry->nud_state); + } +} + +static int sw_fib_notify(struct otx2_nic *pf, + int cnt, + struct fib_entry *entry) +{ + struct fib_notify_req *req; + int rc; + + mutex_lock(&pf->mbox.lock); + req =3D otx2_mbox_alloc_msg_fib_notify(&pf->mbox); + if (!req) { + rc =3D -ENOMEM; + goto out; + } + + req->cnt =3D cnt; + memcpy(req->entry, entry, sizeof(*entry) * cnt); + sw_fib_dump(req->entry, cnt); + + rc =3D otx2_sync_mbox_msg(&pf->mbox); +out: + mutex_unlock(&pf->mbox.lock); + return rc; +} + +static void sw_fib_work_handler(struct work_struct *work) +{ + struct sw_fib_list_entry *lentry; + LIST_HEAD(tlist); + + spin_lock(&sw_fib_llock); + list_splice_init(&sw_fib_lh, &tlist); + spin_unlock(&sw_fib_llock); + + while ((lentry =3D + list_first_entry_or_null(&tlist, + struct sw_fib_list_entry, lh)) !=3D NULL) { + list_del_init(&lentry->lh); + sw_fib_notify(lentry->pf, lentry->cnt, lentry->entry); + kfree(lentry->entry); + kfree(lentry); + } + + spin_lock(&sw_fib_llock); + if (!list_empty(&sw_fib_lh)) + queue_delayed_work(sw_fib_wq, &sw_fib_work, + msecs_to_jiffies(10)); + spin_unlock(&sw_fib_llock); +} + +int sw_fib_add_to_list(struct net_device *dev, + struct fib_entry *entry, int cnt) +{ + struct otx2_nic *pf =3D netdev_priv(dev); + struct sw_fib_list_entry *lentry; + + lentry =3D kcalloc(1, sizeof(*lentry), GFP_ATOMIC); + + lentry->pf =3D pf; + lentry->cnt =3D cnt; + lentry->entry =3D entry; + INIT_LIST_HEAD(&lentry->lh); + + spin_lock(&sw_fib_llock); + list_add_tail(&lentry->lh, &sw_fib_lh); + queue_delayed_work(sw_fib_wq, &sw_fib_work, + msecs_to_jiffies(10)); + spin_unlock(&sw_fib_llock); + + return 0; +} + int sw_fib_init(void) { + sw_fib_wq =3D alloc_workqueue("sw_pf_fib_wq", 0, 0); + if (!sw_fib_wq) + return -ENOMEM; + return 0; } =20 void sw_fib_deinit(void) { + cancel_delayed_work_sync(&sw_fib_work); + destroy_workqueue(sw_fib_wq); } diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.h b/d= rivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.h index a51d15c2b80e..50c4fbca81e8 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fib.h @@ -7,6 +7,9 @@ #ifndef SW_FIB_H_ #define SW_FIB_H_ =20 +int sw_fib_add_to_list(struct net_device *dev, + struct fib_entry *entry, int cnt); + void sw_fib_deinit(void); int sw_fib_init(void); =20 diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c b/dr= ivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c index b295940ab8c7..5da643b3cec3 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c @@ -301,6 +301,8 @@ static int sw_nb_fib_event(struct notifier_block *nb, =20 pr_debug("pf_dev is %s cnt=3D%d\n", pf_dev->name, cnt); =20 + sw_fib_add_to_list(pf_dev, entries, cnt); + if (!hcnt) return NOTIFY_DONE; =20 @@ -327,6 +329,7 @@ static int sw_nb_fib_event(struct notifier_block *nb, iter->cmd, iter->dst, iter->dst_len, iter->gw, dev->name); } =20 + sw_fib_add_to_list(pf_dev, entries, hcnt); kfree(haddr); return NOTIFY_DONE; } @@ -378,6 +381,7 @@ static int sw_nb_net_event(struct notifier_block *nb, =20 pf =3D netdev_priv(pf_dev); entry->port_id =3D pf->pcifunc; + sw_fib_add_to_list(pf_dev, entry, 1); break; } =20 @@ -461,6 +465,7 @@ static int sw_nb_inetaddr_event(struct notifier_block *= nb, pr_debug("%s:%d pushing inetaddr event from HOST interface address %#x, %= pM, %s\n", __func__, __LINE__, entry->dst, entry->mac, dev->name); =20 + sw_fib_add_to_list(pf_dev, entry, 1); return NOTIFY_DONE; } =20 @@ -524,6 +529,8 @@ static int sw_nb_netdev_event(struct notifier_block *un= used, break; } =20 + sw_fib_add_to_list(pf_dev, entry, 1); + pr_debug("%s:%d pushing netdev event from HOST interface address %#x, %pM= , dev=3D%s\n", __func__, __LINE__, entry->dst, entry->mac, dev->name); =20 --=20 2.43.0 From nobody Sun Feb 8 12:14:18 2026 Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD0BB2566D3; Tue, 6 Jan 2026 02:15:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767665753; cv=none; b=Kj7tAnjR+RWAScNFuwvsq4MaMnAt0SehSG9qCHnP2Ai3NEt5IfMcgwKVLvb8/LzMFIFP9PoP4DeHlOomZifMgLS/Yg9hBl3Q+BI6WsZq99IkftfUz2kgtRP2LBXCRfxDpH3WfM/MdY+QJp6tV46pTONq0vKqOKsmE0LUF7LPpws= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767665753; c=relaxed/simple; bh=+c3GqZSWsd+zGf4GAE9uc7Q0L8b+ww84vXYrWWQdBKI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BPf41/QVmwkHlXyJXMmW3rbvMxB0QFaW19QH43IJdspNTqLqhsFpc2aQfxRADxUzhwxirQtxpw3sgYxrT15Ls+/2cm+xWuvpoOg+bp2HbeAAk7dcrANYhWsoqPir5Vl6FM3SasBsxcfzv0T+o+BKgaOpyduXleaQkJAeFHnjp+g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=Fbjx3QwT; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="Fbjx3QwT" Received: from pps.filterd (m0431384.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 605HFNHW2644729; Mon, 5 Jan 2026 18:15:41 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=u 76Uo7p8fLjH4gD/1gYIKC1LlX4XTWRBBBUmcghfHwU=; b=Fbjx3QwTn1/69Ulsw tzhQcc+L0jor/Wic4ccTI2Ws2V1x3yP9z6IkdFzKwxEYnRh8mNUOKtg/KCAyKqLn YWp53GSUdkd2LLbTHWJhvOvwj3Zjd/YYDAvQlDhjOyhe2dVqOrwD5eGEu0UNqhJ/ PzyCIUHc6oQ6/ykwOF8He63JZq0ZAASAjXfSeXj4t9WNjZ7i1660hbipgS0UgGPE QFcjIW0CTmmO8tq18oNppv5qXsaFKW9WfXfv4v3dA12lHyfwRwzPLNU7OSRB3T4Y JkuhE+ovWaFm+AOjc015DhiI+K50gU8FF7mBIvl30wRm5bD1Sli6gbshVy+zC6Mi K7PBQ== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 4bfr8bk802-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 05 Jan 2026 18:15:41 -0800 (PST) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Mon, 5 Jan 2026 18:15:39 -0800 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Mon, 5 Jan 2026 18:15:39 -0800 Received: from rkannoth-OptiPlex-7090.. (unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id 082A93F70C6; Mon, 5 Jan 2026 18:15:36 -0800 (PST) From: Ratheesh Kannoth To: , , CC: , , , , , Ratheesh Kannoth Subject: [PATCH net-next 09/10] octeontx2: switch: Flow offload support Date: Tue, 6 Jan 2026 07:44:46 +0530 Message-ID: <20260106021447.2359108-10-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260106021447.2359108-1-rkannoth@marvell.com> References: <20260106021447.2359108-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: MLgKUVgq3jG8k6ijLe5xmlURfyAA3TcM X-Proofpoint-GUID: MLgKUVgq3jG8k6ijLe5xmlURfyAA3TcM X-Authority-Analysis: v=2.4 cv=P/I3RyAu c=1 sm=1 tr=0 ts=695c704d cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=M5GUcnROAAAA:8 a=Z7sHsl9PSiaRs34vivkA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA2MDAxOCBTYWx0ZWRfX37Qj7J76IPUM MMV6hhojvkB9S/PqujJtzzyCrBVaiVlyM8kJQgZjHl2wC00nhVhLtD2voLiSAlehJ423crZIh/w LcUb2BuJoiwqQmggs8Vxumgv3ZFEk2XYtwxvPKXJLaL4ZJqIlR9TZVAgY0sWEdNU0ga5LJXzTRF hI6LWQOWhhkPlWA+gC5jQQ8h7w+AG22TVrUB9eRJmub5Q0eQr6KFALw+O4C2nJ4StlQK0/xVR+o sVdqABnLBvQ3fMdYLKTnHG7ni7lEATw457Odp+KJS3pjNkVxOMVJGMwjgoo7Sb6QBeSaH0/7XXQ rtszRYDEp3SSv8EIJmVDtv6EpwY9yUdUaNrrWKBvl8tIcF8gIBSuXHr96WTrhalfO6RrGAL2vGI lF3WHDT0+HLltklcvllX+tW+QCOSk9bCoLJvGV1uaDbpE0jWsN6kvCKuxZ0Hu3DKCpjr4NiqiPX 1MYLOFKNxfpoVis5aEA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-05_02,2026-01-05_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" OVS/NFT pushed HW acceleration rules to pf driver thru .ndo_tc(). Switchdev HW flow table is filled with this information. Once populated, flow will be accelerated. Signed-off-by: Ratheesh Kannoth --- .../marvell/octeontx2/af/switch/rvu_sw.c | 4 + .../marvell/octeontx2/af/switch/rvu_sw_fl.c | 273 +++++++++ .../marvell/octeontx2/af/switch/rvu_sw_fl.h | 2 + .../ethernet/marvell/octeontx2/nic/otx2_tc.c | 17 +- .../marvell/octeontx2/nic/switch/sw_fl.c | 516 ++++++++++++++++++ .../marvell/octeontx2/nic/switch/sw_fl.h | 2 + .../marvell/octeontx2/nic/switch/sw_nb.c | 1 - 7 files changed, 813 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c b/dr= ivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c index fe91b0a6baf5..10aed0ca5934 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw.c @@ -37,6 +37,10 @@ int rvu_mbox_handler_swdev2af_notify(struct rvu *rvu, case SWDEV2AF_MSG_TYPE_REFRESH_FDB: rc =3D rvu_sw_l2_fdb_list_entry_add(rvu, req->pcifunc, req->mac); break; + + case SWDEV2AF_MSG_TYPE_REFRESH_FL: + rc =3D rvu_sw_fl_stats_sync2db(rvu, req->fl, req->cnt); + break; } =20 return rc; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.c b= /drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.c index 1f8b82a84a5d..ab03f6596899 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.c @@ -4,12 +4,258 @@ * Copyright (C) 2026 Marvell. * */ + +#include #include "rvu.h" +#include "rvu_sw.h" +#include "rvu_sw_fl.h" + +#define M(_name, _id, _fn_name, _req_type, _rsp_type) \ +static struct _req_type __maybe_unused \ +*otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid) \ +{ \ + struct _req_type *req; \ + \ + req =3D (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ + &rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \ + sizeof(struct _rsp_type)); \ + if (!req) \ + return NULL; \ + req->hdr.sig =3D OTX2_MBOX_REQ_SIG; \ + req->hdr.id =3D _id; \ + return req; \ +} + +MBOX_UP_AF2SWDEV_MESSAGES +#undef M + +static struct workqueue_struct *sw_fl_offl_wq; + +struct fl_entry { + struct list_head list; + struct rvu *rvu; + u32 port_id; + unsigned long cookie; + struct fl_tuple tuple; + u64 flags; + u64 features; +}; + +static DEFINE_MUTEX(fl_offl_llock); +static LIST_HEAD(fl_offl_lh); +static bool fl_offl_work_running; + +static struct workqueue_struct *sw_fl_offl_wq; +static void sw_fl_offl_work_handler(struct work_struct *work); +static DECLARE_DELAYED_WORK(fl_offl_work, sw_fl_offl_work_handler); + +struct sw_fl_stats_node { + struct list_head list; + unsigned long cookie; + u16 mcam_idx[2]; + u64 opkts, npkts; + bool uni_di; +}; + +static LIST_HEAD(sw_fl_stats_lh); +static DEFINE_MUTEX(sw_fl_stats_lock); + +static int +rvu_sw_fl_stats_sync2db_one_entry(unsigned long cookie, u8 disabled, + u16 mcam_idx[2], bool uni_di, u64 pkts) +{ + struct sw_fl_stats_node *snode, *tmp; + + mutex_lock(&sw_fl_stats_lock); + list_for_each_entry_safe(snode, tmp, &sw_fl_stats_lh, list) { + if (snode->cookie !=3D cookie) + continue; + + if (disabled) { + list_del_init(&snode->list); + mutex_unlock(&sw_fl_stats_lock); + kfree(snode); + return 0; + } + + if (snode->uni_di !=3D uni_di) { + snode->uni_di =3D uni_di; + snode->mcam_idx[1] =3D mcam_idx[1]; + } + + if (snode->opkts =3D=3D pkts) { + mutex_unlock(&sw_fl_stats_lock); + return 0; + } + + snode->npkts =3D pkts; + mutex_unlock(&sw_fl_stats_lock); + return 0; + } + mutex_unlock(&sw_fl_stats_lock); + + snode =3D kcalloc(1, sizeof(*snode), GFP_KERNEL); + if (!snode) + return -ENOMEM; + + snode->cookie =3D cookie; + snode->mcam_idx[0] =3D mcam_idx[0]; + if (!uni_di) + snode->mcam_idx[1] =3D mcam_idx[1]; + + snode->npkts =3D pkts; + snode->uni_di =3D uni_di; + INIT_LIST_HEAD(&snode->list); + + mutex_lock(&sw_fl_stats_lock); + list_add_tail(&snode->list, &sw_fl_stats_lh); + mutex_unlock(&sw_fl_stats_lock); + + return 0; +} + +int rvu_sw_fl_stats_sync2db(struct rvu *rvu, struct fl_info *fl, int cnt) +{ + struct npc_mcam_get_mul_stats_req *req =3D NULL; + struct npc_mcam_get_mul_stats_rsp *rsp =3D NULL; + int tot =3D 0; + u16 i2idx_map[256]; + int rc =3D 0; + u64 pkts; + int idx; + + for (int i =3D 0; i < cnt; i++) { + tot++; + if (fl[i].uni_di) + continue; + + tot++; + } + + req =3D kcalloc(1, sizeof(*req), GFP_KERNEL); + if (!req) { + rc =3D -ENOMEM; + goto fail; + } + + rsp =3D kcalloc(1, sizeof(*rsp), GFP_KERNEL); + if (!rsp) { + rc =3D -ENOMEM; + goto fail; + } + + req->cnt =3D tot; + idx =3D 0; + for (int i =3D 0; i < tot; idx++) { + i2idx_map[i] =3D idx; + req->entry[i++] =3D fl[idx].mcam_idx[0]; + if (fl[idx].uni_di) + continue; + + i2idx_map[i] =3D idx; + req->entry[i++] =3D fl[idx].mcam_idx[1]; + } + + if (rvu_mbox_handler_npc_mcam_mul_stats(rvu, req, rsp)) { + dev_err(rvu->dev, "Error to get multiple stats\n"); + rc =3D -EFAULT; + goto fail; + } + + for (int i =3D 0; i < tot;) { + idx =3D i2idx_map[i]; + pkts =3D rsp->stat[i++]; + + if (!fl[idx].uni_di) + pkts +=3D rsp->stat[i++]; + + rc |=3D rvu_sw_fl_stats_sync2db_one_entry(fl[idx].cookie, fl[idx].dis, + fl[idx].mcam_idx, + fl[idx].uni_di, pkts); + } + +fail: + kfree(req); + kfree(rsp); + return rc; +} + +static void sw_fl_offl_dump(struct fl_entry *fl_entry) +{ + struct fl_tuple *tuple =3D &fl_entry->tuple; + + pr_debug("%pI4 to %pI4\n", &tuple->ip4src, &tuple->ip4dst); +} + +static int rvu_sw_fl_offl_rule_push(struct fl_entry *fl_entry) +{ + struct af2swdev_notify_req *req; + struct rvu *rvu; + int swdev_pf; + + rvu =3D fl_entry->rvu; + swdev_pf =3D rvu_get_pf(rvu->pdev, rvu->rswitch.pcifunc); + + mutex_lock(&rvu->mbox_lock); + req =3D otx2_mbox_alloc_msg_af2swdev_notify(rvu, swdev_pf); + if (!req) { + mutex_unlock(&rvu->mbox_lock); + return -ENOMEM; + } + + req->tuple =3D fl_entry->tuple; + req->flags =3D fl_entry->flags; + req->cookie =3D fl_entry->cookie; + req->features =3D fl_entry->features; + + sw_fl_offl_dump(fl_entry); + + otx2_mbox_wait_for_zero(&rvu->afpf_wq_info.mbox_up, swdev_pf); + otx2_mbox_msg_send_up(&rvu->afpf_wq_info.mbox_up, swdev_pf); + + mutex_unlock(&rvu->mbox_lock); + return 0; +} + +static void sw_fl_offl_work_handler(struct work_struct *work) +{ + struct fl_entry *fl_entry; + + mutex_lock(&fl_offl_llock); + fl_entry =3D list_first_entry_or_null(&fl_offl_lh, struct fl_entry, list); + if (!fl_entry) { + mutex_unlock(&fl_offl_llock); + return; + } + + list_del_init(&fl_entry->list); + mutex_unlock(&fl_offl_llock); + + rvu_sw_fl_offl_rule_push(fl_entry); + kfree(fl_entry); + + mutex_lock(&fl_offl_llock); + if (!list_empty(&fl_offl_lh)) + queue_delayed_work(sw_fl_offl_wq, &fl_offl_work, msecs_to_jiffies(10)); + mutex_unlock(&fl_offl_llock); +} =20 int rvu_mbox_handler_fl_get_stats(struct rvu *rvu, struct fl_get_stats_req *req, struct fl_get_stats_rsp *rsp) { + struct sw_fl_stats_node *snode, *tmp; + + mutex_lock(&sw_fl_stats_lock); + list_for_each_entry_safe(snode, tmp, &sw_fl_stats_lh, list) { + if (snode->cookie !=3D req->cookie) + continue; + + rsp->pkts_diff =3D snode->npkts - snode->opkts; + snode->opkts =3D snode->npkts; + break; + } + mutex_unlock(&sw_fl_stats_lock); return 0; } =20 @@ -17,5 +263,32 @@ int rvu_mbox_handler_fl_notify(struct rvu *rvu, struct fl_notify_req *req, struct msg_rsp *rsp) { + struct fl_entry *fl_entry; + + if (!(rvu->rswitch.flags & RVU_SWITCH_FLAG_FW_READY)) + return 0; + + fl_entry =3D kcalloc(1, sizeof(*fl_entry), GFP_KERNEL); + if (!fl_entry) + return -ENOMEM; + + fl_entry->port_id =3D rvu_sw_port_id(rvu, req->hdr.pcifunc); + fl_entry->rvu =3D rvu; + INIT_LIST_HEAD(&fl_entry->list); + fl_entry->tuple =3D req->tuple; + fl_entry->cookie =3D req->cookie; + fl_entry->flags =3D req->flags; + fl_entry->features =3D req->features; + + mutex_lock(&fl_offl_llock); + list_add_tail(&fl_entry->list, &fl_offl_lh); + mutex_unlock(&fl_offl_llock); + + if (!fl_offl_work_running) { + sw_fl_offl_wq =3D alloc_workqueue("sw_af_fl_wq", 0, 0); + fl_offl_work_running =3D true; + } + queue_delayed_work(sw_fl_offl_wq, &fl_offl_work, msecs_to_jiffies(10)); + return 0; } diff --git a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.h b= /drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.h index cf3e5b884f77..aa375413bc14 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/switch/rvu_sw_fl.h @@ -8,4 +8,6 @@ #ifndef RVU_SW_FL_H #define RVU_SW_FL_H =20 +int rvu_sw_fl_stats_sync2db(struct rvu *rvu, struct fl_info *fl, int cnt); + #endif diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c b/drivers= /net/ethernet/marvell/octeontx2/nic/otx2_tc.c index 26a08d2cfbb1..716764d74e6a 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c @@ -20,6 +20,7 @@ #include "cn10k.h" #include "otx2_common.h" #include "qos.h" +#include "switch/sw_fl.h" =20 #define CN10K_MAX_BURST_MANTISSA 0x7FFFULL #define CN10K_MAX_BURST_SIZE 8453888ULL @@ -1238,7 +1239,6 @@ static int otx2_tc_del_flow(struct otx2_nic *nic, mutex_unlock(&nic->mbox.lock); } =20 - free_mcam_flow: otx2_del_mcam_flow_entry(nic, flow_node->entry, NULL); otx2_tc_update_mcam_table(nic, flow_cfg, flow_node, false); @@ -1595,11 +1595,26 @@ static int otx2_setup_tc_block(struct net_device *n= etdev, int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type, void *type_data) { + struct otx2_nic *nic =3D netdev_priv(netdev); + switch (type) { case TC_SETUP_BLOCK: + if (netif_is_ovs_port(netdev)) { + return flow_block_cb_setup_simple(type_data, + &otx2_block_cb_list, + sw_fl_setup_ft_block_ingress_cb, + nic, nic, true); + } + return otx2_setup_tc_block(netdev, type_data); case TC_SETUP_QDISC_HTB: return otx2_setup_tc_htb(netdev, type_data); + + case TC_SETUP_FT: + return flow_block_cb_setup_simple(type_data, + &otx2_block_cb_list, + sw_fl_setup_ft_block_ingress_cb, + nic, nic, true); default: return -EOPNOTSUPP; } diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.c b/dr= ivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.c index 36a2359a0a48..ba3850c9d5cd 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.c @@ -4,13 +4,529 @@ * Copyright (C) 2026 Marvell. * */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../otx2_reg.h" +#include "../otx2_common.h" +#include "../otx2_struct.h" +#include "../cn10k.h" +#include "sw_nb.h" #include "sw_fl.h" =20 +#if !IS_ENABLED(CONFIG_OCTEONTX_SWITCH) +int sw_fl_setup_ft_block_ingress_cb(enum tc_setup_type type, + void *type_data, void *cb_priv) +{ + return -EOPNOTSUPP; +} + +#else + +static DEFINE_SPINLOCK(sw_fl_lock); +static LIST_HEAD(sw_fl_lh); + +struct sw_fl_list_entry { + struct list_head list; + u64 flags; + unsigned long cookie; + struct otx2_nic *pf; + struct fl_tuple tuple; +}; + +static struct workqueue_struct *sw_fl_wq; +static struct work_struct sw_fl_work; + +static int sw_fl_msg_send(struct otx2_nic *pf, + struct fl_tuple *tuple, + u64 flags, + unsigned long cookie) +{ + struct fl_notify_req *req; + int rc; + + mutex_lock(&pf->mbox.lock); + req =3D otx2_mbox_alloc_msg_fl_notify(&pf->mbox); + if (!req) { + rc =3D -ENOMEM; + goto out; + } + + req->tuple =3D *tuple; + req->flags =3D flags; + req->cookie =3D cookie; + + rc =3D otx2_sync_mbox_msg(&pf->mbox); +out: + mutex_unlock(&pf->mbox.lock); + return rc; +} + +static void sw_fl_wq_handler(struct work_struct *work) +{ + struct sw_fl_list_entry *entry; + LIST_HEAD(tlist); + + spin_lock(&sw_fl_lock); + list_splice_init(&sw_fl_lh, &tlist); + spin_unlock(&sw_fl_lock); + + while ((entry =3D + list_first_entry_or_null(&tlist, + struct sw_fl_list_entry, + list)) !=3D NULL) { + list_del_init(&entry->list); + sw_fl_msg_send(entry->pf, &entry->tuple, + entry->flags, entry->cookie); + kfree(entry); + } + + spin_lock(&sw_fl_lock); + if (!list_empty(&sw_fl_lh)) + queue_work(sw_fl_wq, &sw_fl_work); + spin_unlock(&sw_fl_lock); +} + +static int +sw_fl_add_to_list(struct otx2_nic *pf, struct fl_tuple *tuple, + unsigned long cookie, bool add_fl) +{ + struct sw_fl_list_entry *entry; + + entry =3D kcalloc(1, sizeof(*entry), GFP_ATOMIC); + if (!entry) + return -ENOMEM; + + entry->pf =3D pf; + entry->flags =3D add_fl ? FL_ADD : FL_DEL; + if (add_fl) + entry->tuple =3D *tuple; + entry->cookie =3D cookie; + entry->tuple.uni_di =3D netif_is_ovs_port(pf->netdev); + + spin_lock(&sw_fl_lock); + list_add_tail(&entry->list, &sw_fl_lh); + queue_work(sw_fl_wq, &sw_fl_work); + spin_unlock(&sw_fl_lock); + + return 0; +} + +static int sw_fl_parse_actions(struct otx2_nic *nic, + struct flow_action *flow_action, + struct flow_cls_offload *f, + struct fl_tuple *tuple, u64 *op) +{ + struct flow_action_entry *act; + struct otx2_nic *out_nic; + int err; + int used =3D 0; + int i; + + if (!flow_action_has_entries(flow_action)) + return -EINVAL; + + flow_action_for_each(i, act, flow_action) { + WARN_ON(used >=3D MANGLE_ARR_SZ); + + switch (act->id) { + case FLOW_ACTION_REDIRECT: + tuple->in_pf =3D nic->pcifunc; + out_nic =3D netdev_priv(act->dev); + tuple->xmit_pf =3D out_nic->pcifunc; + *op |=3D BIT_ULL(FLOW_ACTION_REDIRECT); + break; + + case FLOW_ACTION_CT: + err =3D nf_flow_table_offload_add_cb(act->ct.flow_table, + sw_fl_setup_ft_block_ingress_cb, + nic); + if (err !=3D -EEXIST && err) { + pr_err("%s:%d Error to offload flow, err=3D%d\n", + __func__, __LINE__, err); + break; + } + + *op |=3D BIT_ULL(FLOW_ACTION_CT); + break; + + case FLOW_ACTION_MANGLE: + tuple->mangle[used].type =3D act->mangle.htype; + tuple->mangle[used].val =3D act->mangle.val; + tuple->mangle[used].mask =3D act->mangle.mask; + tuple->mangle[used].offset =3D act->mangle.offset; + tuple->mangle_map[act->mangle.htype] |=3D BIT(used); + used++; + break; + + default: + break; + } + } + + tuple->mangle_cnt =3D used; + + if (!*op) { + pr_debug("%s:%d Op is not valid\n", __func__, __LINE__); + return -EOPNOTSUPP; + } + + return 0; +} + +static int sw_fl_get_route(struct fib_result *res, __be32 addr) +{ + struct flowi4 fl4; + + memset(&fl4, 0, sizeof(fl4)); + fl4.daddr =3D addr; + return fib_lookup(&init_net, &fl4, res, 0); +} + +static int sw_fl_get_pcifunc(__be32 dst, u16 *pcifunc, struct fl_tuple *ft= uple, bool is_in_dev) +{ + struct fib_nh_common *fib_nhc; + struct net_device *dev, *br; + struct otx2_nic *nic; + struct fib_result res; + struct list_head *lh; + int err; + + rcu_read_lock(); + + err =3D sw_fl_get_route(&res, dst); + if (err) { + pr_err("%s:%d Failed to find route to dst %pI4\n", + __func__, __LINE__, &dst); + goto done; + } + + if (res.fi->fib_type !=3D RTN_UNICAST) { + pr_err("%s:%d Not unicast route to dst %pi4\n", + __func__, __LINE__, &dst); + err =3D -EFAULT; + goto done; + } + + fib_nhc =3D fib_info_nhc(res.fi, 0); + if (!fib_nhc) { + err =3D -EINVAL; + pr_err("%s:%d Could not get fib_nhc for %pI4\n", + __func__, __LINE__, &dst); + goto done; + } + + if (unlikely(netif_is_bridge_master(fib_nhc->nhc_dev))) { + br =3D fib_nhc->nhc_dev; + + if (is_in_dev) + ftuple->is_indev_br =3D 1; + else + ftuple->is_xdev_br =3D 1; + + lh =3D &br->adj_list.lower; + if (list_empty(lh)) { + pr_err("%s:%d Unable to find any slave device\n", + __func__, __LINE__); + err =3D -EINVAL; + goto done; + } + dev =3D netdev_next_lower_dev_rcu(br, &lh); + + } else { + dev =3D fib_nhc->nhc_dev; + } + + if (!sw_nb_is_valid_dev(dev)) { + pr_err("%s:%d flow acceleration support is only for cavium devices\n", + __func__, __LINE__); + err =3D -EOPNOTSUPP; + goto done; + } + + nic =3D netdev_priv(dev); + *pcifunc =3D nic->pcifunc; + +done: + rcu_read_unlock(); + return err; +} + +static int sw_fl_parse_flow(struct otx2_nic *nic, struct flow_cls_offload = *f, + struct fl_tuple *tuple, u64 *features) +{ + struct flow_dissector *dissector; + struct flow_rule *rule; + u8 ip_proto =3D 0; + + *features =3D 0; + + rule =3D flow_cls_offload_flow_rule(f); + dissector =3D rule->match.dissector; + + if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { + struct flow_match_basic match; + + flow_rule_match_basic(rule, &match); + + /* All EtherTypes can be matched, no hw limitation */ + + if (match.mask->n_proto) { + tuple->eth_type =3D match.key->n_proto; + tuple->m_eth_type =3D match.mask->n_proto; + *features |=3D BIT_ULL(NPC_ETYPE); + } + + if (match.mask->ip_proto && + (match.key->ip_proto !=3D IPPROTO_TCP && + match.key->ip_proto !=3D IPPROTO_UDP)) { + netdev_dbg(nic->netdev, + "ip_proto=3D%u not supported\n", + match.key->ip_proto); + } + + if (match.mask->ip_proto) + ip_proto =3D match.key->ip_proto; + + if (ip_proto =3D=3D IPPROTO_UDP) { + *features |=3D BIT_ULL(NPC_IPPROTO_UDP); + } else if (ip_proto =3D=3D IPPROTO_TCP) { + *features |=3D BIT_ULL(NPC_IPPROTO_TCP); + } else { + netdev_dbg(nic->netdev, + "ip_proto=3D%u not supported\n", + match.key->ip_proto); + } + + tuple->proto =3D ip_proto; + } + + if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { + struct flow_match_eth_addrs match; + + flow_rule_match_eth_addrs(rule, &match); + + if (!is_zero_ether_addr(match.key->dst) && + is_unicast_ether_addr(match.key->dst)) { + ether_addr_copy(tuple->dmac, + match.key->dst); + + ether_addr_copy(tuple->m_dmac, + match.mask->dst); + + *features |=3D BIT_ULL(NPC_DMAC); + } + + if (!is_zero_ether_addr(match.key->src) && + is_unicast_ether_addr(match.key->src)) { + ether_addr_copy(tuple->smac, + match.key->src); + ether_addr_copy(tuple->m_smac, + match.mask->src); + *features |=3D BIT_ULL(NPC_SMAC); + } + } + + if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IPV4_ADDRS)) { + struct flow_match_ipv4_addrs match; + + flow_rule_match_ipv4_addrs(rule, &match); + + if (match.key->dst) { + tuple->ip4dst =3D match.key->dst; + tuple->m_ip4dst =3D match.mask->dst; + *features |=3D BIT_ULL(NPC_DIP_IPV4); + } + + if (match.key->src) { + tuple->ip4src =3D match.key->src; + tuple->m_ip4src =3D match.mask->src; + *features |=3D BIT_ULL(NPC_SIP_IPV4); + } + } + + if (!(*features & BIT_ULL(NPC_DMAC))) { + if (!tuple->ip4src || !tuple->ip4dst) { + pr_err("%s:%d Invalid src=3D%pI4 and dst=3D%pI4 addresses\n", + __func__, __LINE__, &tuple->ip4src, &tuple->ip4dst); + return -EINVAL; + } + + if ((tuple->ip4src & tuple->m_ip4src) =3D=3D (tuple->ip4dst & tuple->m_i= p4dst)) { + pr_err("%s:%d Masked values are same; Invalid src=3D%pI4 and dst=3D%pI4= addresses\n", + __func__, __LINE__, &tuple->ip4src, &tuple->ip4dst); + return -EINVAL; + } + } + + if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) { + struct flow_match_ports match; + + flow_rule_match_ports(rule, &match); + + if (ip_proto =3D=3D IPPROTO_UDP) { + if (match.key->dst) + *features |=3D BIT_ULL(NPC_DPORT_UDP); + + if (match.key->src) + *features |=3D BIT_ULL(NPC_SPORT_UDP); + } else if (ip_proto =3D=3D IPPROTO_TCP) { + if (match.key->dst) + *features |=3D BIT_ULL(NPC_DPORT_TCP); + + if (match.key->src) + *features |=3D BIT_ULL(NPC_SPORT_TCP); + } + + if (match.mask->src) { + tuple->sport =3D match.key->src; + tuple->m_sport =3D match.mask->src; + } + + if (match.mask->dst) { + tuple->dport =3D match.key->dst; + tuple->m_dport =3D match.mask->dst; + } + } + + if (!(*features & (BIT_ULL(NPC_DMAC) | + BIT_ULL(NPC_SMAC) | + BIT_ULL(NPC_DIP_IPV4) | + BIT_ULL(NPC_SIP_IPV4) | + BIT_ULL(NPC_DPORT_UDP) | + BIT_ULL(NPC_SPORT_UDP) | + BIT_ULL(NPC_DPORT_TCP) | + BIT_ULL(NPC_SPORT_TCP)))) { + return -EINVAL; + } + + tuple->features =3D *features; + + return 0; +} + +static int sw_fl_add(struct otx2_nic *nic, struct flow_cls_offload *f) +{ + struct fl_tuple tuple =3D { 0 }; + struct flow_rule *rule; + u64 features =3D 0; + u64 op =3D 0; + int rc; + + rule =3D flow_cls_offload_flow_rule(f); + + rc =3D sw_fl_parse_actions(nic, &rule->action, f, &tuple, &op); + if (rc) + return rc; + + if (op & BIT_ULL(FLOW_ACTION_CT)) + return 0; + + rc =3D sw_fl_parse_flow(nic, f, &tuple, &features); + if (rc) + return -EFAULT; + + if (!netif_is_ovs_port(nic->netdev)) { + rc =3D sw_fl_get_pcifunc(tuple.ip4src, &tuple.in_pf, &tuple, true); + if (rc) + return rc; + + rc =3D sw_fl_get_pcifunc(tuple.ip4dst, &tuple.xmit_pf, &tuple, false); + if (rc) + return rc; + } + + sw_fl_add_to_list(nic, &tuple, f->cookie, true); + return 0; +} + +static int sw_fl_del(struct otx2_nic *nic, struct flow_cls_offload *f) +{ + sw_fl_add_to_list(nic, NULL, f->cookie, false); + return 0; +} + +static int sw_fl_stats(struct otx2_nic *nic, struct flow_cls_offload *f) +{ + struct fl_get_stats_req *req; + struct fl_get_stats_rsp *rsp; + u64 pkts_diff; + int rc =3D 0; + + mutex_lock(&nic->mbox.lock); + + req =3D otx2_mbox_alloc_msg_fl_get_stats(&nic->mbox); + if (!req) { + pr_err("%s:%d Error happened while mcam alloc req\n", __func__, __LINE__= ); + rc =3D -ENOMEM; + goto fail; + } + req->cookie =3D f->cookie; + + if (otx2_sync_mbox_msg(&nic->mbox)) + goto fail; + + rsp =3D (struct fl_get_stats_rsp *)otx2_mbox_get_rsp + (&nic->mbox.mbox, 0, &req->hdr); + pkts_diff =3D rsp->pkts_diff; + mutex_unlock(&nic->mbox.lock); + + if (pkts_diff) { + flow_stats_update(&f->stats, 0x0, pkts_diff, + 0x0, jiffies, + FLOW_ACTION_HW_STATS_IMMEDIATE); + } + return 0; +fail: + mutex_unlock(&nic->mbox.lock); + return rc; +} + +static bool init_done; + +int sw_fl_setup_ft_block_ingress_cb(enum tc_setup_type type, + void *type_data, void *cb_priv) +{ + struct flow_cls_offload *cls =3D type_data; + struct otx2_nic *nic =3D cb_priv; + + if (!init_done) + return 0; + + switch (cls->command) { + case FLOW_CLS_REPLACE: + return sw_fl_add(nic, cls); + case FLOW_CLS_DESTROY: + return sw_fl_del(nic, cls); + case FLOW_CLS_STATS: + return sw_fl_stats(nic, cls); + default: + break; + } + + return -EOPNOTSUPP; +} + int sw_fl_init(void) { + INIT_WORK(&sw_fl_work, sw_fl_wq_handler); + sw_fl_wq =3D alloc_workqueue("sw_fl_wq", 0, 0); + if (!sw_fl_wq) + return -ENOMEM; + + init_done =3D true; return 0; } =20 void sw_fl_deinit(void) { + cancel_work_sync(&sw_fl_work); + destroy_workqueue(sw_fl_wq); } +#endif diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.h b/dr= ivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.h index cd018d770a8a..8dd816eb17d2 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.h @@ -9,5 +9,7 @@ =20 void sw_fl_deinit(void); int sw_fl_init(void); +int sw_fl_setup_ft_block_ingress_cb(enum tc_setup_type type, + void *type_data, void *cb_priv); =20 #endif // SW_FL_H diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c b/dr= ivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c index 5da643b3cec3..f4b6aa9f404e 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_nb.c @@ -21,7 +21,6 @@ #include "sw_fdb.h" #include "sw_fib.h" #include "sw_fl.h" -#include "sw_nb.h" =20 static const char *sw_nb_cmd2str[OTX2_CMD_MAX] =3D { [OTX2_DEV_UP] =3D "OTX2_DEV_UP", --=20 2.43.0 From nobody Sun Feb 8 12:14:18 2026 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38EF3239562; Tue, 6 Jan 2026 02:15:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767665753; cv=none; b=ixAWx5s5JDtQuVxpVCY7eKPxdmdjsI4pwSNFvWWwqV9fspKZo8KNwCi2a35aqrgc6LGXu6V/Zy8udm5ZbKUz9QITsodteU92XtMTQUiauhnabz+N/x/HxzDeHDuGvmNd+4W8OnMVxBqzxSmJt1cr4CGmzD4TcvUGTsHVDaCg+34= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767665753; c=relaxed/simple; bh=aGDFOyTLZfv2IQyX9EtmxyYcsOHHfQ2B1PeajKzAZns=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qzVKwpJV216LjgVTDxAqfe4IgDBibvUhxgHGP87XtAK+6P4KvohDs0AL+Sri56p0U2FRDnyslb0fTp5UsevAP/Cb9P8AnGDX9vNFocA1IM+ONCep2yNnc4xeVFjdOv8U5b9zsZYYqlCT0Wac2RZNBqsQ+eX7+/YkafzzTRU06sY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=OwEgoSAF; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="OwEgoSAF" Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 605EShsv2795652; Mon, 5 Jan 2026 18:15:43 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=z O+fdnic0woPTV2ppw1I+krARqRe5oQoi6/WHf2PoyE=; b=OwEgoSAF1anzFsSmf iUX3IiOdFEapXQII3kXfLQV1+zOPOevIl73pNcThU7QX8MrW9tPJYVcbLoQnqicn 64Za0GviHgDjfdDbHsxfc+FjBuEcpwQ5qvDS65ILOVhYk3jsQSqec6+7AfkmDCpV xxBLzUv5Ym7du5KAhYGTnoTAIiwb61H6P+mj+FXH6DxiIM9vGzw1s4gm/wGjswKZ J0JhEJXqmlQlIdFF0Ui+JQux3xeN5o5ovnF0BtnT7tKUlVFx+ytUjz6SLRFuAt+j 6QbRjfKsMr7xDigkwWg6OB0dfhQoM0sZDcLRsXTWx3mm9Y+4vjevd95bcbISqDTb Y6P1w== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 4bgf3fsa5w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 05 Jan 2026 18:15:43 -0800 (PST) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Mon, 5 Jan 2026 18:15:43 -0800 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Mon, 5 Jan 2026 18:15:42 -0800 Received: from rkannoth-OptiPlex-7090.. (unknown [10.28.36.165]) by maili.marvell.com (Postfix) with ESMTP id 2CEBC3F70C5; Mon, 5 Jan 2026 18:15:39 -0800 (PST) From: Ratheesh Kannoth To: , , CC: , , , , , Ratheesh Kannoth Subject: [PATCH net-next 10/10] octeontx2: switch: trace support Date: Tue, 6 Jan 2026 07:44:47 +0530 Message-ID: <20260106021447.2359108-11-rkannoth@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260106021447.2359108-1-rkannoth@marvell.com> References: <20260106021447.2359108-1-rkannoth@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=PLgCOPqC c=1 sm=1 tr=0 ts=695c704f cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=vUbySO9Y5rIA:10 a=VkNPw1HP01LnGYTKEx00:22 a=M5GUcnROAAAA:8 a=gFDZAJeugxnc_ztJiqIA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA2MDAxOCBTYWx0ZWRfX0dt+yGH/LIK+ NU0i2j3XqNCWFo1r3f/hIKPFNRaEfzQSGZgJsI2dpx5CKeOps8ZeI8HcBtHX9dkYHc//0yQ6qSU Zvg8maSN/bZ9nkl6F1mLHmIh1Nu+LIiVotbSAU+AliORfL1wgRHf6S2msGNoFRiwAPw83VRgS2o Gw1PS2pShItL89Hq9DXcqpa1T2lPIoOURj3J1SYxJ3yUdE1RJwD0arlGf9SAtKWmuQUTqj2Y5gu fVQsYwiFmZJQwKrmWnOdQSFByh/XV8m4gVfKWhHqqWVsGWeGMOwzh9LJREswMyblCqxvmdK5mFr H3AY0teR1VpNi9kVV6dCUM8M/pZvqpu6wGtryPtJPvc5vCzNXvBcxQDfYSmyd71Pai3R3btLaZW SacyIWTa+9YSvinGSk9wVYN+fUBSi6Dsk04E0EGB8qTlPNcKLag8JCHIbAr5UAxPn7WAjKnrTa5 rHq3W1DuU4i5oONwlKA== X-Proofpoint-GUID: C9gpFoIOMhE6py7ypJmaZmxPZseC0Pl8 X-Proofpoint-ORIG-GUID: C9gpFoIOMhE6py7ypJmaZmxPZseC0Pl8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-05_02,2026-01-05_01,2025-10-01_01 Content-Type: text/plain; charset="utf-8" Traces are added to flow parsing to ease debugging. Signed-off-by: Ratheesh Kannoth --- .../ethernet/marvell/octeontx2/nic/Makefile | 2 +- .../marvell/octeontx2/nic/switch/sw_fl.c | 18 +++- .../marvell/octeontx2/nic/switch/sw_trace.c | 11 +++ .../marvell/octeontx2/nic/switch/sw_trace.h | 82 +++++++++++++++++++ 4 files changed, 109 insertions(+), 4 deletions(-) create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_tr= ace.c create mode 100644 drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_tr= ace.h diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/Makefile b/drivers/= net/ethernet/marvell/octeontx2/nic/Makefile index da87e952c187..5f722d0cfac2 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/Makefile +++ b/drivers/net/ethernet/marvell/octeontx2/nic/Makefile @@ -13,7 +13,7 @@ rvu_nicpf-y :=3D otx2_pf.o otx2_common.o otx2_txrx.o otx2= _ethtool.o \ switch/sw_fdb.o switch/sw_fl.o =20 ifdef CONFIG_OCTEONTX_SWITCH -rvu_nicpf-y +=3D switch/sw_nb.o switch/sw_fib.o +rvu_nicpf-y +=3D switch/sw_nb.o switch/sw_fib.o switch/sw_trace.o endif =20 rvu_nicvf-y :=3D otx2_vf.o diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.c b/dr= ivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.c index ba3850c9d5cd..d348c77cb1f8 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_fl.c @@ -18,6 +18,7 @@ #include "../otx2_struct.h" #include "../cn10k.h" #include "sw_nb.h" +#include "sw_trace.h" #include "sw_fl.h" =20 #if !IS_ENABLED(CONFIG_OCTEONTX_SWITCH) @@ -137,6 +138,7 @@ static int sw_fl_parse_actions(struct otx2_nic *nic, =20 switch (act->id) { case FLOW_ACTION_REDIRECT: + trace_sw_act_dump(__func__, __LINE__, act->id); tuple->in_pf =3D nic->pcifunc; out_nic =3D netdev_priv(act->dev); tuple->xmit_pf =3D out_nic->pcifunc; @@ -144,6 +146,7 @@ static int sw_fl_parse_actions(struct otx2_nic *nic, break; =20 case FLOW_ACTION_CT: + trace_sw_act_dump(__func__, __LINE__, act->id); err =3D nf_flow_table_offload_add_cb(act->ct.flow_table, sw_fl_setup_ft_block_ingress_cb, nic); @@ -157,6 +160,7 @@ static int sw_fl_parse_actions(struct otx2_nic *nic, break; =20 case FLOW_ACTION_MANGLE: + trace_sw_act_dump(__func__, __LINE__, act->id); tuple->mangle[used].type =3D act->mangle.htype; tuple->mangle[used].val =3D act->mangle.val; tuple->mangle[used].mask =3D act->mangle.mask; @@ -166,6 +170,7 @@ static int sw_fl_parse_actions(struct otx2_nic *nic, break; =20 default: + trace_sw_act_dump(__func__, __LINE__, act->id); break; } } @@ -429,19 +434,26 @@ static int sw_fl_add(struct otx2_nic *nic, struct flo= w_cls_offload *f) return 0; =20 rc =3D sw_fl_parse_flow(nic, f, &tuple, &features); - if (rc) + if (rc) { + trace_sw_fl_dump(__func__, __LINE__, &tuple); return -EFAULT; + } =20 if (!netif_is_ovs_port(nic->netdev)) { rc =3D sw_fl_get_pcifunc(tuple.ip4src, &tuple.in_pf, &tuple, true); - if (rc) + if (rc) { + trace_sw_fl_dump(__func__, __LINE__, &tuple); return rc; + } =20 rc =3D sw_fl_get_pcifunc(tuple.ip4dst, &tuple.xmit_pf, &tuple, false); - if (rc) + if (rc) { + trace_sw_fl_dump(__func__, __LINE__, &tuple); return rc; + } } =20 + trace_sw_fl_dump(__func__, __LINE__, &tuple); sw_fl_add_to_list(nic, &tuple, f->cookie, true); return 0; } diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_trace.c b= /drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_trace.c new file mode 100644 index 000000000000..260fd2bb3606 --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_trace.c @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Marvell RVU Admin Function driver + * + * Copyright (C) 2026 Marvell. + * + */ + +#define CREATE_TRACE_POINTS +#include "sw_trace.h" +EXPORT_TRACEPOINT_SYMBOL(sw_fl_dump); +EXPORT_TRACEPOINT_SYMBOL(sw_act_dump); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_trace.h b= /drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_trace.h new file mode 100644 index 000000000000..4353c440a4c6 --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/nic/switch/sw_trace.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Marvell RVU Admin Function driver + * + * Copyright (C) 2026 Marvell. + * + */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM rvu + +#if !defined(SW_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define SW_TRACE_H + +#include +#include + +#include "mbox.h" + +TRACE_EVENT(sw_fl_dump, + TP_PROTO(const char *fname, int line, struct fl_tuple *ftuple), + TP_ARGS(fname, line, ftuple), + TP_STRUCT__entry(__string(f, fname) + __field(int, l) + __array(u8, smac, ETH_ALEN) + __array(u8, dmac, ETH_ALEN) + __field(u16, eth_type) + __field(u32, sip) + __field(u32, dip) + __field(u8, ip_proto) + __field(u16, sport) + __field(u16, dport) + __field(u8, uni_di) + __field(u16, in_pf) + __field(u16, out_pf) + ), + TP_fast_assign(__assign_str(f); + __entry->l =3D line; + memcpy(__entry->smac, ftuple->smac, ETH_ALEN); + memcpy(__entry->dmac, ftuple->dmac, ETH_ALEN); + __entry->sip =3D ftuple->ip4src; + __entry->dip =3D ftuple->ip4dst; + __entry->eth_type =3D ftuple->eth_type; + __entry->ip_proto =3D ftuple->proto; + __entry->sport =3D ftuple->sport; + __entry->dport =3D ftuple->dport; + __entry->uni_di =3D ftuple->uni_di; + __entry->in_pf =3D ftuple->in_pf; + __entry->out_pf =3D ftuple->xmit_pf; + ), + TP_printk("[%s:%d] %pM %pI4:%u to %pM %pI4:%u eth_type=3D%#x proto=3D= %u uni=3D%u in=3D%#x out=3D%#x", + __get_str(f), __entry->l, __entry->smac, &__entry->sip, __entry->s= port, + __entry->dmac, &__entry->dip, __entry->dport, + ntohs(__entry->eth_type), __entry->ip_proto, __entry->uni_di, + __entry->in_pf, __entry->out_pf) +); + +TRACE_EVENT(sw_act_dump, + TP_PROTO(const char *fname, int line, u32 act), + TP_ARGS(fname, line, act), + TP_STRUCT__entry(__string(fname, fname) + __field(int, line) + __field(u32, act) + ), + + TP_fast_assign(__assign_str(fname); + __entry->line =3D line; + __entry->act =3D act; + ), + + TP_printk("[%s:%d] %u", + __get_str(fname), __entry->line, __entry->act) +); + +#endif + +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH ../../drivers/net/ethernet/marvell/octeontx2/ni= c/switch/ + +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_FILE sw_trace + +#include --=20 2.43.0