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Signed-off-by: Mrinmay Sarkar Reviewed-by: Krzysztof Kozlowski --- .../bindings/pci/qcom,sa8255p-pcie-ep.yaml | 110 +++++++++++++++++= ++++ 1 file changed, 110 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,sa8255p-pcie-ep.yam= l b/Documentation/devicetree/bindings/pci/qcom,sa8255p-pcie-ep.yaml new file mode 100644 index 0000000000000000000000000000000000000000..e338797d5dc2f68e2ad658e7f2c= 073023c4aea75 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,sa8255p-pcie-ep.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,sa8255p-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm firmware managed PCIe Endpoint Controller + +description: + Qualcomm SA8255p SoC PCIe endpoint controller is based on the Synopsys + DesignWare PCIe IP which is managed by firmware. + +maintainers: + - Manivannan Sadhasivam + +properties: + compatible: + const: qcom,sa8255p-pcie-ep + + reg: + items: + - description: Qualcomm-specific PARF configuration registers + - description: DesignWare PCIe registers + - description: External local bus interface registers + - description: Address Translation Unit (ATU) registers + - description: Memory region used to map remote RC address space + - description: BAR memory region + - description: DMA register space + + reg-names: + items: + - const: parf + - const: dbi + - const: elbi + - const: atu + - const: addr_space + - const: mmio + - const: dma + + interrupts: + items: + - description: PCIe Global interrupt + - description: PCIe Doorbell interrupt + - description: DMA interrupt + + interrupt-names: + items: + - const: global + - const: doorbell + - const: dma + + iommus: + maxItems: 1 + + reset-gpios: + description: GPIO used as PERST# input signal + maxItems: 1 + + wake-gpios: + description: GPIO used as WAKE# output signal + maxItems: 1 + + power-domains: + maxItems: 1 + + dma-coherent: true + + num-lanes: + default: 2 + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - reset-gpios + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells =3D <2>; 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Tue, 06 Jan 2026 04:35:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IHge5WmZqCBf8j+3Ngw9xkT9W1WtOx50n7DYYhwZyH4ZZwl7y63KFgminhgHunMQGCuKBeUeg== X-Received: by 2002:a05:6a00:4295:b0:781:1f28:eadd with SMTP id d2e1a72fcca58-81880b6c513mr2696923b3a.20.1767702915396; Tue, 06 Jan 2026 04:35:15 -0800 (PST) Received: from hu-msarkar-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-819c59e83bcsm2161583b3a.56.2026.01.06.04.35.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jan 2026 04:35:15 -0800 (PST) From: Mrinmay Sarkar Date: Tue, 06 Jan 2026 18:04:46 +0530 Subject: [PATCH v5 2/2] PCI: qcom-ep: Add support for firmware-managed PCIe Endpoint Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260106-firmware_managed_ep-v5-2-1933432127ec@oss.qualcomm.com> References: <20260106-firmware_managed_ep-v5-0-1933432127ec@oss.qualcomm.com> In-Reply-To: <20260106-firmware_managed_ep-v5-0-1933432127ec@oss.qualcomm.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Krishna Chaitanya Chundru , quic_vbadigan@quicinc.com, quic_shazhuss@quicinc.com, konrad.dybcio@oss.qualcomm.com, Mrinmay sarkar , Rama Krishna , Ayiluri Naga Rashmi , Nitesh Gupta X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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In these cases, the Linux driver should not perform resource enable or disable operations directly. Additionally, runtime PM support has been enabled to ensure proper power state transitions. This commit introduces a `firmware_managed` flag in the Endpoint configuration structure. When set, the driver skips resource handling and uses generic runtime PM calls to let firmware do resource management. A new compatible string is added for SA8255P platforms where firmware manages resources. Signed-off-by: Mrinmay Sarkar --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 61 +++++++++++++++++++++++++++= ---- 1 file changed, 53 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index f1bc0ac81a928b928ab3f8cc7bf82558fc430474..38fcc241032b60e4c93574e4d75= 9596ddf268efa 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -168,11 +168,13 @@ enum qcom_pcie_ep_link_status { * @hdma_support: HDMA support on this SoC * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache = snooping * @disable_mhi_ram_parity_check: Disable MHI RAM data parity error check + * @firmware_managed: Set if the Endpoint controller is firmware managed */ struct qcom_pcie_ep_cfg { bool hdma_support; bool override_no_snoop; bool disable_mhi_ram_parity_check; + bool firmware_managed; }; =20 /** @@ -377,6 +379,14 @@ static int qcom_pcie_enable_resources(struct qcom_pcie= _ep *pcie_ep) =20 static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep) { + struct device *dev =3D pcie_ep->pci.dev; + + pm_runtime_put(dev); + + /* Skip resource disablement if Endpoint controller is firmware-managed */ + if (pcie_ep->cfg && pcie_ep->cfg->firmware_managed) + return; + icc_set_bw(pcie_ep->icc_mem, 0, 0); phy_power_off(pcie_ep->phy); phy_exit(pcie_ep->phy); @@ -390,12 +400,24 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *p= ci) u32 val, offset; int ret; =20 + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) { + dev_err(dev, "Failed to enable endpoint device: %d\n", ret); + return ret; + } + + /* Skip resource enablement if Endpoint controller is firmware-managed */ + if (pcie_ep->cfg && pcie_ep->cfg->firmware_managed) + goto skip_resources_enable; + ret =3D qcom_pcie_enable_resources(pcie_ep); if (ret) { dev_err(dev, "Failed to enable resources: %d\n", ret); + pm_runtime_put(dev); return ret; } =20 +skip_resources_enable: /* Perform cleanup that requires refclk */ pci_epc_deinit_notify(pci->ep.epc); dw_pcie_ep_cleanup(&pci->ep); @@ -630,6 +652,17 @@ static int qcom_pcie_ep_get_resources(struct platform_= device *pdev, return ret; } =20 + pcie_ep->reset =3D devm_gpiod_get(dev, "reset", GPIOD_IN); + if (IS_ERR(pcie_ep->reset)) + return PTR_ERR(pcie_ep->reset); + + pcie_ep->wake =3D devm_gpiod_get_optional(dev, "wake", GPIOD_OUT_LOW); + if (IS_ERR(pcie_ep->wake)) + return PTR_ERR(pcie_ep->wake); + + if (pcie_ep->cfg && pcie_ep->cfg->firmware_managed) + return 0; + pcie_ep->num_clks =3D devm_clk_bulk_get_all(dev, &pcie_ep->clks); if (pcie_ep->num_clks < 0) { dev_err(dev, "Failed to get clocks\n"); @@ -640,14 +673,6 @@ static int qcom_pcie_ep_get_resources(struct platform_= device *pdev, if (IS_ERR(pcie_ep->core_reset)) return PTR_ERR(pcie_ep->core_reset); =20 - pcie_ep->reset =3D devm_gpiod_get(dev, "reset", GPIOD_IN); - if (IS_ERR(pcie_ep->reset)) - return PTR_ERR(pcie_ep->reset); - - pcie_ep->wake =3D devm_gpiod_get_optional(dev, "wake", GPIOD_OUT_LOW); - if (IS_ERR(pcie_ep->wake)) - return PTR_ERR(pcie_ep->wake); - pcie_ep->phy =3D devm_phy_optional_get(dev, "pciephy"); if (IS_ERR(pcie_ep->phy)) ret =3D PTR_ERR(pcie_ep->phy); @@ -874,6 +899,12 @@ static int qcom_pcie_ep_probe(struct platform_device *= pdev) =20 platform_set_drvdata(pdev, pcie_ep); =20 + pm_runtime_get_noresume(dev); + pm_runtime_set_active(dev); + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return ret; + ret =3D qcom_pcie_ep_get_resources(pdev, pcie_ep); if (ret) return ret; @@ -894,6 +925,12 @@ static int qcom_pcie_ep_probe(struct platform_device *= pdev) goto err_disable_irqs; } =20 + ret =3D pm_runtime_put_sync(dev); + if (ret < 0) { + dev_err(dev, "Failed to disable endpoint device: %d\n", ret); + goto err_disable_irqs; + } + pcie_ep->debugfs =3D debugfs_create_dir(name, NULL); qcom_pcie_ep_init_debugfs(pcie_ep); =20 @@ -930,7 +967,15 @@ static const struct qcom_pcie_ep_cfg cfg_1_34_0 =3D { .disable_mhi_ram_parity_check =3D true, }; =20 +static const struct qcom_pcie_ep_cfg cfg_1_34_0_fw_managed =3D { + .hdma_support =3D true, + .override_no_snoop =3D true, + .disable_mhi_ram_parity_check =3D true, + .firmware_managed =3D true, +}; + static const struct of_device_id qcom_pcie_ep_match[] =3D { + { .compatible =3D "qcom,sa8255p-pcie-ep", .data =3D &cfg_1_34_0_fw_manage= d}, { .compatible =3D "qcom,sa8775p-pcie-ep", .data =3D &cfg_1_34_0}, { .compatible =3D "qcom,sdx55-pcie-ep", }, { .compatible =3D "qcom,sm8450-pcie-ep", }, --=20 2.25.1