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[2a02:3100:a8ad:5500:1e86:bff:fe2f:57b7]) by smtp.googlemail.com with ESMTPSA id a640c23a62f3a-b842a233ef3sm26240566b.1.2026.01.05.12.47.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jan 2026 12:47:35 -0800 (PST) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, jian.hu@amlogic.com, jbrunet@baylibre.com, Martin Blumenstingl Subject: [PATCH v1 2/3] clk: meson: g12a: Limit the HDMI PLL OD to /4 Date: Mon, 5 Jan 2026 21:47:09 +0100 Message-ID: <20260105204710.447779-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260105204710.447779-1-martin.blumenstingl@googlemail.com> References: <20260105204710.447779-1-martin.blumenstingl@googlemail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" GXBB has the HDMI PLL OD in the HHI_HDMI_PLL_CNTL2 register while for G12A/G12B/SM1 the OD has moved to HHI_HDMI_PLL_CNTL0. At first glance the rest of the OD setup seems identical. However, looking at the downstream kernel sources as well as testing shows that G12A/G12B/SM1 only supports three OD values: - register value 0 means: divide by 1 - register value 1 means: divide by 2 - register value 2 means: divide by 4 Downstream sources are also only using OD register values 0, 1 and 2 for G12A/G12B/SM1 (while for GXBB the downstream kernel sources are also using value 3 which means: divide by 8). Add clk_div_table and have it replace the CLK_DIVIDER_POWER_OF_TWO flag to make the kernel's view of this register match with how the hardware actually works. Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Signed-off-by: Martin Blumenstingl --- drivers/clk/meson/g12a.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 185b6348251d..19057d2dff47 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -777,12 +777,19 @@ static struct clk_regmap g12a_hdmi_pll_dco =3D { }, }; =20 +static const struct clk_div_table g12a_hdmi_pll_od_div_table[] =3D { + { .val =3D 0, .div =3D 1 }, + { .val =3D 1, .div =3D 2 }, + { .val =3D 2, .div =3D 4 }, + { /* sentinel */ } +}; + static struct clk_regmap g12a_hdmi_pll_od =3D { .data =3D &(struct clk_regmap_div_data){ .offset =3D HHI_HDMI_PLL_CNTL0, .shift =3D 16, .width =3D 2, - .flags =3D CLK_DIVIDER_POWER_OF_TWO, + .table =3D g12a_hdmi_pll_od_div_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "hdmi_pll_od", @@ -800,7 +807,7 @@ static struct clk_regmap g12a_hdmi_pll_od2 =3D { .offset =3D HHI_HDMI_PLL_CNTL0, .shift =3D 18, .width =3D 2, - .flags =3D CLK_DIVIDER_POWER_OF_TWO, + .table =3D g12a_hdmi_pll_od_div_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "hdmi_pll_od2", @@ -818,7 +825,7 @@ static struct clk_regmap g12a_hdmi_pll =3D { .offset =3D HHI_HDMI_PLL_CNTL0, .shift =3D 20, .width =3D 2, - .flags =3D CLK_DIVIDER_POWER_OF_TWO, + .table =3D g12a_hdmi_pll_od_div_table, }, .hw.init =3D &(struct clk_init_data){ .name =3D "hdmi_pll", --=20 2.52.0