From nobody Mon Feb 9 22:19:02 2026 Received: from mta-64-225.siemens.flowmailer.net (mta-64-225.siemens.flowmailer.net [185.136.64.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A4A2833B6F0 for ; Mon, 5 Jan 2026 17:54:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.64.225 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767635661; cv=none; b=JxbKF5sKH1CnPgqZDIFEHGQ/IPk7aFevl7WF/zweAZOQPLDdP84MlHhvPcsljkwMCCumnGm9dtuKFoQvy/XvBhgewxiW72fSUIqU0FYUt1CW/8Q5GY6tpQuC5Dz6KxVf8L1r9ZNy5QjrRDh0joQ8koYA/lIGT43XQ3beNg9+2Ao= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767635661; c=relaxed/simple; bh=EBm/YQI9I0Cx3kFnWopwMJkeOGt2puAwe2xLZXInpPU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=t5me2aWah7egisszRMq+sDf9OyWmgEwReQwrQpbpGGBpDA0OpvVMcHG18CNMMD1gJsJqkMy4cmcu7pg8irei7SeBDlAJ6ihUeXMlldNdF6gEQTvAyQh8xEU/K0CLPVZ34lX6Cngrv1WHDsEUWtD+aD/08s7bj6W/qNX+6abKsvo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com; dkim=pass (2048-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b=Lt5pjqMb; arc=none smtp.client-ip=185.136.64.225 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b="Lt5pjqMb" Received: by mta-64-225.siemens.flowmailer.net with ESMTPSA id 20260105175415b91d57fdb70002076f for ; Mon, 05 Jan 2026 18:54:15 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=alexander.sverdlin@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=+cNctosICkbQmisl8GDG+alFgnVkKRXfvi6QE6hmyKU=; b=Lt5pjqMbuTWBDA3l7Ins0mXnGK8lpRKao3PxSZbt8kU6hjr4B3/7O1/MzkR/HNp2vOkP/t RZxtHYINA6+ABCy/1icqC58Sg5sOuRcZf8j/7Uo0zkUV5w2kopZoooW2KEzYjRKa6qc/bD4o u0wM7CpG12bQnM/KIo6pUFFqyDRyawyiTpYauyiN4nDF+XvWlTzKqL6v9aoOv0vseDjt3f2h lzg3qi8j6IYstyuoCexly/UhgRGZ3vL7pGDobQG5jzFKzlyw1wqM9yWNMchcf0VXy/BPwDOO 1CHDabSKLkolCl18wDKcTHN2FRHPky490oI7WMUnI0lOYRyKHEDtf1kQ==; From: "A. Sverdlin" To: netdev@vger.kernel.org Cc: Alexander Sverdlin , Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Daniel Golle Subject: [PATCH v3 2/2] net: dsa: mxl-gsw1xx: Support R(G)MII slew rate configuration Date: Mon, 5 Jan 2026 18:53:11 +0100 Message-ID: <20260105175320.2141753-3-alexander.sverdlin@siemens.com> In-Reply-To: <20260105175320.2141753-1-alexander.sverdlin@siemens.com> References: <20260105175320.2141753-1-alexander.sverdlin@siemens.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-456497:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Alexander Sverdlin Support newly introduced slew-rate device tree property to configure R(G)MII interface pins slew rate. It might be used to reduce the radiated emissions. Signed-off-by: Alexander Sverdlin --- Changelog: v3: - use [pinctrl] standard "slew-rate" property as suggested by Rob https://lore.kernel.org/all/20251219204324.GA3881969-robh@kernel.org/ - better sorted struct gswip_hw_info initialisers as suggested by Daniel v2: - do not hijack gsw1xx_phylink_mac_select_pcs() for configuring the port, introduce struct gswip_hw_info::port_setup callback - actively configure "normal" slew rate (if the new DT property is missing) - properly use regmap_set_bits() (v1 had reg and value mixed up) drivers/net/dsa/lantiq/lantiq_gswip.h | 1 + drivers/net/dsa/lantiq/lantiq_gswip_common.c | 6 ++++ drivers/net/dsa/lantiq/mxl-gsw1xx.c | 31 ++++++++++++++++++++ drivers/net/dsa/lantiq/mxl-gsw1xx.h | 2 ++ 4 files changed, 40 insertions(+) diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.h b/drivers/net/dsa/lantiq= /lantiq_gswip.h index 2e0f2afbadbbc..8fc4c7cc5283a 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip.h +++ b/drivers/net/dsa/lantiq/lantiq_gswip.h @@ -263,6 +263,7 @@ struct gswip_hw_info { struct phylink_config *config); struct phylink_pcs *(*mac_select_pcs)(struct phylink_config *config, phy_interface_t interface); + int (*port_setup)(struct dsa_switch *ds, int port); }; =20 struct gswip_gphy_fw { diff --git a/drivers/net/dsa/lantiq/lantiq_gswip_common.c b/drivers/net/dsa= /lantiq/lantiq_gswip_common.c index e790f2ef75884..17a61e445f00f 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip_common.c +++ b/drivers/net/dsa/lantiq/lantiq_gswip_common.c @@ -425,6 +425,12 @@ static int gswip_port_setup(struct dsa_switch *ds, int= port) struct gswip_priv *priv =3D ds->priv; int err; =20 + if (priv->hw_info->port_setup) { + err =3D priv->hw_info->port_setup(ds, port); + if (err) + return err; + } + if (!dsa_is_cpu_port(ds, port)) { err =3D gswip_add_single_port_br(priv, port, true); if (err) diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.c b/drivers/net/dsa/lantiq/m= xl-gsw1xx.c index f8ff8a604bf53..6c290bac537ad 100644 --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.c +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.c @@ -559,6 +559,34 @@ static struct phylink_pcs *gsw1xx_phylink_mac_select_p= cs(struct phylink_config * } } =20 +static int gsw1xx_port_setup(struct dsa_switch *ds, int port) +{ + struct dsa_port *dp =3D dsa_to_port(ds, port); + struct gsw1xx_priv *gsw1xx_priv; + struct gswip_priv *gswip_priv; + u32 rate; + int ret; + + if (dp->index !=3D GSW1XX_MII_PORT) + return 0; + + gswip_priv =3D ds->priv; + gsw1xx_priv =3D container_of(gswip_priv, struct gsw1xx_priv, gswip); + + ret =3D of_property_read_u32(dp->dn, "slew-rate", &rate); + /* Optional property */ + if (ret =3D=3D -EINVAL) + return 0; + if (ret < 0 || rate > 1) { + dev_err(&gsw1xx_priv->mdio_dev->dev, "Invalid slew-rate\n"); + return (ret < 0) ? ret : -EINVAL; + } + + return regmap_update_bits(gsw1xx_priv->shell, GSW1XX_SHELL_RGMII_SLEW_CFG, + RGMII_SLEW_CFG_DRV_TXD | RGMII_SLEW_CFG_DRV_TXC, + (RGMII_SLEW_CFG_DRV_TXD | RGMII_SLEW_CFG_DRV_TXC) * rate); +} + static struct regmap *gsw1xx_regmap_init(struct gsw1xx_priv *priv, const char *name, unsigned int reg_base, @@ -707,6 +735,7 @@ static const struct gswip_hw_info gsw12x_data =3D { .mac_select_pcs =3D gsw1xx_phylink_mac_select_pcs, .phylink_get_caps =3D &gsw1xx_phylink_get_caps, .supports_2500m =3D true, + .port_setup =3D gsw1xx_port_setup, .pce_microcode =3D &gsw1xx_pce_microcode, .pce_microcode_size =3D ARRAY_SIZE(gsw1xx_pce_microcode), .tag_protocol =3D DSA_TAG_PROTO_MXL_GSW1XX, @@ -720,6 +749,7 @@ static const struct gswip_hw_info gsw140_data =3D { .mac_select_pcs =3D gsw1xx_phylink_mac_select_pcs, .phylink_get_caps =3D &gsw1xx_phylink_get_caps, .supports_2500m =3D true, + .port_setup =3D gsw1xx_port_setup, .pce_microcode =3D &gsw1xx_pce_microcode, .pce_microcode_size =3D ARRAY_SIZE(gsw1xx_pce_microcode), .tag_protocol =3D DSA_TAG_PROTO_MXL_GSW1XX, @@ -732,6 +762,7 @@ static const struct gswip_hw_info gsw141_data =3D { .mii_port_reg_offset =3D -GSW1XX_MII_PORT, .mac_select_pcs =3D gsw1xx_phylink_mac_select_pcs, .phylink_get_caps =3D gsw1xx_phylink_get_caps, + .port_setup =3D gsw1xx_port_setup, .pce_microcode =3D &gsw1xx_pce_microcode, .pce_microcode_size =3D ARRAY_SIZE(gsw1xx_pce_microcode), .tag_protocol =3D DSA_TAG_PROTO_MXL_GSW1XX, diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.h b/drivers/net/dsa/lantiq/m= xl-gsw1xx.h index 38e03c048a26c..8c0298b2b7663 100644 --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.h +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.h @@ -110,6 +110,8 @@ #define GSW1XX_RST_REQ_SGMII_SHELL BIT(5) /* RGMII PAD Slew Control Register */ #define GSW1XX_SHELL_RGMII_SLEW_CFG 0x78 +#define RGMII_SLEW_CFG_DRV_TXC BIT(2) +#define RGMII_SLEW_CFG_DRV_TXD BIT(3) #define RGMII_SLEW_CFG_RX_2_5_V BIT(4) #define RGMII_SLEW_CFG_TX_2_5_V BIT(5) =20 --=20 2.52.0