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Mon, 05 Jan 2026 03:54:08 -0800 (PST) Received: from hu-prashk-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7ff7e48cd07sm48125744b3a.46.2026.01.05.03.54.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jan 2026 03:54:07 -0800 (PST) From: Prashanth K To: Thinh Nguyen , Greg Kroah-Hartman Cc: linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, Prashanth K Subject: [PATCH v2 2/3] usb: dwc3: Add dwc pointer to dwc3_readl/writel Date: Mon, 5 Jan 2026 17:23:24 +0530 Message-Id: <20260105115325.1765176-3-prashanth.k@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260105115325.1765176-1-prashanth.k@oss.qualcomm.com> References: <20260105115325.1765176-1-prashanth.k@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=I5Vohdgg c=1 sm=1 tr=0 ts=695ba663 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=1-JGb9IuH62Of12rmQMA:9 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: v9WXsc8nSNLU6BuEEbai4RY2mB5KueKt X-Proofpoint-ORIG-GUID: v9WXsc8nSNLU6BuEEbai4RY2mB5KueKt X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA1MDEwNCBTYWx0ZWRfXxS9xYpvEivYz 3MVn3x7QEQEQRZiFYSXUSN+VSL2f4GQSX+MbipP8Kx4UiFJqA3I+dNfywGOeeV0oP4xSYOK1u5n bfRy5TVGnFsV7eVcFPQWespDeSd5cx2QKNxFYcPWMYo3nouaYcP30Q1tcgGpjXsyajtNq309Gqs YxFgmmUyyDYUypfRZ8i0fZSk64sTHR082Y7F9c+iYUcXKyLQGMJB9WSWUDDFJfmJKdR+RM1HHX/ JZeirRovnWuWdGkODI7jH68eM7xPAqeWeYwS04dj7AhY7JpgE6HJZ+VTQimPI+Fj+JeiSdDtOXY gUDU5nWiaFdU9hukj7ZHFxMenXCdEh0+UeXIM4KS+RtYBXtGfvyeJ/lKMqFMgv674gDmbSbFFty I+q1RP1wqZoGCnPQqMIOATEbXLaD4WT5aHlH3qZ+JCwOgWTd6Y3Ah73B9XnN/zeKR1HWssq6XeL 2qmyxqzoXp+YSNGQSDA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-05_01,2025-12-31_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 priorityscore=1501 bulkscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601050104 Content-Type: text/plain; charset="utf-8" Use dwc pointer in dwc3_readl() dwc3_writel() instead of passing the dwc->regs. This would help us access the dwc structure and log the base address in traces. There's no functional changes in this patch, just refactoring existing APIs. Signed-off-by: Prashanth K Acked-by: Thinh Nguyen --- drivers/usb/dwc3/core.c | 194 ++++++++++++++++++------------------- drivers/usb/dwc3/debugfs.c | 32 +++--- drivers/usb/dwc3/drd.c | 76 +++++++-------- drivers/usb/dwc3/ep0.c | 20 ++-- drivers/usb/dwc3/gadget.c | 160 +++++++++++++++--------------- drivers/usb/dwc3/gadget.h | 4 +- drivers/usb/dwc3/io.h | 7 +- drivers/usb/dwc3/ulpi.c | 10 +- 8 files changed, 253 insertions(+), 250 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index ec8407972b9d..670a9d4bfff2 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -114,23 +114,23 @@ void dwc3_enable_susphy(struct dwc3 *dwc, bool enable) int i; =20 for (i =3D 0; i < dwc->num_usb3_ports; i++) { - reg =3D dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i)); + reg =3D dwc3_readl(dwc, DWC3_GUSB3PIPECTL(i)); if (enable && !dwc->dis_u3_susphy_quirk) reg |=3D DWC3_GUSB3PIPECTL_SUSPHY; else reg &=3D ~DWC3_GUSB3PIPECTL_SUSPHY; =20 - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg); + dwc3_writel(dwc, DWC3_GUSB3PIPECTL(i), reg); } =20 for (i =3D 0; i < dwc->num_usb2_ports; i++) { - reg =3D dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); + reg =3D dwc3_readl(dwc, DWC3_GUSB2PHYCFG(i)); if (enable && !dwc->dis_u2_susphy_quirk) reg |=3D DWC3_GUSB2PHYCFG_SUSPHY; else reg &=3D ~DWC3_GUSB2PHYCFG_SUSPHY; =20 - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); + dwc3_writel(dwc, DWC3_GUSB2PHYCFG(i), reg); } } EXPORT_SYMBOL_GPL(dwc3_enable_susphy); @@ -140,7 +140,7 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool i= gnore_susphy) unsigned int hw_mode; u32 reg; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_GCTL); + reg =3D dwc3_readl(dwc, DWC3_GCTL); =20 /* * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE and @@ -155,7 +155,7 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool i= gnore_susphy) =20 reg &=3D ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); reg |=3D DWC3_GCTL_PRTCAPDIR(mode); - dwc3_writel(dwc->regs, DWC3_GCTL, reg); + dwc3_writel(dwc, DWC3_GCTL, reg); =20 dwc->current_dr_role =3D mode; trace_dwc3_set_prtcap(mode); @@ -216,9 +216,9 @@ static void __dwc3_set_mode(struct work_struct *work) if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || DWC3_VER_IS_PRIOR(DWC31, 190A)) && desired_dr_role !=3D DWC3_GCTL_PRTCAP_OTG)) { - reg =3D dwc3_readl(dwc->regs, DWC3_GCTL); + reg =3D dwc3_readl(dwc, DWC3_GCTL); reg |=3D DWC3_GCTL_CORESOFTRESET; - dwc3_writel(dwc->regs, DWC3_GCTL, reg); + dwc3_writel(dwc, DWC3_GCTL, reg); =20 /* * Wait for internal clocks to synchronized. DWC_usb31 and @@ -228,9 +228,9 @@ static void __dwc3_set_mode(struct work_struct *work) */ msleep(100); =20 - reg =3D dwc3_readl(dwc->regs, DWC3_GCTL); + reg =3D dwc3_readl(dwc, DWC3_GCTL); reg &=3D ~DWC3_GCTL_CORESOFTRESET; - dwc3_writel(dwc->regs, DWC3_GCTL, reg); + dwc3_writel(dwc, DWC3_GCTL, reg); } =20 spin_lock_irqsave(&dwc->lock, flags); @@ -254,9 +254,9 @@ static void __dwc3_set_mode(struct work_struct *work) phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST); =20 if (dwc->dis_split_quirk) { - reg =3D dwc3_readl(dwc->regs, DWC3_GUCTL3); + reg =3D dwc3_readl(dwc, DWC3_GUCTL3); reg |=3D DWC3_GUCTL3_SPLITDISABLE; - dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); + dwc3_writel(dwc, DWC3_GUCTL3, reg); } } break; @@ -306,11 +306,11 @@ u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) struct dwc3 *dwc =3D dep->dwc; u32 reg; =20 - dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, - DWC3_GDBGFIFOSPACE_NUM(dep->number) | - DWC3_GDBGFIFOSPACE_TYPE(type)); + dwc3_writel(dwc, DWC3_GDBGFIFOSPACE, + DWC3_GDBGFIFOSPACE_NUM(dep->number) | + DWC3_GDBGFIFOSPACE_TYPE(type)); =20 - reg =3D dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); + reg =3D dwc3_readl(dwc, DWC3_GDBGFIFOSPACE); =20 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); } @@ -332,7 +332,7 @@ int dwc3_core_soft_reset(struct dwc3 *dwc) if (dwc->current_dr_role =3D=3D DWC3_GCTL_PRTCAP_HOST) return 0; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DCTL); + reg =3D dwc3_readl(dwc, DWC3_DCTL); reg |=3D DWC3_DCTL_CSFTRST; reg &=3D ~DWC3_DCTL_RUN_STOP; dwc3_gadget_dctl_write_safe(dwc, reg); @@ -347,7 +347,7 @@ int dwc3_core_soft_reset(struct dwc3 *dwc) retries =3D 10; =20 do { - reg =3D dwc3_readl(dwc->regs, DWC3_DCTL); + reg =3D dwc3_readl(dwc, DWC3_DCTL); if (!(reg & DWC3_DCTL_CSFTRST)) goto done; =20 @@ -387,12 +387,12 @@ static void dwc3_frame_length_adjustment(struct dwc3 = *dwc) if (dwc->fladj =3D=3D 0) return; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_GFLADJ); + reg =3D dwc3_readl(dwc, DWC3_GFLADJ); dft =3D reg & DWC3_GFLADJ_30MHZ_MASK; if (dft !=3D dwc->fladj) { reg &=3D ~DWC3_GFLADJ_30MHZ_MASK; reg |=3D DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; - dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); + dwc3_writel(dwc, DWC3_GFLADJ, reg); } } =20 @@ -424,10 +424,10 @@ static void dwc3_ref_clk_period(struct dwc3 *dwc) return; } =20 - reg =3D dwc3_readl(dwc->regs, DWC3_GUCTL); + reg =3D dwc3_readl(dwc, DWC3_GUCTL); reg &=3D ~DWC3_GUCTL_REFCLKPER_MASK; reg |=3D FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); - dwc3_writel(dwc->regs, DWC3_GUCTL, reg); + dwc3_writel(dwc, DWC3_GUCTL, reg); =20 if (DWC3_VER_IS_PRIOR(DWC3, 250A)) return; @@ -455,7 +455,7 @@ static void dwc3_ref_clk_period(struct dwc3 *dwc) */ decr =3D 480000000 / rate; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_GFLADJ); + reg =3D dwc3_readl(dwc, DWC3_GFLADJ); reg &=3D ~DWC3_GFLADJ_REFCLK_FLADJ_MASK & ~DWC3_GFLADJ_240MHZDECR & ~DWC3_GFLADJ_240MHZDECR_PLS1; @@ -466,7 +466,7 @@ static void dwc3_ref_clk_period(struct dwc3 *dwc) if (dwc->gfladj_refclk_lpm_sel) reg |=3D DWC3_GFLADJ_REFCLK_LPM_SEL; =20 - dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); + dwc3_writel(dwc, DWC3_GFLADJ, reg); } =20 /** @@ -569,16 +569,16 @@ int dwc3_event_buffers_setup(struct dwc3 *dwc) =20 evt =3D dwc->ev_buf; evt->lpos =3D 0; - dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), - lower_32_bits(evt->dma)); - dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), - upper_32_bits(evt->dma)); - dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), - DWC3_GEVNTSIZ_SIZE(evt->length)); + dwc3_writel(dwc, DWC3_GEVNTADRLO(0), + lower_32_bits(evt->dma)); + dwc3_writel(dwc, DWC3_GEVNTADRHI(0), + upper_32_bits(evt->dma)); + dwc3_writel(dwc, DWC3_GEVNTSIZ(0), + DWC3_GEVNTSIZ_SIZE(evt->length)); =20 /* Clear any stale event */ - reg =3D dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); - dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), reg); + reg =3D dwc3_readl(dwc, DWC3_GEVNTCOUNT(0)); + dwc3_writel(dwc, DWC3_GEVNTCOUNT(0), reg); return 0; } =20 @@ -593,7 +593,7 @@ void dwc3_event_buffers_cleanup(struct dwc3 *dwc) * Exynos platforms may not be able to access event buffer if the * controller failed to halt on dwc3_core_exit(). */ - reg =3D dwc3_readl(dwc->regs, DWC3_DSTS); + reg =3D dwc3_readl(dwc, DWC3_DSTS); if (!(reg & DWC3_DSTS_DEVCTRLHLT)) return; =20 @@ -601,14 +601,14 @@ void dwc3_event_buffers_cleanup(struct dwc3 *dwc) =20 evt->lpos =3D 0; =20 - dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); - dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); - dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK + dwc3_writel(dwc, DWC3_GEVNTADRLO(0), 0); + dwc3_writel(dwc, DWC3_GEVNTADRHI(0), 0); + dwc3_writel(dwc, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK | DWC3_GEVNTSIZ_SIZE(0)); =20 /* Clear any stale event */ - reg =3D dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); - dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), reg); + reg =3D dwc3_readl(dwc, DWC3_GEVNTCOUNT(0)); + dwc3_writel(dwc, DWC3_GEVNTCOUNT(0), reg); } =20 static void dwc3_core_num_eps(struct dwc3 *dwc) @@ -622,18 +622,18 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc) { struct dwc3_hwparams *parms =3D &dwc->hwparams; =20 - parms->hwparams0 =3D dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); - parms->hwparams1 =3D dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); - parms->hwparams2 =3D dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); - parms->hwparams3 =3D dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); - parms->hwparams4 =3D dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); - parms->hwparams5 =3D dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); - parms->hwparams6 =3D dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); - parms->hwparams7 =3D dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); - parms->hwparams8 =3D dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); + parms->hwparams0 =3D dwc3_readl(dwc, DWC3_GHWPARAMS0); + parms->hwparams1 =3D dwc3_readl(dwc, DWC3_GHWPARAMS1); + parms->hwparams2 =3D dwc3_readl(dwc, DWC3_GHWPARAMS2); + parms->hwparams3 =3D dwc3_readl(dwc, DWC3_GHWPARAMS3); + parms->hwparams4 =3D dwc3_readl(dwc, DWC3_GHWPARAMS4); + parms->hwparams5 =3D dwc3_readl(dwc, DWC3_GHWPARAMS5); + parms->hwparams6 =3D dwc3_readl(dwc, DWC3_GHWPARAMS6); + parms->hwparams7 =3D dwc3_readl(dwc, DWC3_GHWPARAMS7); + parms->hwparams8 =3D dwc3_readl(dwc, DWC3_GHWPARAMS8); =20 if (DWC3_IP_IS(DWC32)) - parms->hwparams9 =3D dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); + parms->hwparams9 =3D dwc3_readl(dwc, DWC3_GHWPARAMS9); } =20 static void dwc3_config_soc_bus(struct dwc3 *dwc) @@ -641,10 +641,10 @@ static void dwc3_config_soc_bus(struct dwc3 *dwc) if (dwc->gsbuscfg0_reqinfo !=3D DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED) { u32 reg; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); + reg =3D dwc3_readl(dwc, DWC3_GSBUSCFG0); reg &=3D ~DWC3_GSBUSCFG0_REQINFO(~0); reg |=3D DWC3_GSBUSCFG0_REQINFO(dwc->gsbuscfg0_reqinfo); - dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg); + dwc3_writel(dwc, DWC3_GSBUSCFG0, reg); } } =20 @@ -668,7 +668,7 @@ static int dwc3_ss_phy_setup(struct dwc3 *dwc, int inde= x) { u32 reg; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index)); + reg =3D dwc3_readl(dwc, DWC3_GUSB3PIPECTL(index)); =20 /* * Make sure UX_EXIT_PX is cleared as that causes issues with some @@ -706,7 +706,7 @@ static int dwc3_ss_phy_setup(struct dwc3 *dwc, int inde= x) if (dwc->dis_del_phy_power_chg_quirk) reg &=3D ~DWC3_GUSB3PIPECTL_DEPOCHANGE; =20 - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg); + dwc3_writel(dwc, DWC3_GUSB3PIPECTL(index), reg); =20 return 0; } @@ -715,7 +715,7 @@ static int dwc3_hs_phy_setup(struct dwc3 *dwc, int inde= x) { u32 reg; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index)); + reg =3D dwc3_readl(dwc, DWC3_GUSB2PHYCFG(index)); =20 /* Select the HS PHY interface */ switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { @@ -727,7 +727,7 @@ static int dwc3_hs_phy_setup(struct dwc3 *dwc, int inde= x) } else if (dwc->hsphy_interface && !strncmp(dwc->hsphy_interface, "ulpi", 4)) { reg |=3D DWC3_GUSB2PHYCFG_ULPI_UTMI; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg); + dwc3_writel(dwc, DWC3_GUSB2PHYCFG(index), reg); } else { /* Relying on default value. */ if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) @@ -777,7 +777,7 @@ static int dwc3_hs_phy_setup(struct dwc3 *dwc, int inde= x) if (dwc->ulpi_ext_vbus_drv) reg |=3D DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV; =20 - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg); + dwc3_writel(dwc, DWC3_GUSB2PHYCFG(index), reg); =20 return 0; } @@ -991,15 +991,15 @@ static bool dwc3_core_is_valid(struct dwc3 *dwc) { u32 reg; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_GSNPSID); + reg =3D dwc3_readl(dwc, DWC3_GSNPSID); dwc->ip =3D DWC3_GSNPS_ID(reg); =20 /* This should read as U3 followed by revision number */ if (DWC3_IP_IS(DWC3)) { dwc->revision =3D reg; } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { - dwc->revision =3D dwc3_readl(dwc->regs, DWC3_VER_NUMBER); - dwc->version_type =3D dwc3_readl(dwc->regs, DWC3_VER_TYPE); + dwc->revision =3D dwc3_readl(dwc, DWC3_VER_NUMBER); + dwc->version_type =3D dwc3_readl(dwc, DWC3_VER_TYPE); } else { return false; } @@ -1013,7 +1013,7 @@ static void dwc3_core_setup_global_control(struct dwc= 3 *dwc) unsigned int hw_mode; u32 reg; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_GCTL); + reg =3D dwc3_readl(dwc, DWC3_GCTL); reg &=3D ~DWC3_GCTL_SCALEDOWN_MASK; hw_mode =3D DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); power_opt =3D DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); @@ -1091,7 +1091,7 @@ static void dwc3_core_setup_global_control(struct dwc= 3 *dwc) if (DWC3_VER_IS_PRIOR(DWC3, 190A)) reg |=3D DWC3_GCTL_U2RSTECN; =20 - dwc3_writel(dwc->regs, DWC3_GCTL, reg); + dwc3_writel(dwc, DWC3_GCTL, reg); } =20 static int dwc3_core_get_phy(struct dwc3 *dwc); @@ -1111,7 +1111,7 @@ static void dwc3_set_incr_burst_type(struct dwc3 *dwc) int ret; int i; =20 - cfg =3D dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); + cfg =3D dwc3_readl(dwc, DWC3_GSBUSCFG0); =20 /* * Handle property "snps,incr-burst-type-adjustment". @@ -1186,7 +1186,7 @@ static void dwc3_set_incr_burst_type(struct dwc3 *dwc) break; } =20 - dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); + dwc3_writel(dwc, DWC3_GSBUSCFG0, cfg); } =20 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc) @@ -1211,12 +1211,12 @@ static void dwc3_set_power_down_clk_scale(struct dw= c3 *dwc) * (3x or more) to be within the requirement. */ scale =3D DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000); - reg =3D dwc3_readl(dwc->regs, DWC3_GCTL); + reg =3D dwc3_readl(dwc, DWC3_GCTL); if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) || (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) { reg &=3D ~(DWC3_GCTL_PWRDNSCALE_MASK); reg |=3D DWC3_GCTL_PWRDNSCALE(scale); - dwc3_writel(dwc->regs, DWC3_GCTL, reg); + dwc3_writel(dwc, DWC3_GCTL, reg); } } =20 @@ -1239,7 +1239,7 @@ static void dwc3_config_threshold(struct dwc3 *dwc) tx_maxburst =3D dwc->tx_max_burst_prd; =20 if (rx_thr_num && rx_maxburst) { - reg =3D dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); + reg =3D dwc3_readl(dwc, DWC3_GRXTHRCFG); reg |=3D DWC31_RXTHRNUMPKTSEL_PRD; =20 reg &=3D ~DWC31_RXTHRNUMPKT_PRD(~0); @@ -1248,11 +1248,11 @@ static void dwc3_config_threshold(struct dwc3 *dwc) reg &=3D ~DWC31_MAXRXBURSTSIZE_PRD(~0); reg |=3D DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); =20 - dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); + dwc3_writel(dwc, DWC3_GRXTHRCFG, reg); } =20 if (tx_thr_num && tx_maxburst) { - reg =3D dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); + reg =3D dwc3_readl(dwc, DWC3_GTXTHRCFG); reg |=3D DWC31_TXTHRNUMPKTSEL_PRD; =20 reg &=3D ~DWC31_TXTHRNUMPKT_PRD(~0); @@ -1261,7 +1261,7 @@ static void dwc3_config_threshold(struct dwc3 *dwc) reg &=3D ~DWC31_MAXTXBURSTSIZE_PRD(~0); reg |=3D DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); =20 - dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); + dwc3_writel(dwc, DWC3_GTXTHRCFG, reg); } } =20 @@ -1272,7 +1272,7 @@ static void dwc3_config_threshold(struct dwc3 *dwc) =20 if (DWC3_IP_IS(DWC3)) { if (rx_thr_num && rx_maxburst) { - reg =3D dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); + reg =3D dwc3_readl(dwc, DWC3_GRXTHRCFG); reg |=3D DWC3_GRXTHRCFG_PKTCNTSEL; =20 reg &=3D ~DWC3_GRXTHRCFG_RXPKTCNT(~0); @@ -1281,11 +1281,11 @@ static void dwc3_config_threshold(struct dwc3 *dwc) reg &=3D ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0); reg |=3D DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst); =20 - dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); + dwc3_writel(dwc, DWC3_GRXTHRCFG, reg); } =20 if (tx_thr_num && tx_maxburst) { - reg =3D dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); + reg =3D dwc3_readl(dwc, DWC3_GTXTHRCFG); reg |=3D DWC3_GTXTHRCFG_PKTCNTSEL; =20 reg &=3D ~DWC3_GTXTHRCFG_TXPKTCNT(~0); @@ -1294,11 +1294,11 @@ static void dwc3_config_threshold(struct dwc3 *dwc) reg &=3D ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0); reg |=3D DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst); =20 - dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); + dwc3_writel(dwc, DWC3_GTXTHRCFG, reg); } } else { if (rx_thr_num && rx_maxburst) { - reg =3D dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); + reg =3D dwc3_readl(dwc, DWC3_GRXTHRCFG); reg |=3D DWC31_GRXTHRCFG_PKTCNTSEL; =20 reg &=3D ~DWC31_GRXTHRCFG_RXPKTCNT(~0); @@ -1307,11 +1307,11 @@ static void dwc3_config_threshold(struct dwc3 *dwc) reg &=3D ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0); reg |=3D DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst); =20 - dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); + dwc3_writel(dwc, DWC3_GRXTHRCFG, reg); } =20 if (tx_thr_num && tx_maxburst) { - reg =3D dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); + reg =3D dwc3_readl(dwc, DWC3_GTXTHRCFG); reg |=3D DWC31_GTXTHRCFG_PKTCNTSEL; =20 reg &=3D ~DWC31_GTXTHRCFG_TXPKTCNT(~0); @@ -1320,7 +1320,7 @@ static void dwc3_config_threshold(struct dwc3 *dwc) reg &=3D ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0); reg |=3D DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst); =20 - dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); + dwc3_writel(dwc, DWC3_GTXTHRCFG, reg); } } } @@ -1343,7 +1343,7 @@ int dwc3_core_init(struct dwc3 *dwc) * Write Linux Version Code to our GUID register so it's easy to figure * out which kernel version a bug was found. */ - dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); + dwc3_writel(dwc, DWC3_GUID, LINUX_VERSION_CODE); =20 ret =3D dwc3_phy_setup(dwc); if (ret) @@ -1408,9 +1408,9 @@ int dwc3_core_init(struct dwc3 *dwc) * DWC_usb31 controller. */ if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { - reg =3D dwc3_readl(dwc->regs, DWC3_GUCTL2); + reg =3D dwc3_readl(dwc, DWC3_GUCTL2); reg |=3D DWC3_GUCTL2_RST_ACTBITLATER; - dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); + dwc3_writel(dwc, DWC3_GUCTL2, reg); } =20 /* @@ -1423,9 +1423,9 @@ int dwc3_core_init(struct dwc3 *dwc) * setting GUCTL2[19] by default; instead, use GUCTL2[19] =3D 0. */ if (DWC3_VER_IS(DWC3, 320A)) { - reg =3D dwc3_readl(dwc->regs, DWC3_GUCTL2); + reg =3D dwc3_readl(dwc, DWC3_GUCTL2); reg &=3D ~DWC3_GUCTL2_LC_TIMER; - dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); + dwc3_writel(dwc, DWC3_GUCTL2, reg); } =20 /* @@ -1438,13 +1438,13 @@ int dwc3_core_init(struct dwc3 *dwc) * legacy ULPI PHYs. */ if (dwc->resume_hs_terminations) { - reg =3D dwc3_readl(dwc->regs, DWC3_GUCTL1); + reg =3D dwc3_readl(dwc, DWC3_GUCTL1); reg |=3D DWC3_GUCTL1_RESUME_OPMODE_HS_HOST; - dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); + dwc3_writel(dwc, DWC3_GUCTL1, reg); } =20 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { - reg =3D dwc3_readl(dwc->regs, DWC3_GUCTL1); + reg =3D dwc3_readl(dwc, DWC3_GUCTL1); =20 /* * Enable hardware control of sending remote wakeup @@ -1479,7 +1479,7 @@ int dwc3_core_init(struct dwc3 *dwc) reg &=3D ~DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; } =20 - dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); + dwc3_writel(dwc, DWC3_GUCTL1, reg); } =20 dwc3_config_threshold(dwc); @@ -1490,9 +1490,9 @@ int dwc3_core_init(struct dwc3 *dwc) int i; =20 for (i =3D 0; i < dwc->num_usb3_ports; i++) { - reg =3D dwc3_readl(dwc->regs, DWC3_LLUCTL(i)); + reg =3D dwc3_readl(dwc, DWC3_LLUCTL(i)); reg |=3D DWC3_LLUCTL_FORCE_GEN1; - dwc3_writel(dwc->regs, DWC3_LLUCTL(i), reg); + dwc3_writel(dwc, DWC3_LLUCTL(i), reg); } } =20 @@ -1511,9 +1511,9 @@ int dwc3_core_init(struct dwc3 *dwc) * function is available only from version 1.70a. */ if (DWC3_VER_IS_WITHIN(DWC31, 170A, 180A)) { - reg =3D dwc3_readl(dwc->regs, DWC3_GUCTL3); + reg =3D dwc3_readl(dwc, DWC3_GUCTL3); reg |=3D DWC3_GUCTL3_USB20_RETRY_DISABLE; - dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); + dwc3_writel(dwc, DWC3_GUCTL3, reg); } =20 return 0; @@ -2437,9 +2437,9 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_m= essage_t msg) int ret; =20 if (!pm_runtime_suspended(dwc->dev) && !PMSG_IS_AUTO(msg)) { - dwc->susphy_state =3D (dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)) & + dwc->susphy_state =3D (dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0)) & DWC3_GUSB2PHYCFG_SUSPHY) || - (dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)) & + (dwc3_readl(dwc, DWC3_GUSB3PIPECTL(0)) & DWC3_GUSB3PIPECTL_SUSPHY); /* * TI AM62 platform requires SUSPHY to be @@ -2469,10 +2469,10 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm= _message_t msg) if (dwc->dis_u2_susphy_quirk || dwc->dis_enblslpm_quirk) { for (i =3D 0; i < dwc->num_usb2_ports; i++) { - reg =3D dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); + reg =3D dwc3_readl(dwc, DWC3_GUSB2PHYCFG(i)); reg |=3D DWC3_GUSB2PHYCFG_ENBLSLPM | DWC3_GUSB2PHYCFG_SUSPHY; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); + dwc3_writel(dwc, DWC3_GUSB2PHYCFG(i), reg); } =20 /* Give some time for USB2 PHY to suspend */ @@ -2532,14 +2532,14 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_= message_t msg) } /* Restore GUSB2PHYCFG bits that were modified in suspend */ for (i =3D 0; i < dwc->num_usb2_ports; i++) { - reg =3D dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); + reg =3D dwc3_readl(dwc, DWC3_GUSB2PHYCFG(i)); if (dwc->dis_u2_susphy_quirk) reg &=3D ~DWC3_GUSB2PHYCFG_SUSPHY; =20 if (dwc->dis_enblslpm_quirk) reg &=3D ~DWC3_GUSB2PHYCFG_ENBLSLPM; =20 - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); + dwc3_writel(dwc, DWC3_GUSB2PHYCFG(i), reg); } =20 for (i =3D 0; i < dwc->num_usb2_ports; i++) @@ -2721,9 +2721,9 @@ void dwc3_pm_complete(struct dwc3 *dwc) =20 if (dwc->current_dr_role =3D=3D DWC3_GCTL_PRTCAP_HOST && dwc->dis_split_quirk) { - reg =3D dwc3_readl(dwc->regs, DWC3_GUCTL3); + reg =3D dwc3_readl(dwc, DWC3_GUCTL3); reg |=3D DWC3_GUCTL3_SPLITDISABLE; - dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); + dwc3_writel(dwc, DWC3_GUCTL3, reg); } } EXPORT_SYMBOL_GPL(dwc3_pm_complete); diff --git a/drivers/usb/dwc3/debugfs.c b/drivers/usb/dwc3/debugfs.c index 0b45ff16f575..ffb1101f55c7 100644 --- a/drivers/usb/dwc3/debugfs.c +++ b/drivers/usb/dwc3/debugfs.c @@ -296,14 +296,14 @@ static void dwc3_host_lsp(struct seq_file *s) =20 reg =3D DWC3_GDBGLSPMUX_HOSTSELECT(sel); =20 - dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg); - val =3D dwc3_readl(dwc->regs, DWC3_GDBGLSP); + dwc3_writel(dwc, DWC3_GDBGLSPMUX, reg); + val =3D dwc3_readl(dwc, DWC3_GDBGLSP); seq_printf(s, "GDBGLSP[%d] =3D 0x%08x\n", sel, val); =20 if (dbc_enabled && sel < 256) { reg |=3D DWC3_GDBGLSPMUX_ENDBC; - dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg); - val =3D dwc3_readl(dwc->regs, DWC3_GDBGLSP); + dwc3_writel(dwc, DWC3_GDBGLSPMUX, reg); + val =3D dwc3_readl(dwc, DWC3_GDBGLSP); seq_printf(s, "GDBGLSP_DBC[%d] =3D 0x%08x\n", sel, val); } } @@ -316,8 +316,8 @@ static void dwc3_gadget_lsp(struct seq_file *s) =20 for (i =3D 0; i < 16; i++) { reg =3D DWC3_GDBGLSPMUX_DEVSELECT(i); - dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg); - reg =3D dwc3_readl(dwc->regs, DWC3_GDBGLSP); + dwc3_writel(dwc, DWC3_GDBGLSPMUX, reg); + reg =3D dwc3_readl(dwc, DWC3_GDBGLSP); seq_printf(s, "GDBGLSP[%d] =3D 0x%08x\n", i, reg); } } @@ -335,7 +335,7 @@ static int dwc3_lsp_show(struct seq_file *s, void *unus= ed) return ret; =20 spin_lock_irqsave(&dwc->lock, flags); - reg =3D dwc3_readl(dwc->regs, DWC3_GSTS); + reg =3D dwc3_readl(dwc, DWC3_GSTS); current_mode =3D DWC3_GSTS_CURMOD(reg); =20 switch (current_mode) { @@ -406,7 +406,7 @@ static int dwc3_mode_show(struct seq_file *s, void *unu= sed) return ret; =20 spin_lock_irqsave(&dwc->lock, flags); - reg =3D dwc3_readl(dwc->regs, DWC3_GCTL); + reg =3D dwc3_readl(dwc, DWC3_GCTL); spin_unlock_irqrestore(&dwc->lock, flags); =20 mode =3D DWC3_GCTL_PRTCAP(reg); @@ -478,7 +478,7 @@ static int dwc3_testmode_show(struct seq_file *s, void = *unused) return ret; =20 spin_lock_irqsave(&dwc->lock, flags); - reg =3D dwc3_readl(dwc->regs, DWC3_DCTL); + reg =3D dwc3_readl(dwc, DWC3_DCTL); reg &=3D DWC3_DCTL_TSTCTRL_MASK; reg >>=3D 1; spin_unlock_irqrestore(&dwc->lock, flags); @@ -577,7 +577,7 @@ static int dwc3_link_state_show(struct seq_file *s, voi= d *unused) return ret; =20 spin_lock_irqsave(&dwc->lock, flags); - reg =3D dwc3_readl(dwc->regs, DWC3_GSTS); + reg =3D dwc3_readl(dwc, DWC3_GSTS); if (DWC3_GSTS_CURMOD(reg) !=3D DWC3_GSTS_CURMOD_DEVICE) { seq_puts(s, "Not available\n"); spin_unlock_irqrestore(&dwc->lock, flags); @@ -585,7 +585,7 @@ static int dwc3_link_state_show(struct seq_file *s, voi= d *unused) return 0; } =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DSTS); + reg =3D dwc3_readl(dwc, DWC3_DSTS); state =3D DWC3_DSTS_USBLNKST(reg); speed =3D reg & DWC3_DSTS_CONNECTSPD; =20 @@ -639,14 +639,14 @@ static ssize_t dwc3_link_state_write(struct file *fil= e, return ret; =20 spin_lock_irqsave(&dwc->lock, flags); - reg =3D dwc3_readl(dwc->regs, DWC3_GSTS); + reg =3D dwc3_readl(dwc, DWC3_GSTS); if (DWC3_GSTS_CURMOD(reg) !=3D DWC3_GSTS_CURMOD_DEVICE) { spin_unlock_irqrestore(&dwc->lock, flags); pm_runtime_put_sync(dwc->dev); return -EINVAL; } =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DSTS); + reg =3D dwc3_readl(dwc, DWC3_DSTS); speed =3D reg & DWC3_DSTS_CONNECTSPD; =20 if (speed < DWC3_DSTS_SUPERSPEED && @@ -942,10 +942,10 @@ static int dwc3_ep_info_register_show(struct seq_file= *s, void *unused) =20 spin_lock_irqsave(&dwc->lock, flags); reg =3D DWC3_GDBGLSPMUX_EPSELECT(dep->number); - dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg); + dwc3_writel(dwc, DWC3_GDBGLSPMUX, reg); =20 - lower_32_bits =3D dwc3_readl(dwc->regs, DWC3_GDBGEPINFO0); - upper_32_bits =3D dwc3_readl(dwc->regs, DWC3_GDBGEPINFO1); + lower_32_bits =3D dwc3_readl(dwc, DWC3_GDBGEPINFO0); + upper_32_bits =3D dwc3_readl(dwc, DWC3_GDBGEPINFO1); =20 ep_info =3D ((u64)upper_32_bits << 32) | lower_32_bits; seq_printf(s, "0x%016llx\n", ep_info); diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c index 589bbeb27454..9558862d63d8 100644 --- a/drivers/usb/dwc3/drd.c +++ b/drivers/usb/dwc3/drd.c @@ -18,25 +18,25 @@ =20 static void dwc3_otg_disable_events(struct dwc3 *dwc, u32 disable_mask) { - u32 reg =3D dwc3_readl(dwc->regs, DWC3_OEVTEN); + u32 reg =3D dwc3_readl(dwc, DWC3_OEVTEN); =20 reg &=3D ~(disable_mask); - dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); + dwc3_writel(dwc, DWC3_OEVTEN, reg); } =20 static void dwc3_otg_enable_events(struct dwc3 *dwc, u32 enable_mask) { - u32 reg =3D dwc3_readl(dwc->regs, DWC3_OEVTEN); + u32 reg =3D dwc3_readl(dwc, DWC3_OEVTEN); =20 reg |=3D (enable_mask); - dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); + dwc3_writel(dwc, DWC3_OEVTEN, reg); } =20 static void dwc3_otg_clear_events(struct dwc3 *dwc) { - u32 reg =3D dwc3_readl(dwc->regs, DWC3_OEVT); + u32 reg =3D dwc3_readl(dwc, DWC3_OEVT); =20 - dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); + dwc3_writel(dwc, DWC3_OEVTEN, reg); } =20 #define DWC3_OTG_ALL_EVENTS (DWC3_OEVTEN_XHCIRUNSTPSETEN | \ @@ -72,18 +72,18 @@ static irqreturn_t dwc3_otg_irq(int irq, void *_dwc) struct dwc3 *dwc =3D _dwc; irqreturn_t ret =3D IRQ_NONE; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_OEVT); + reg =3D dwc3_readl(dwc, DWC3_OEVT); if (reg) { /* ignore non OTG events, we can't disable them in OEVTEN */ if (!(reg & DWC3_OTG_ALL_EVENTS)) { - dwc3_writel(dwc->regs, DWC3_OEVT, reg); + dwc3_writel(dwc, DWC3_OEVT, reg); return IRQ_NONE; } =20 if (dwc->current_otg_role =3D=3D DWC3_OTG_ROLE_HOST && !(reg & DWC3_OEVT_DEVICEMODE)) dwc->otg_restart_host =3D true; - dwc3_writel(dwc->regs, DWC3_OEVT, reg); + dwc3_writel(dwc, DWC3_OEVT, reg); ret =3D IRQ_WAKE_THREAD; } =20 @@ -100,23 +100,23 @@ static void dwc3_otgregs_init(struct dwc3 *dwc) * the signal outputs sent to the PHY, the OTG FSM logic of the * core and also the resets to the VBUS filters inside the core. */ - reg =3D dwc3_readl(dwc->regs, DWC3_OCFG); + reg =3D dwc3_readl(dwc, DWC3_OCFG); reg |=3D DWC3_OCFG_SFTRSTMASK; - dwc3_writel(dwc->regs, DWC3_OCFG, reg); + dwc3_writel(dwc, DWC3_OCFG, reg); =20 /* Disable hibernation for simplicity */ - reg =3D dwc3_readl(dwc->regs, DWC3_GCTL); + reg =3D dwc3_readl(dwc, DWC3_GCTL); reg &=3D ~DWC3_GCTL_GBLHIBERNATIONEN; - dwc3_writel(dwc->regs, DWC3_GCTL, reg); + dwc3_writel(dwc, DWC3_GCTL, reg); =20 /* * Initialize OTG registers as per * Figure 11-4 OTG Driver Overall Programming Flow */ /* OCFG.SRPCap =3D 0, OCFG.HNPCap =3D 0 */ - reg =3D dwc3_readl(dwc->regs, DWC3_OCFG); + reg =3D dwc3_readl(dwc, DWC3_OCFG); reg &=3D ~(DWC3_OCFG_SRPCAP | DWC3_OCFG_HNPCAP); - dwc3_writel(dwc->regs, DWC3_OCFG, reg); + dwc3_writel(dwc, DWC3_OCFG, reg); /* OEVT =3D FFFF */ dwc3_otg_clear_events(dwc); /* OEVTEN =3D 0 */ @@ -127,11 +127,11 @@ static void dwc3_otgregs_init(struct dwc3 *dwc) * OCTL.PeriMode =3D 1, OCTL.DevSetHNPEn =3D 0, OCTL.HstSetHNPEn =3D 0, * OCTL.HNPReq =3D 0 */ - reg =3D dwc3_readl(dwc->regs, DWC3_OCTL); + reg =3D dwc3_readl(dwc, DWC3_OCTL); reg |=3D DWC3_OCTL_PERIMODE; reg &=3D ~(DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HSTSETHNPEN | DWC3_OCTL_HNPREQ); - dwc3_writel(dwc->regs, DWC3_OCTL, reg); + dwc3_writel(dwc, DWC3_OCTL, reg); } =20 static int dwc3_otg_get_irq(struct dwc3 *dwc) @@ -175,9 +175,9 @@ void dwc3_otg_init(struct dwc3 *dwc) /* GCTL.PrtCapDir=3D2'b11 */ dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_OTG, true); /* GUSB2PHYCFG0.SusPHY=3D0 */ - reg =3D dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + reg =3D dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0)); reg &=3D ~DWC3_GUSB2PHYCFG_SUSPHY; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + dwc3_writel(dwc, DWC3_GUSB2PHYCFG(0), reg); =20 /* Initialize OTG registers */ dwc3_otgregs_init(dwc); @@ -203,17 +203,17 @@ void dwc3_otg_host_init(struct dwc3 *dwc) * OCTL.PeriMode=3D0, OCTL.TermSelDLPulse =3D 0, * OCTL.DevSetHNPEn =3D 0, OCTL.HstSetHNPEn =3D 0 */ - reg =3D dwc3_readl(dwc->regs, DWC3_OCTL); + reg =3D dwc3_readl(dwc, DWC3_OCTL); reg &=3D ~(DWC3_OCTL_PERIMODE | DWC3_OCTL_TERMSELIDPULSE | DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HSTSETHNPEN); - dwc3_writel(dwc->regs, DWC3_OCTL, reg); + dwc3_writel(dwc, DWC3_OCTL, reg); =20 /* * OCFG.DisPrtPwrCutoff =3D 0/1 */ - reg =3D dwc3_readl(dwc->regs, DWC3_OCFG); + reg =3D dwc3_readl(dwc, DWC3_OCFG); reg &=3D ~DWC3_OCFG_DISPWRCUTTOFF; - dwc3_writel(dwc->regs, DWC3_OCFG, reg); + dwc3_writel(dwc, DWC3_OCFG, reg); =20 /* * OCFG.SRPCap =3D 1, OCFG.HNPCap =3D GHWPARAMS6.HNP_CAP @@ -229,15 +229,15 @@ void dwc3_otg_host_init(struct dwc3 *dwc) =20 /* GUSB2PHYCFG.ULPIAutoRes =3D 1/0, GUSB2PHYCFG.SusPHY =3D 1 */ if (!dwc->dis_u2_susphy_quirk) { - reg =3D dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + reg =3D dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0)); reg |=3D DWC3_GUSB2PHYCFG_SUSPHY; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + dwc3_writel(dwc, DWC3_GUSB2PHYCFG(0), reg); } =20 /* Set Port Power to enable VBUS: OCTL.PrtPwrCtl =3D 1 */ - reg =3D dwc3_readl(dwc->regs, DWC3_OCTL); + reg =3D dwc3_readl(dwc, DWC3_OCTL); reg |=3D DWC3_OCTL_PRTPWRCTL; - dwc3_writel(dwc->regs, DWC3_OCTL, reg); + dwc3_writel(dwc, DWC3_OCTL, reg); } =20 /* should be called after Host controller driver is stopped */ @@ -258,9 +258,9 @@ static void dwc3_otg_host_exit(struct dwc3 *dwc) */ =20 /* OCTL.HstSetHNPEn =3D 0, OCTL.PrtPwrCtl=3D0 */ - reg =3D dwc3_readl(dwc->regs, DWC3_OCTL); + reg =3D dwc3_readl(dwc, DWC3_OCTL); reg &=3D ~(DWC3_OCTL_HSTSETHNPEN | DWC3_OCTL_PRTPWRCTL); - dwc3_writel(dwc->regs, DWC3_OCTL, reg); + dwc3_writel(dwc, DWC3_OCTL, reg); } =20 /* should be called before the gadget controller driver is started */ @@ -274,27 +274,27 @@ static void dwc3_otg_device_init(struct dwc3 *dwc) * OCFG.HNPCap =3D GHWPARAMS6.HNP_CAP, OCFG.SRPCap =3D 1 * but we keep them 0 for simple dual-role operation. */ - reg =3D dwc3_readl(dwc->regs, DWC3_OCFG); + reg =3D dwc3_readl(dwc, DWC3_OCFG); /* OCFG.OTGSftRstMsk =3D 0/1 */ reg |=3D DWC3_OCFG_SFTRSTMASK; - dwc3_writel(dwc->regs, DWC3_OCFG, reg); + dwc3_writel(dwc, DWC3_OCFG, reg); /* * OCTL.PeriMode =3D 1 * OCTL.TermSelDLPulse =3D 0/1, OCTL.HNPReq =3D 0 * OCTL.DevSetHNPEn =3D 0, OCTL.HstSetHNPEn =3D 0 */ - reg =3D dwc3_readl(dwc->regs, DWC3_OCTL); + reg =3D dwc3_readl(dwc, DWC3_OCTL); reg |=3D DWC3_OCTL_PERIMODE; reg &=3D ~(DWC3_OCTL_TERMSELIDPULSE | DWC3_OCTL_HNPREQ | DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HSTSETHNPEN); - dwc3_writel(dwc->regs, DWC3_OCTL, reg); + dwc3_writel(dwc, DWC3_OCTL, reg); /* OEVTEN.OTGBDevSesVldDetEvntEn =3D 1 */ dwc3_otg_enable_events(dwc, DWC3_OEVTEN_BDEVSESSVLDDETEN); /* GUSB2PHYCFG.ULPIAutoRes =3D 0, GUSB2PHYCFG0.SusPHY =3D 1 */ if (!dwc->dis_u2_susphy_quirk) { - reg =3D dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + reg =3D dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0)); reg |=3D DWC3_GUSB2PHYCFG_SUSPHY; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + dwc3_writel(dwc, DWC3_GUSB2PHYCFG(0), reg); } /* GCTL.GblHibernationEn =3D 0. Already 0. */ } @@ -319,10 +319,10 @@ static void dwc3_otg_device_exit(struct dwc3 *dwc) DWC3_OEVTEN_BDEVBHOSTENDEN); =20 /* OCTL.DevSetHNPEn =3D 0, OCTL.HNPReq =3D 0, OCTL.PeriMode=3D1 */ - reg =3D dwc3_readl(dwc->regs, DWC3_OCTL); + reg =3D dwc3_readl(dwc, DWC3_OCTL); reg &=3D ~(DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HNPREQ); reg |=3D DWC3_OCTL_PERIMODE; - dwc3_writel(dwc->regs, DWC3_OCTL, reg); + dwc3_writel(dwc, DWC3_OCTL, reg); } =20 void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) @@ -341,7 +341,7 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idst= atus) return; =20 if (!ignore_idstatus) { - reg =3D dwc3_readl(dwc->regs, DWC3_OSTS); + reg =3D dwc3_readl(dwc, DWC3_OSTS); id =3D !!(reg & DWC3_OSTS_CONIDSTS); =20 dwc->desired_otg_role =3D id ? DWC3_OTG_ROLE_DEVICE : diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index e0bad5708664..a8ff8db610d3 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c @@ -361,7 +361,7 @@ static int dwc3_ep0_handle_status(struct dwc3 *dwc, =20 if ((dwc->speed =3D=3D DWC3_DSTS_SUPERSPEED) || (dwc->speed =3D=3D DWC3_DSTS_SUPERSPEED_PLUS)) { - reg =3D dwc3_readl(dwc->regs, DWC3_DCTL); + reg =3D dwc3_readl(dwc, DWC3_DCTL); if (reg & DWC3_DCTL_INITU1ENA) usb_status |=3D 1 << USB_DEV_STAT_U1_ENABLED; if (reg & DWC3_DCTL_INITU2ENA) @@ -417,12 +417,12 @@ static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum = usb_device_state state, if (set && dwc->dis_u1_entry_quirk) return -EINVAL; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DCTL); + reg =3D dwc3_readl(dwc, DWC3_DCTL); if (set) reg |=3D DWC3_DCTL_INITU1ENA; else reg &=3D ~DWC3_DCTL_INITU1ENA; - dwc3_writel(dwc->regs, DWC3_DCTL, reg); + dwc3_writel(dwc, DWC3_DCTL, reg); =20 return 0; } @@ -441,12 +441,12 @@ static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum = usb_device_state state, if (set && dwc->dis_u2_entry_quirk) return -EINVAL; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DCTL); + reg =3D dwc3_readl(dwc, DWC3_DCTL); if (set) reg |=3D DWC3_DCTL_INITU2ENA; else reg &=3D ~DWC3_DCTL_INITU2ENA; - dwc3_writel(dwc->regs, DWC3_DCTL, reg); + dwc3_writel(dwc, DWC3_DCTL, reg); =20 return 0; } @@ -612,10 +612,10 @@ static int dwc3_ep0_set_address(struct dwc3 *dwc, str= uct usb_ctrlrequest *ctrl) return -EINVAL; } =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DCFG); + reg =3D dwc3_readl(dwc, DWC3_DCFG); reg &=3D ~(DWC3_DCFG_DEVADDR_MASK); reg |=3D DWC3_DCFG_DEVADDR(addr); - dwc3_writel(dwc->regs, DWC3_DCFG, reg); + dwc3_writel(dwc, DWC3_DCFG, reg); =20 if (addr) usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS); @@ -672,12 +672,12 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, stru= ct usb_ctrlrequest *ctrl) * Enable transition to U1/U2 state when * nothing is pending from application. */ - reg =3D dwc3_readl(dwc->regs, DWC3_DCTL); + reg =3D dwc3_readl(dwc, DWC3_DCTL); if (!dwc->dis_u1_entry_quirk) reg |=3D DWC3_DCTL_ACCEPTU1ENA; if (!dwc->dis_u2_entry_quirk) reg |=3D DWC3_DCTL_ACCEPTU2ENA; - dwc3_writel(dwc->regs, DWC3_DCTL, reg); + dwc3_writel(dwc, DWC3_DCTL, reg); } break; =20 @@ -717,7 +717,7 @@ static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, st= ruct usb_request *req) dwc->u2sel =3D le16_to_cpu(timing.u2sel); dwc->u2pel =3D le16_to_cpu(timing.u2pel); =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DCTL); + reg =3D dwc3_readl(dwc, DWC3_DCTL); if (reg & DWC3_DCTL_INITU2ENA) param =3D dwc->u2pel; if (reg & DWC3_DCTL_INITU1ENA) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index f08560af1701..a85ba5ca7912 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -42,7 +42,7 @@ int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) { u32 reg; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DCTL); + reg =3D dwc3_readl(dwc, DWC3_DCTL); reg &=3D ~DWC3_DCTL_TSTCTRL_MASK; =20 switch (mode) { @@ -73,7 +73,7 @@ int dwc3_gadget_get_link_state(struct dwc3 *dwc) { u32 reg; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DSTS); + reg =3D dwc3_readl(dwc, DWC3_DSTS); =20 return DWC3_DSTS_USBLNKST(reg); } @@ -97,7 +97,7 @@ int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc= 3_link_state state) */ if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) { while (--retries) { - reg =3D dwc3_readl(dwc->regs, DWC3_DSTS); + reg =3D dwc3_readl(dwc, DWC3_DSTS); if (reg & DWC3_DSTS_DCNRD) udelay(5); else @@ -108,15 +108,15 @@ int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum= dwc3_link_state state) return -ETIMEDOUT; } =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DCTL); + reg =3D dwc3_readl(dwc, DWC3_DCTL); reg &=3D ~DWC3_DCTL_ULSTCHNGREQ_MASK; =20 /* set no action before sending new link state change */ - dwc3_writel(dwc->regs, DWC3_DCTL, reg); + dwc3_writel(dwc, DWC3_DCTL, reg); =20 /* set requested state */ reg |=3D DWC3_DCTL_ULSTCHNGREQ(state); - dwc3_writel(dwc->regs, DWC3_DCTL, reg); + dwc3_writel(dwc, DWC3_DCTL, reg); =20 /* * The following code is racy when called from dwc3_gadget_wakeup, @@ -128,7 +128,7 @@ int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum d= wc3_link_state state) /* wait for a change in DSTS */ retries =3D 10000; while (--retries) { - reg =3D dwc3_readl(dwc->regs, DWC3_DSTS); + reg =3D dwc3_readl(dwc, DWC3_DSTS); =20 if (DWC3_DSTS_USBLNKST(reg) =3D=3D state) return 0; @@ -260,11 +260,11 @@ int dwc3_send_gadget_generic_command(struct dwc3 *dwc= , unsigned int cmd, int ret =3D 0; u32 reg; =20 - dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); - dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); + dwc3_writel(dwc, DWC3_DGCMDPAR, param); + dwc3_writel(dwc, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); =20 do { - reg =3D dwc3_readl(dwc->regs, DWC3_DGCMD); + reg =3D dwc3_readl(dwc, DWC3_DGCMD); if (!(reg & DWC3_DGCMD_CMDACT)) { status =3D DWC3_DGCMD_STATUS(reg); if (status) @@ -334,7 +334,7 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsign= ed int cmd, */ if (dwc->gadget->speed <=3D USB_SPEED_HIGH || DWC3_DEPCMD_CMD(cmd) =3D=3D DWC3_DEPCMD_ENDTRANSFER) { - reg =3D dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + reg =3D dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0)); if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) { saved_config |=3D DWC3_GUSB2PHYCFG_SUSPHY; reg &=3D ~DWC3_GUSB2PHYCFG_SUSPHY; @@ -346,7 +346,7 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsign= ed int cmd, } =20 if (saved_config) - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + dwc3_writel(dwc, DWC3_GUSB2PHYCFG(0), reg); } =20 /* @@ -356,9 +356,9 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsign= ed int cmd, * improve performance. */ if (DWC3_DEPCMD_CMD(cmd) !=3D DWC3_DEPCMD_UPDATETRANSFER) { - dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(epnum), params->param0); - dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(epnum), params->param1); - dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(epnum), params->param2); + dwc3_writel(dwc, DWC3_DEPCMDPAR0(epnum), params->param0); + dwc3_writel(dwc, DWC3_DEPCMDPAR1(epnum), params->param1); + dwc3_writel(dwc, DWC3_DEPCMDPAR2(epnum), params->param2); } =20 /* @@ -382,7 +382,7 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsign= ed int cmd, else cmd |=3D DWC3_DEPCMD_CMDACT; =20 - dwc3_writel(dwc->regs, DWC3_DEPCMD(epnum), cmd); + dwc3_writel(dwc, DWC3_DEPCMD(epnum), cmd); =20 if (!(cmd & DWC3_DEPCMD_CMDACT) || (DWC3_DEPCMD_CMD(cmd) =3D=3D DWC3_DEPCMD_ENDTRANSFER && @@ -392,7 +392,7 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsign= ed int cmd, } =20 do { - reg =3D dwc3_readl(dwc->regs, DWC3_DEPCMD(epnum)); + reg =3D dwc3_readl(dwc, DWC3_DEPCMD(epnum)); if (!(reg & DWC3_DEPCMD_CMDACT)) { cmd_status =3D DWC3_DEPCMD_STATUS(reg); =20 @@ -448,9 +448,9 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsign= ed int cmd, mdelay(1); =20 if (saved_config) { - reg =3D dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + reg =3D dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0)); reg |=3D saved_config; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + dwc3_writel(dwc, DWC3_GUSB2PHYCFG(0), reg); } =20 return ret; @@ -727,7 +727,7 @@ static int dwc3_gadget_calc_ram_depth(struct dwc3 *dwc) u32 reg; =20 /* Check if TXFIFOs start at non-zero addr */ - reg =3D dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0)); + reg =3D dwc3_readl(dwc, DWC3_GTXFIFOSIZ(0)); fifo_0_start =3D DWC3_GTXFIFOSIZ_TXFSTADDR(reg); =20 ram_depth -=3D (fifo_0_start >> 16); @@ -755,7 +755,7 @@ void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc) =20 /* Read ep0IN related TXFIFO size */ dep =3D dwc->eps[1]; - size =3D dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0)); + size =3D dwc3_readl(dwc, DWC3_GTXFIFOSIZ(0)); if (DWC3_IP_IS(DWC3)) fifo_depth =3D DWC3_GTXFIFOSIZ_TXFDEP(size); else @@ -770,10 +770,10 @@ void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc) =20 /* Don't change TXFRAMNUM on usb31 version */ size =3D DWC3_IP_IS(DWC3) ? 0 : - dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) & + dwc3_readl(dwc, DWC3_GTXFIFOSIZ(num >> 1)) & DWC31_GTXFIFOSIZ_TXFRAMNUM; =20 - dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size); + dwc3_writel(dwc, DWC3_GTXFIFOSIZ(num >> 1), size); dep->flags &=3D ~DWC3_EP_TXFIFO_RESIZED; } dwc->num_ep_resized =3D 0; @@ -876,7 +876,7 @@ static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *= dep) fifo_size++; =20 /* Check if TXFIFOs start at non-zero addr */ - tmp =3D dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0)); + tmp =3D dwc3_readl(dwc, DWC3_GTXFIFOSIZ(0)); fifo_0_start =3D DWC3_GTXFIFOSIZ_TXFSTADDR(tmp); =20 fifo_size |=3D (fifo_0_start + (dwc->last_fifo_depth << 16)); @@ -899,7 +899,7 @@ static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *= dep) return -ENOMEM; } =20 - dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size); + dwc3_writel(dwc, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size); dep->flags |=3D DWC3_EP_TXFIFO_RESIZED; dwc->num_ep_resized++; =20 @@ -943,9 +943,9 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,= unsigned int action) dep->type =3D usb_endpoint_type(desc); dep->flags |=3D DWC3_EP_ENABLED; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DALEPENA); + reg =3D dwc3_readl(dwc, DWC3_DALEPENA); reg |=3D DWC3_DALEPENA_EP(dep->number); - dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); + dwc3_writel(dwc, DWC3_DALEPENA, reg); =20 dep->trb_dequeue =3D 0; dep->trb_enqueue =3D 0; @@ -1080,9 +1080,9 @@ static int __dwc3_gadget_ep_disable(struct dwc3_ep *d= ep) if (dep->flags & DWC3_EP_STALL) __dwc3_gadget_ep_set_halt(dep, 0, false); =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DALEPENA); + reg =3D dwc3_readl(dwc, DWC3_DALEPENA); reg &=3D ~DWC3_DALEPENA_EP(dep->number); - dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); + dwc3_writel(dwc, DWC3_DALEPENA, reg); =20 dwc3_remove_requests(dwc, dep, -ESHUTDOWN); =20 @@ -1743,7 +1743,7 @@ static int __dwc3_gadget_get_frame(struct dwc3 *dwc) { u32 reg; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DSTS); + reg =3D dwc3_readl(dwc, DWC3_DSTS); return DWC3_DSTS_SOFFN(reg); } =20 @@ -2351,13 +2351,13 @@ static void dwc3_gadget_enable_linksts_evts(struct = dwc3 *dwc, bool set) if (DWC3_VER_IS_PRIOR(DWC3, 250A)) return; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DEVTEN); + reg =3D dwc3_readl(dwc, DWC3_DEVTEN); if (set) reg |=3D DWC3_DEVTEN_ULSTCNGEN; else reg &=3D ~DWC3_DEVTEN_ULSTCNGEN; =20 - dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); + dwc3_writel(dwc, DWC3_DEVTEN, reg); } =20 static int dwc3_gadget_get_frame(struct usb_gadget *g) @@ -2380,7 +2380,7 @@ static int __dwc3_gadget_wakeup(struct dwc3 *dwc) * * We can check that via USB Link State bits in DSTS register. */ - reg =3D dwc3_readl(dwc->regs, DWC3_DSTS); + reg =3D dwc3_readl(dwc, DWC3_DSTS); =20 link_state =3D DWC3_DSTS_USBLNKST(reg); =20 @@ -2408,9 +2408,9 @@ static int __dwc3_gadget_wakeup(struct dwc3 *dwc) /* Recent versions do this automatically */ if (DWC3_VER_IS_PRIOR(DWC3, 194A)) { /* write zeroes to Link Change Request */ - reg =3D dwc3_readl(dwc->regs, DWC3_DCTL); + reg =3D dwc3_readl(dwc, DWC3_DCTL); reg &=3D ~DWC3_DCTL_ULSTCHNGREQ_MASK; - dwc3_writel(dwc->regs, DWC3_DCTL, reg); + dwc3_writel(dwc, DWC3_DCTL, reg); } =20 /* @@ -2530,7 +2530,7 @@ static void __dwc3_gadget_set_ssp_rate(struct dwc3 *d= wc) if (ssp_rate =3D=3D USB_SSP_GEN_UNKNOWN) ssp_rate =3D dwc->max_ssp_rate; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DCFG); + reg =3D dwc3_readl(dwc, DWC3_DCFG); reg &=3D ~DWC3_DCFG_SPEED_MASK; reg &=3D ~DWC3_DCFG_NUMLANES(~0); =20 @@ -2543,7 +2543,7 @@ static void __dwc3_gadget_set_ssp_rate(struct dwc3 *d= wc) dwc->max_ssp_rate !=3D USB_SSP_GEN_2x1) reg |=3D DWC3_DCFG_NUMLANES(1); =20 - dwc3_writel(dwc->regs, DWC3_DCFG, reg); + dwc3_writel(dwc, DWC3_DCFG, reg); } =20 static void __dwc3_gadget_set_speed(struct dwc3 *dwc) @@ -2561,7 +2561,7 @@ static void __dwc3_gadget_set_speed(struct dwc3 *dwc) return; } =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DCFG); + reg =3D dwc3_readl(dwc, DWC3_DCFG); reg &=3D ~(DWC3_DCFG_SPEED_MASK); =20 /* @@ -2612,7 +2612,7 @@ static void __dwc3_gadget_set_speed(struct dwc3 *dwc) speed < USB_SPEED_SUPER_PLUS) reg &=3D ~DWC3_DCFG_NUMLANES(~0); =20 - dwc3_writel(dwc->regs, DWC3_DCFG, reg); + dwc3_writel(dwc, DWC3_DCFG, reg); } =20 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on) @@ -2637,7 +2637,7 @@ static int dwc3_gadget_run_stop(struct dwc3 *dwc, int= is_on) * mentioned in the dwc3 programming guide. It has been tested on an * Exynos platforms. */ - reg =3D dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + reg =3D dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0)); if (reg & DWC3_GUSB2PHYCFG_SUSPHY) { saved_config |=3D DWC3_GUSB2PHYCFG_SUSPHY; reg &=3D ~DWC3_GUSB2PHYCFG_SUSPHY; @@ -2649,9 +2649,9 @@ static int dwc3_gadget_run_stop(struct dwc3 *dwc, int= is_on) } =20 if (saved_config) - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + dwc3_writel(dwc, DWC3_GUSB2PHYCFG(0), reg); =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DCTL); + reg =3D dwc3_readl(dwc, DWC3_DCTL); if (is_on) { if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) { reg &=3D ~DWC3_DCTL_TRGTULST_MASK; @@ -2675,14 +2675,14 @@ static int dwc3_gadget_run_stop(struct dwc3 *dwc, i= nt is_on) =20 do { usleep_range(1000, 2000); - reg =3D dwc3_readl(dwc->regs, DWC3_DSTS); + reg =3D dwc3_readl(dwc, DWC3_DSTS); reg &=3D DWC3_DSTS_DEVCTRLHLT; } while (--timeout && !(!is_on ^ !reg)); =20 if (saved_config) { - reg =3D dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + reg =3D dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0)); reg |=3D saved_config; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + dwc3_writel(dwc, DWC3_GUSB2PHYCFG(0), reg); } =20 if (!timeout) @@ -2858,13 +2858,13 @@ static void dwc3_gadget_enable_irq(struct dwc3 *dwc) if (!DWC3_VER_IS_PRIOR(DWC3, 230A)) reg |=3D DWC3_DEVTEN_U3L2L1SUSPEN; =20 - dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); + dwc3_writel(dwc, DWC3_DEVTEN, reg); } =20 static void dwc3_gadget_disable_irq(struct dwc3 *dwc) { /* mask all interrupts */ - dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); + dwc3_writel(dwc, DWC3_DEVTEN, 0x00); } =20 static irqreturn_t dwc3_interrupt(int irq, void *_dwc); @@ -2905,10 +2905,10 @@ static void dwc3_gadget_setup_nump(struct dwc3 *dwc) nump =3D min_t(u32, nump, 16); =20 /* update NumP */ - reg =3D dwc3_readl(dwc->regs, DWC3_DCFG); + reg =3D dwc3_readl(dwc, DWC3_DCFG); reg &=3D ~DWC3_DCFG_NUMP_MASK; reg |=3D nump << DWC3_DCFG_NUMP_SHIFT; - dwc3_writel(dwc->regs, DWC3_DCFG, reg); + dwc3_writel(dwc, DWC3_DCFG, reg); } =20 static int __dwc3_gadget_start(struct dwc3 *dwc) @@ -2922,10 +2922,10 @@ static int __dwc3_gadget_start(struct dwc3 *dwc) * the core supports IMOD, disable it. */ if (dwc->imod_interval) { - dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); - dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); + dwc3_writel(dwc, DWC3_DEV_IMOD(0), dwc->imod_interval); + dwc3_writel(dwc, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); } else if (dwc3_has_imod(dwc)) { - dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0); + dwc3_writel(dwc, DWC3_DEV_IMOD(0), 0); } =20 /* @@ -2935,13 +2935,13 @@ static int __dwc3_gadget_start(struct dwc3 *dwc) * This way, we maximize the chances that we'll be able to get several * bursts of data without going through any sort of endpoint throttling. */ - reg =3D dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); + reg =3D dwc3_readl(dwc, DWC3_GRXTHRCFG); if (DWC3_IP_IS(DWC3)) reg &=3D ~DWC3_GRXTHRCFG_PKTCNTSEL; else reg &=3D ~DWC31_GRXTHRCFG_PKTCNTSEL; =20 - dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); + dwc3_writel(dwc, DWC3_GRXTHRCFG, reg); =20 dwc3_gadget_setup_nump(dwc); =20 @@ -2952,15 +2952,15 @@ static int __dwc3_gadget_start(struct dwc3 *dwc) * ACK with NumP=3D0 and PP=3D0 (for IN direction). This slightly improves * the stream performance. */ - reg =3D dwc3_readl(dwc->regs, DWC3_DCFG); + reg =3D dwc3_readl(dwc, DWC3_DCFG); reg |=3D DWC3_DCFG_IGNSTRMPP; - dwc3_writel(dwc->regs, DWC3_DCFG, reg); + dwc3_writel(dwc, DWC3_DCFG, reg); =20 /* Enable MST by default if the device is capable of MST */ if (DWC3_MST_CAPABLE(&dwc->hwparams)) { - reg =3D dwc3_readl(dwc->regs, DWC3_DCFG1); + reg =3D dwc3_readl(dwc, DWC3_DCFG1); reg &=3D ~DWC3_DCFG1_DIS_MST_ENH; - dwc3_writel(dwc->regs, DWC3_DCFG1, reg); + dwc3_writel(dwc, DWC3_DCFG1, reg); } =20 /* Start with SuperSpeed Default */ @@ -3240,7 +3240,7 @@ static int dwc3_gadget_init_in_endpoint(struct dwc3_e= p *dep) /* MDWIDTH is represented in bits, we need it in bytes */ mdwidth /=3D 8; =20 - size =3D dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1)); + size =3D dwc3_readl(dwc, DWC3_GTXFIFOSIZ(dep->number >> 1)); if (DWC3_IP_IS(DWC3)) size =3D DWC3_GTXFIFOSIZ_TXFDEP(size); else @@ -3289,7 +3289,7 @@ static int dwc3_gadget_init_out_endpoint(struct dwc3_= ep *dep) mdwidth /=3D 8; =20 /* All OUT endpoints share a single RxFIFO space */ - size =3D dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0)); + size =3D dwc3_readl(dwc, DWC3_GRXFIFOSIZ(0)); if (DWC3_IP_IS(DWC3)) size =3D DWC3_GRXFIFOSIZ_RXFDEP(size); else @@ -3742,9 +3742,9 @@ static bool dwc3_gadget_endpoint_trbs_complete(struct= dwc3_ep *dep, return no_started_trb; } =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DCTL); + reg =3D dwc3_readl(dwc, DWC3_DCTL); reg |=3D dwc->u1u2; - dwc3_writel(dwc->regs, DWC3_DCTL, reg); + dwc3_writel(dwc, DWC3_DCTL, reg); =20 dwc->u1u2 =3D 0; } @@ -4074,7 +4074,7 @@ static void dwc3_gadget_disconnect_interrupt(struct d= wc3 *dwc) =20 dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET); =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DCTL); + reg =3D dwc3_readl(dwc, DWC3_DCTL); reg &=3D ~DWC3_DCTL_INITU1ENA; reg &=3D ~DWC3_DCTL_INITU2ENA; dwc3_gadget_dctl_write_safe(dwc, reg); @@ -4163,7 +4163,7 @@ static void dwc3_gadget_reset_interrupt(struct dwc3 *= dwc) dwc3_stop_active_transfers(dwc); dwc->connected =3D true; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DCTL); + reg =3D dwc3_readl(dwc, DWC3_DCTL); reg &=3D ~DWC3_DCTL_TSTCTRL_MASK; dwc3_gadget_dctl_write_safe(dwc, reg); dwc->test_mode =3D false; @@ -4172,9 +4172,9 @@ static void dwc3_gadget_reset_interrupt(struct dwc3 *= dwc) dwc3_clear_stall_all_ep(dwc); =20 /* Reset device address to zero */ - reg =3D dwc3_readl(dwc->regs, DWC3_DCFG); + reg =3D dwc3_readl(dwc, DWC3_DCFG); reg &=3D ~(DWC3_DCFG_DEVADDR_MASK); - dwc3_writel(dwc->regs, DWC3_DCFG, reg); + dwc3_writel(dwc, DWC3_DCFG, reg); } =20 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) @@ -4188,7 +4188,7 @@ static void dwc3_gadget_conndone_interrupt(struct dwc= 3 *dwc) if (!dwc->softconnect) return; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DSTS); + reg =3D dwc3_readl(dwc, DWC3_DSTS); speed =3D reg & DWC3_DSTS_CONNECTSPD; dwc->speed =3D speed; =20 @@ -4263,11 +4263,11 @@ static void dwc3_gadget_conndone_interrupt(struct d= wc3 *dwc) !dwc->usb2_gadget_lpm_disable && (speed !=3D DWC3_DSTS_SUPERSPEED) && (speed !=3D DWC3_DSTS_SUPERSPEED_PLUS)) { - reg =3D dwc3_readl(dwc->regs, DWC3_DCFG); + reg =3D dwc3_readl(dwc, DWC3_DCFG); reg |=3D DWC3_DCFG_LPM_CAP; - dwc3_writel(dwc->regs, DWC3_DCFG, reg); + dwc3_writel(dwc, DWC3_DCFG, reg); =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DCTL); + reg =3D dwc3_readl(dwc, DWC3_DCTL); reg &=3D ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); =20 reg |=3D DWC3_DCTL_HIRD_THRES(dwc->hird_threshold | @@ -4290,12 +4290,12 @@ static void dwc3_gadget_conndone_interrupt(struct d= wc3 *dwc) dwc3_gadget_dctl_write_safe(dwc, reg); } else { if (dwc->usb2_gadget_lpm_disable) { - reg =3D dwc3_readl(dwc->regs, DWC3_DCFG); + reg =3D dwc3_readl(dwc, DWC3_DCFG); reg &=3D ~DWC3_DCFG_LPM_CAP; - dwc3_writel(dwc->regs, DWC3_DCFG, reg); + dwc3_writel(dwc, DWC3_DCFG, reg); } =20 - reg =3D dwc3_readl(dwc->regs, DWC3_DCTL); + reg =3D dwc3_readl(dwc, DWC3_DCTL); reg &=3D ~DWC3_DCTL_HIRD_THRES_MASK; dwc3_gadget_dctl_write_safe(dwc, reg); } @@ -4401,7 +4401,7 @@ static void dwc3_gadget_linksts_change_interrupt(stru= ct dwc3 *dwc, switch (dwc->link_state) { case DWC3_LINK_STATE_U1: case DWC3_LINK_STATE_U2: - reg =3D dwc3_readl(dwc->regs, DWC3_DCTL); + reg =3D dwc3_readl(dwc, DWC3_DCTL); u1u2 =3D reg & (DWC3_DCTL_INITU2ENA | DWC3_DCTL_ACCEPTU2ENA | DWC3_DCTL_INITU1ENA @@ -4558,7 +4558,7 @@ static irqreturn_t dwc3_process_event_buf(struct dwc3= _event_buffer *evt) ret =3D IRQ_HANDLED; =20 /* Unmask interrupt */ - dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), + dwc3_writel(dwc, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_SIZE(evt->length)); =20 evt->flags &=3D ~DWC3_EVENT_PENDING; @@ -4569,8 +4569,8 @@ static irqreturn_t dwc3_process_event_buf(struct dwc3= _event_buffer *evt) wmb(); =20 if (dwc->imod_interval) { - dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); - dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); + dwc3_writel(dwc, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); + dwc3_writel(dwc, DWC3_DEV_IMOD(0), dwc->imod_interval); } =20 return ret; @@ -4619,7 +4619,7 @@ static irqreturn_t dwc3_check_event_buf(struct dwc3_e= vent_buffer *evt) if (evt->flags & DWC3_EVENT_PENDING) return IRQ_HANDLED; =20 - count =3D dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); + count =3D dwc3_readl(dwc, DWC3_GEVNTCOUNT(0)); count &=3D DWC3_GEVNTCOUNT_MASK; if (!count) return IRQ_NONE; @@ -4634,7 +4634,7 @@ static irqreturn_t dwc3_check_event_buf(struct dwc3_e= vent_buffer *evt) evt->flags |=3D DWC3_EVENT_PENDING; =20 /* Mask interrupt */ - dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), + dwc3_writel(dwc, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK | DWC3_GEVNTSIZ_SIZE(evt->length)); =20 amount =3D min(count, evt->length - evt->lpos); @@ -4643,7 +4643,7 @@ static irqreturn_t dwc3_check_event_buf(struct dwc3_e= vent_buffer *evt) if (amount < count) memcpy(evt->cache, evt->buf, count - amount); =20 - dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count); + dwc3_writel(dwc, DWC3_GEVNTCOUNT(0), count); =20 return IRQ_WAKE_THREAD; } diff --git a/drivers/usb/dwc3/gadget.h b/drivers/usb/dwc3/gadget.h index c3aa9638b7a5..45f113b3c146 100644 --- a/drivers/usb/dwc3/gadget.h +++ b/drivers/usb/dwc3/gadget.h @@ -132,7 +132,7 @@ static inline void dwc3_gadget_ep_get_transfer_index(st= ruct dwc3_ep *dep) { u32 res_id; =20 - res_id =3D dwc3_readl(dep->dwc->regs, DWC3_DEPCMD(dep->number)); + res_id =3D dwc3_readl(dep->dwc, DWC3_DEPCMD(dep->number)); dep->resource_index =3D DWC3_DEPCMD_GET_RSC_IDX(res_id); } =20 @@ -147,7 +147,7 @@ static inline void dwc3_gadget_ep_get_transfer_index(st= ruct dwc3_ep *dep) static inline void dwc3_gadget_dctl_write_safe(struct dwc3 *dwc, u32 value) { value &=3D ~DWC3_DCTL_ULSTCHNGREQ_MASK; - dwc3_writel(dwc->regs, DWC3_DCTL, value); + dwc3_writel(dwc, DWC3_DCTL, value); } =20 #endif /* __DRIVERS_USB_DWC3_GADGET_H */ diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h index 1e96ea339d48..7dd0c1e0cf74 100644 --- a/drivers/usb/dwc3/io.h +++ b/drivers/usb/dwc3/io.h @@ -16,9 +16,10 @@ #include "debug.h" #include "core.h" =20 -static inline u32 dwc3_readl(void __iomem *base, u32 offset) +static inline u32 dwc3_readl(struct dwc3 *dwc, u32 offset) { u32 value; + void __iomem *base =3D dwc->regs; =20 /* * We requested the mem region starting from the Globals address @@ -37,8 +38,10 @@ static inline u32 dwc3_readl(void __iomem *base, u32 off= set) return value; } =20 -static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value) +static inline void dwc3_writel(struct dwc3 *dwc, u32 offset, u32 value) { + void __iomem *base =3D dwc->regs; + /* * We requested the mem region starting from the Globals address * space, see dwc3_probe in core.c. diff --git a/drivers/usb/dwc3/ulpi.c b/drivers/usb/dwc3/ulpi.c index f23f4c9a557e..57daad15f502 100644 --- a/drivers/usb/dwc3/ulpi.c +++ b/drivers/usb/dwc3/ulpi.c @@ -33,13 +33,13 @@ static int dwc3_ulpi_busyloop(struct dwc3 *dwc, u8 addr= , bool read) if (read) ns +=3D DWC3_ULPI_BASE_DELAY; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + reg =3D dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0)); if (reg & DWC3_GUSB2PHYCFG_SUSPHY) usleep_range(1000, 1200); =20 while (count--) { ndelay(ns); - reg =3D dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0)); + reg =3D dwc3_readl(dwc, DWC3_GUSB2PHYACC(0)); if (reg & DWC3_GUSB2PHYACC_DONE) return 0; cpu_relax(); @@ -55,13 +55,13 @@ static int dwc3_ulpi_read(struct device *dev, u8 addr) int ret; =20 reg =3D DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr); - dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg); + dwc3_writel(dwc, DWC3_GUSB2PHYACC(0), reg); =20 ret =3D dwc3_ulpi_busyloop(dwc, addr, true); if (ret) return ret; =20 - reg =3D dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0)); + reg =3D dwc3_readl(dwc, DWC3_GUSB2PHYACC(0)); =20 return DWC3_GUSB2PHYACC_DATA(reg); } @@ -73,7 +73,7 @@ static int dwc3_ulpi_write(struct device *dev, u8 addr, u= 8 val) =20 reg =3D DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr); reg |=3D DWC3_GUSB2PHYACC_WRITE | val; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg); + dwc3_writel(dwc, DWC3_GUSB2PHYACC(0), reg); =20 return dwc3_ulpi_busyloop(dwc, addr, false); } --=20 2.34.1