From nobody Sat Feb 7 08:44:20 2026 Received: from out-189.mta0.migadu.com (out-189.mta0.migadu.com [91.218.175.189]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAF8C3191A9 for ; Mon, 5 Jan 2026 10:55:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.189 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767610528; cv=none; b=tUnNocYrGZnV1i19LXuxOb+vlWcTCkfUIhvi8AlhELgI8U2fBPDfukzoUJd0qLpU5Hj1mrLWzMsh90OaF/vjEKof3Lq7HER38hmweuI4d83i21YiU91ShhoYgIUyqtAoqbEAXSBfj16mY9kqOPGdzkWRG6Nc6AveFhaxZR/uf1k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767610528; c=relaxed/simple; bh=sJvta61e7Mf0t7zmQWhXb474jlF4nrYsgrlBrZYj6vU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=r177M+g/B69jOcR5qCHHbSnf3vI5k7BZCPOREpNsnN4rGmtncLfeiBI8Mqh5AhBJsSir8+VgarWEWqahEt//UEfi2I0Zk1dbe4gu4KblUzX0s3AII8xyFg7VKS5XvbnXUGMRhu3V/lbaGAl1nDKC7ZwVSW8+u3t6NEqnH20+ZIA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=AcfHgUpA; arc=none smtp.client-ip=91.218.175.189 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="AcfHgUpA" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1767610523; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9qVCFGif6aX0Q2JIbCH2ROkDXMNqpato8z92+S7+prM=; b=AcfHgUpAIJlaSq71+UGdtDOe0+F8XFJp+DddB/Hu3/tjYpivNEoh4bfHOj7fnJVs6cZ15f hdnVDNXPS6dhEofox4Ep+gft8yrcIs2nkJ/bTIyjZggi2cyj5B+E09osdtvQHNdXzL7ZKF R/PMBo/HvFrDDSaQFg5cjpV/Nhdz2mQ= From: George Guo To: chenhuacai@kernel.org Cc: dongtai.guo@linux.dev, hengqi.chen@gmail.com, kernel@xen0n.name, lianyangyang@kylinos.cn, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, r@hev.cc, xry111@xry111.site, George Guo Subject: [PATCH v9 loongarch-next 1/4] LoongArch: Replace seq_printf with seq_puts for simple strings Date: Mon, 5 Jan 2026 18:55:11 +0800 Message-ID: <20260105105514.76021-2-dongtai.guo@linux.dev> In-Reply-To: <20260105105514.76021-1-dongtai.guo@linux.dev> References: <20260105105514.76021-1-dongtai.guo@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" From: George Guo Fix warnings like: "Prefer seq_puts to seq_printf" by checkpatch.pl. Replace seq_printf() calls with seq_puts() in show_cpuinfo() when outputting simple constant strings without format specifiers. This improves performance slightly as seq_puts() avoids parsing the format string. Signed-off-by: George Guo --- arch/loongarch/kernel/proc.c | 61 ++++++++++++++++++++++-------------- 1 file changed, 38 insertions(+), 23 deletions(-) diff --git a/arch/loongarch/kernel/proc.c b/arch/loongarch/kernel/proc.c index a8800d20e11b..1d646da010f9 100644 --- a/arch/loongarch/kernel/proc.c +++ b/arch/loongarch/kernel/proc.c @@ -50,32 +50,47 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "Address Sizes\t\t: %d bits physical, %d bits virtual\n", cpu_pabits + 1, cpu_vabits + 1); =20 - seq_printf(m, "ISA\t\t\t:"); + seq_puts(m, "ISA\t\t\t:"); if (isa & LOONGARCH_CPU_ISA_LA32R) - seq_printf(m, " loongarch32r"); + seq_puts(m, " loongarch32r"); if (isa & LOONGARCH_CPU_ISA_LA32S) - seq_printf(m, " loongarch32s"); + seq_puts(m, " loongarch32s"); if (isa & LOONGARCH_CPU_ISA_LA64) - seq_printf(m, " loongarch64"); - seq_printf(m, "\n"); + seq_puts(m, " loongarch64"); + seq_puts(m, "\n"); =20 - seq_printf(m, "Features\t\t:"); - if (cpu_has_cpucfg) seq_printf(m, " cpucfg"); - if (cpu_has_lam) seq_printf(m, " lam"); - if (cpu_has_ual) seq_printf(m, " ual"); - if (cpu_has_fpu) seq_printf(m, " fpu"); - if (cpu_has_lsx) seq_printf(m, " lsx"); - if (cpu_has_lasx) seq_printf(m, " lasx"); - if (cpu_has_crc32) seq_printf(m, " crc32"); - if (cpu_has_complex) seq_printf(m, " complex"); - if (cpu_has_crypto) seq_printf(m, " crypto"); - if (cpu_has_ptw) seq_printf(m, " ptw"); - if (cpu_has_lspw) seq_printf(m, " lspw"); - if (cpu_has_lvz) seq_printf(m, " lvz"); - if (cpu_has_lbt_x86) seq_printf(m, " lbt_x86"); - if (cpu_has_lbt_arm) seq_printf(m, " lbt_arm"); - if (cpu_has_lbt_mips) seq_printf(m, " lbt_mips"); - seq_printf(m, "\n"); + seq_puts(m, "Features\t\t:"); + if (cpu_has_cpucfg) + seq_puts(m, " cpucfg"); + if (cpu_has_lam) + seq_puts(m, " lam"); + if (cpu_has_ual) + seq_puts(m, " ual"); + if (cpu_has_fpu) + seq_puts(m, " fpu"); + if (cpu_has_lsx) + seq_puts(m, " lsx"); + if (cpu_has_lasx) + seq_puts(m, " lasx"); + if (cpu_has_crc32) + seq_puts(m, " crc32"); + if (cpu_has_complex) + seq_puts(m, " complex"); + if (cpu_has_crypto) + seq_puts(m, " crypto"); + if (cpu_has_ptw) + seq_puts(m, " ptw"); + if (cpu_has_lspw) + seq_puts(m, " lspw"); + if (cpu_has_lvz) + seq_puts(m, " lvz"); + if (cpu_has_lbt_x86) + seq_puts(m, " lbt_x86"); + if (cpu_has_lbt_arm) + seq_puts(m, " lbt_arm"); + if (cpu_has_lbt_mips) + seq_puts(m, " lbt_mips"); + seq_puts(m, "\n"); =20 seq_printf(m, "Hardware Watchpoint\t: %s", str_yes_no(cpu_has_watch)); if (cpu_has_watch) { @@ -83,7 +98,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) cpu_data[n].watch_ireg_count, cpu_data[n].watch_dreg_count); } =20 - seq_printf(m, "\n\n"); + seq_puts(m, "\n\n"); =20 return 0; } --=20 2.43.0 From nobody Sat Feb 7 08:44:20 2026 Received: from out-189.mta0.migadu.com (out-189.mta0.migadu.com [91.218.175.189]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83CE831961F for ; Mon, 5 Jan 2026 10:55:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.189 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767610529; cv=none; b=MT/9kJxmDd3nzCjMg9EDYbn4Blko1dshBqDNkBqAAReeIiloaueGyI/5w9QFw62bF49qK+/kxBXoEm+axem40Q6aaHiWiTNRYwmlnw4R8P0LF6DLqgheUuqlZwhFWHamJV7Bpfz/PBZQdwh7LlHCOCNrg9+05IJFqcZg5pVtYz8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767610529; c=relaxed/simple; bh=v9dGUaKiidFT+wdfksDoj6y+BO3lzpqJ86ZIRN+U4Mg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XmKvyLjmCK/7Q6TP7hIu/5GsLQNd9igcMwL+GhJ6BeocL+ClKSlpeEhWYjEj6J+ZWtposUcgU+g99D7WUGnXvoWi3XqDD50U6lhWeZfMkb9HTIcKC7MUAJb4R1VBmhzf8D7gdbFOAQoh0vxVpuZssv7FbsjXIhp1zMxOGivzdRM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=gX6+IS4X; arc=none smtp.client-ip=91.218.175.189 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="gX6+IS4X" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1767610525; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=SmbWiSqYvy7Kpnw5YL2YoBrlTEHHLFtpCiYxR9AYad8=; b=gX6+IS4XAGwOSnlm8cnjK+lSAIgm7LzC2F8dNla8NPNwr1hyfzjurZBt8Hx1ysurY+tuwk /qX6bFIv7z/ra7grv4VBNeA3n+xMLTM2NyupPR6oomKGLY06RvHXPCzxog+3+5vQosAP97 nDiJUhpy2NjkuWV4xVFNvLQ9TUOtJ3s= From: George Guo To: chenhuacai@kernel.org Cc: dongtai.guo@linux.dev, hengqi.chen@gmail.com, kernel@xen0n.name, lianyangyang@kylinos.cn, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, r@hev.cc, xry111@xry111.site, George Guo Subject: [PATCH v9 loongarch-next 2/4] LoongArch: Add SCQ support detection Date: Mon, 5 Jan 2026 18:55:12 +0800 Message-ID: <20260105105514.76021-3-dongtai.guo@linux.dev> In-Reply-To: <20260105105514.76021-1-dongtai.guo@linux.dev> References: <20260105105514.76021-1-dongtai.guo@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" From: George Guo Check CPUCFG2_SCQ bit to determine if the CPU supports SCQ instruction. Co-developed-by: Yangyang Lian Signed-off-by: Yangyang Lian Reviewed-by: Hengqi Chen Tested-by: Hengqi Chen Signed-off-by: George Guo --- arch/loongarch/include/asm/cpu-features.h | 1 + arch/loongarch/include/asm/cpu.h | 2 ++ arch/loongarch/include/uapi/asm/hwcap.h | 1 + arch/loongarch/kernel/cpu-probe.c | 4 ++++ arch/loongarch/kernel/proc.c | 2 ++ 5 files changed, 10 insertions(+) diff --git a/arch/loongarch/include/asm/cpu-features.h b/arch/loongarch/inc= lude/asm/cpu-features.h index 3745d991a99a..39c7fe64c3ef 100644 --- a/arch/loongarch/include/asm/cpu-features.h +++ b/arch/loongarch/include/asm/cpu-features.h @@ -67,5 +67,6 @@ #define cpu_has_msgint cpu_opt(LOONGARCH_CPU_MSGINT) #define cpu_has_avecint cpu_opt(LOONGARCH_CPU_AVECINT) #define cpu_has_redirectint cpu_opt(LOONGARCH_CPU_REDIRECTINT) +#define cpu_has_scq cpu_opt(LOONGARCH_CPU_SCQ) =20 #endif /* __ASM_CPU_FEATURES_H */ diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/include/asm/= cpu.h index f3efb00b6141..5531039027ec 100644 --- a/arch/loongarch/include/asm/cpu.h +++ b/arch/loongarch/include/asm/cpu.h @@ -125,6 +125,7 @@ static inline char *id_to_core_name(unsigned int id) #define CPU_FEATURE_MSGINT 29 /* CPU has MSG interrupt */ #define CPU_FEATURE_AVECINT 30 /* CPU has AVEC interrupt */ #define CPU_FEATURE_REDIRECTINT 31 /* CPU has interrupt remapping */ +#define CPU_FEATURE_SCQ 32 /* CPU has SC.Q instruction */ =20 #define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG) #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM) @@ -158,5 +159,6 @@ static inline char *id_to_core_name(unsigned int id) #define LOONGARCH_CPU_MSGINT BIT_ULL(CPU_FEATURE_MSGINT) #define LOONGARCH_CPU_AVECINT BIT_ULL(CPU_FEATURE_AVECINT) #define LOONGARCH_CPU_REDIRECTINT BIT_ULL(CPU_FEATURE_REDIRECTINT) +#define LOONGARCH_CPU_SCQ BIT_ULL(CPU_FEATURE_SCQ) =20 #endif /* _ASM_CPU_H */ diff --git a/arch/loongarch/include/uapi/asm/hwcap.h b/arch/loongarch/inclu= de/uapi/asm/hwcap.h index 2b34e56cfa9e..a3c570d407b9 100644 --- a/arch/loongarch/include/uapi/asm/hwcap.h +++ b/arch/loongarch/include/uapi/asm/hwcap.h @@ -18,5 +18,6 @@ #define HWCAP_LOONGARCH_LBT_MIPS (1 << 12) #define HWCAP_LOONGARCH_PTW (1 << 13) #define HWCAP_LOONGARCH_LSPW (1 << 14) +#define HWCAP_LOONGARCH_CPU_SCQ (1 << 15) =20 #endif /* _UAPI_ASM_HWCAP_H */ diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-= probe.c index 08a227034042..0051f2fcd3ec 100644 --- a/arch/loongarch/kernel/cpu-probe.c +++ b/arch/loongarch/kernel/cpu-probe.c @@ -205,6 +205,10 @@ static void cpu_probe_common(struct cpuinfo_loongarch = *c) c->options |=3D LOONGARCH_CPU_PTW; elf_hwcap |=3D HWCAP_LOONGARCH_PTW; } + if (config & CPUCFG2_SCQ) { + c->options |=3D LOONGARCH_CPU_SCQ; + elf_hwcap |=3D HWCAP_LOONGARCH_CPU_SCQ; + } if (config & CPUCFG2_LSPW) { c->options |=3D LOONGARCH_CPU_LSPW; elf_hwcap |=3D HWCAP_LOONGARCH_LSPW; diff --git a/arch/loongarch/kernel/proc.c b/arch/loongarch/kernel/proc.c index 1d646da010f9..1b9cc05d1f33 100644 --- a/arch/loongarch/kernel/proc.c +++ b/arch/loongarch/kernel/proc.c @@ -90,6 +90,8 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_puts(m, " lbt_arm"); if (cpu_has_lbt_mips) seq_puts(m, " lbt_mips"); + if (cpu_has_scq) + seq_puts(m, " scq"); seq_puts(m, "\n"); =20 seq_printf(m, "Hardware Watchpoint\t: %s", str_yes_no(cpu_has_watch)); --=20 2.43.0 From nobody Sat Feb 7 08:44:20 2026 Received: from out-186.mta0.migadu.com (out-186.mta0.migadu.com [91.218.175.186]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AAA6332C30A for ; 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DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1767610527; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=D6rvEwZD8QRZ7Ipur3Iub81lCQbfAfUNvjx39IoX1tE=; b=ajQ6d8y5Dd4dTaCmrNihZvpstMNcCL7nHJ7+zCqCbHw0BJBlnndYfS6B0WCdlUZgeizK/4 0m/Qj9Q1I06Oh+fEaRj1/ChBU6vj8LSL6Xfxd4KozPlItbGN2Kh7vYrGvLQhnyQr5AETJK xXCLQi5n1GIIt8SR27REQFpp7VHBwbI= From: George Guo To: chenhuacai@kernel.org Cc: dongtai.guo@linux.dev, hengqi.chen@gmail.com, kernel@xen0n.name, lianyangyang@kylinos.cn, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, r@hev.cc, xry111@xry111.site, George Guo Subject: [PATCH v9 loongarch-next 3/4] LoongArch: Add 128-bit atomic cmpxchg support Date: Mon, 5 Jan 2026 18:55:13 +0800 Message-ID: <20260105105514.76021-4-dongtai.guo@linux.dev> In-Reply-To: <20260105105514.76021-1-dongtai.guo@linux.dev> References: <20260105105514.76021-1-dongtai.guo@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" From: George Guo Implement 128-bit atomic compare-and-exchange using LoongArch's LL.D/SC.Q instructions. At the same time, fix BPF scheduler test failures (scx_central scx_qmap) caused by kmalloc_nolock_noprof returning NULL due to missing 128-bit atomics. The NULL returns led to -ENOMEM errors during scheduler initialization, causing test cases to fail. Verified by testing with the scx_qmap scheduler (located in tools/sched_ext/). Building with `make` and running ./tools/sched_ext/build/bin/scx_qmap. Link: https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git/commit/?i= d=3D5fb750e8a9ae Acked-by: Hengqi Chen Tested-by: Hengqi Chen Signed-off-by: George Guo --- arch/loongarch/include/asm/cmpxchg.h | 48 ++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/loongarch/include/asm/cmpxchg.h b/arch/loongarch/include/= asm/cmpxchg.h index 0494c2ab553e..d25e25d8fc9e 100644 --- a/arch/loongarch/include/asm/cmpxchg.h +++ b/arch/loongarch/include/asm/cmpxchg.h @@ -8,6 +8,7 @@ #include #include #include +#include =20 #define __xchg_amo_asm(amswap_db, m, val) \ ({ \ @@ -137,6 +138,44 @@ __arch_xchg(volatile void *ptr, unsigned long x, int s= ize) __ret; \ }) =20 +union __u128_halves { + u128 full; + struct { + u64 low; + u64 high; + }; +}; + +#define __arch_cmpxchg128(ptr, old, new) \ +({ \ + union __u128_halves __old, __new, __ret; \ + volatile u64 *__ptr =3D (volatile u64 *)(ptr); \ + \ + __old.full =3D (old); \ + __new.full =3D (new); \ + \ + __asm__ __volatile__( \ + "1: ll.d %0, %3 # 128-bit cmpxchg low \n" \ + __WEAK_LLSC_MB \ + " ld.d %1, %4 # 128-bit cmpxchg high \n" \ + " bne %0, %z5, 2f \n" \ + " bne %1, %z6, 2f \n" \ + " move $t0, %z7 \n" \ + " move $t1, %z8 \n" \ + " sc.q $t0, $t1, %2 \n" \ + " beqz $t0, 1b \n" \ + "2: \n" \ + __WEAK_LLSC_MB \ + : "=3D&r" (__ret.low), "=3D&r" (__ret.high) \ + : "r" (__ptr), \ + "ZC" (__ptr[0]), "m" (__ptr[1]), \ + "Jr" (__old.low), "Jr" (__old.high), \ + "Jr" (__new.low), "Jr" (__new.high) \ + : "t0", "t1", "memory"); \ + \ + __ret.full; \ +}) + static inline unsigned int __cmpxchg_small(volatile void *ptr, unsigned in= t old, unsigned int new, unsigned int size) { @@ -224,6 +263,15 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsig= ned long new, unsigned int __res; \ }) =20 +/* cmpxchg128 */ +#define system_has_cmpxchg128() (cpu_has_scq) + +#define arch_cmpxchg128(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 16); \ + __arch_cmpxchg128(ptr, o, n); \ +}) + #ifdef CONFIG_64BIT #define arch_cmpxchg64_local(ptr, o, n) \ ({ \ --=20 2.43.0 From nobody Sat Feb 7 08:44:20 2026 Received: from out-188.mta0.migadu.com (out-188.mta0.migadu.com [91.218.175.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AAB5B32E6B4 for ; Mon, 5 Jan 2026 10:55:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767610535; cv=none; b=Ohem98XNzzjsCv96kONlpl5X9m07Cy3RtGpllGdzDdOhQX1ke66ssKg6mcN5YQeBY4KL76uLKjp66Ig0ofr0+zxvfAUcy+0H4UCnkvp/01nlHbXcb1kiITfSS9P2DP/Ci/OTjJ8WVzDTz/TIVfnHFsga/o5u5z52kMtEDJSxOqg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767610535; c=relaxed/simple; bh=VvIMH6uDCfo9dHgHYOA50uC9oucTRbBEH2ez1L+nu/0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LybF4VWg19Zuc0QuZ4ygS0g6ojGlJ2hPI2yPd1JMzxQLN891eoKGx3QhHuNdzFVhOkTTnRj5KTJqMaZkbjeDlefh41QhhMsP9RUTNrAy17++INX9VCHPXfJMdjgeuxeWIN4efdB5FLvAHBzGMno8au/8Y5kvwnRbpPErjFnRRuo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=ELLsImp8; arc=none smtp.client-ip=91.218.175.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="ELLsImp8" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1767610529; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=90lPtiX5iGw6HKdw2bSu0Tovhut4F8g9SrqqXr/vigA=; b=ELLsImp8JFptd+lTJNZSfdVorahEefI8KjaNa2rDC5GcGrfiODzfnoECuPDP4KG1Af2MAv XWN9r7PSsQAYwTLsMndefSojZCDLqhWOu7DGCBLTJt/LjJYpp093OYoKmYaVQbho4OEG/S A4LN5JMvYdwODSvvWQiDGuayJzSZVrA= From: George Guo To: chenhuacai@kernel.org Cc: dongtai.guo@linux.dev, hengqi.chen@gmail.com, kernel@xen0n.name, lianyangyang@kylinos.cn, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, r@hev.cc, xry111@xry111.site, George Guo Subject: [PATCH v9 loongarch-next 4/4] LoongArch: Enable 128-bit atomics cmpxchg support Date: Mon, 5 Jan 2026 18:55:14 +0800 Message-ID: <20260105105514.76021-5-dongtai.guo@linux.dev> In-Reply-To: <20260105105514.76021-1-dongtai.guo@linux.dev> References: <20260105105514.76021-1-dongtai.guo@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" From: George Guo Add select HAVE_CMPXCHG_DOUBLE and select HAVE_ALIGNED_STRUCT_PAGE in Kconf= ig to enable 128-bit atomic cmpxchg support on LoongArch. Reviewed-by: Hengqi Chen Tested-by: Hengqi Chen Signed-off-by: George Guo --- arch/loongarch/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index 730f34214519..f9845ebec1a4 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -114,6 +114,7 @@ config LOONGARCH select GENERIC_TIME_VSYSCALL select GPIOLIB select HAS_IOPORT + select HAVE_ALIGNED_STRUCT_PAGE select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_BITREVERSE select HAVE_ARCH_JUMP_LABEL @@ -130,6 +131,7 @@ config LOONGARCH select HAVE_ARCH_TRANSPARENT_HUGEPAGE select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD select HAVE_ASM_MODVERSIONS + select HAVE_CMPXCHG_DOUBLE select HAVE_CONTEXT_TRACKING_USER select HAVE_C_RECORDMCOUNT select HAVE_DEBUG_KMEMLEAK --=20 2.43.0