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Change of_pci_get_equalization_presets() to accept a device_node pointer. This allows parsing equalization presets from any device tree node, which is needed for multi-port PCIe controllers. Signed-off-by: Sumit Kumar --- drivers/pci/of.c | 6 ++++-- drivers/pci/pci.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index 3579265f119845637e163d9051437c89662762f8..d09eff40b523c920c9ca3eaa64f= 784765b3c5bf8 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -971,6 +971,7 @@ EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); * of_pci_get_equalization_presets - Parses the "eq-presets-Ngts" property. * * @dev: Device containing the properties. + * @node: Device tree node containing the properties. * @presets: Pointer to store the parsed data. * @num_lanes: Maximum number of lanes supported. * @@ -981,6 +982,7 @@ EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); * errno otherwise. */ int of_pci_get_equalization_presets(struct device *dev, + struct device_node *node, struct pci_eq_presets *presets, int num_lanes) { @@ -988,7 +990,7 @@ int of_pci_get_equalization_presets(struct device *dev, int ret; =20 presets->eq_presets_8gts[0] =3D PCI_EQ_RESV; - ret =3D of_property_read_u16_array(dev->of_node, "eq-presets-8gts", + ret =3D of_property_read_u16_array(node, "eq-presets-8gts", presets->eq_presets_8gts, num_lanes); if (ret && ret !=3D -EINVAL) { dev_err(dev, "Error reading eq-presets-8gts: %d\n", ret); @@ -998,7 +1000,7 @@ int of_pci_get_equalization_presets(struct device *dev, for (int i =3D 0; i < EQ_PRESET_TYPE_MAX - 1; i++) { presets->eq_presets_Ngts[i][0] =3D PCI_EQ_RESV; snprintf(name, sizeof(name), "eq-presets-%dgts", 8 << (i + 1)); - ret =3D of_property_read_u8_array(dev->of_node, name, + ret =3D of_property_read_u8_array(node, name, presets->eq_presets_Ngts[i], num_lanes); if (ret && ret !=3D -EINVAL) { diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 34f65d69662e9f61f0c489ec58de2ce17d21c0c6..72fa6db95b8a75f6e69b8019d1e= b2262b6a46c13 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -965,6 +965,7 @@ void pci_release_bus_of_node(struct pci_bus *bus); int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *br= idge); 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a=ed25519-sha256; t=1767616078; l=30988; i=sumit.kumar@oss.qualcomm.com; s=20250409; h=from:subject:message-id; bh=IS0G0BpMid9/nqI0jD+QbVmmNAwgZUEycCSk3LGYIYE=; b=70nNXL65DjlN4enNSlB2XKOCB6g/U7kHGmK5Lfs3ix2AOFZ7Z4hQS+VIMVK+52cm4p/hN0LFP yldqPPqgv9oCKZ9lgZJeesOcWfcCW9w5AlCn5sIGXDV0uuPRJipUbaV X-Developer-Key: i=sumit.kumar@oss.qualcomm.com; a=ed25519; pk=3cys6srXqLACgA68n7n7KjDeM9JiMK1w6VxzMxr0dnM= X-Authority-Analysis: v=2.4 cv=I5Vohdgg c=1 sm=1 tr=0 ts=695bae6f cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=4983JweL2ci_JWkmBjsA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: _SbOWo4YFDAesEOedOaPAIlnTe-LSjtz X-Proofpoint-ORIG-GUID: _SbOWo4YFDAesEOedOaPAIlnTe-LSjtz X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA1MDEwOSBTYWx0ZWRfX5XxHnegFrj9n ctG3AcpQqBXp++p4QNW85HzGF7Lxj6wbQqyXzVx9i7GYJQj4HostNjnCEpRKhI/Dw2O00ueW6up r7DKMjYg8YEAG2PnihPR2YlYS/0lMBcNjpKGeaaugTCmUvw19sKnm2x68/IKwAVflkqQKbT6Hyb ZVGzZ9tG4DYOr84veINsw1c/9yl+bYpGPCoiJX0ltGCPlIDhxgTgPGbYh8UqdMlE9rjqB4b+EVj gvdv8bIPdwVkSjJz7pQEORTNyK3tF4aBIG+BGbRt3DYC7HqPbQCVmJy8ij8Vb79FyrF4/NkzVOO LecQLaIYHBxhhz/oRQwSZOIdG4bWE4WQlqqFwKiXYAvAs9nTe9xnKA1Vt01TU+KZMm32JhL0MGc od0T9/Pj6hsEX7Swpo1PmM4E5cyE1FoIMoKlFQ55IDPifSqcizJMFsWG9tUEppQMJnJ4wFJPaUM wTgLCMrskN/dRC1sWnA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-05_01,2025-12-31_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 priorityscore=1501 bulkscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601050109 The current DesignWare PCIe RC implementation supports only the controller (Host Bridge) node for specifying the Root Port properties in an assumption that the underlying platform only supports a single root Port per controller instance. This limits support for multi-port controllers where different ports may have different lane configurations and speed limits. Introduce a separate dw_pcie_port structure to enable multi-port support. Each Root Port can have independent lane count, speed limit through pcie@N child nodes in device tree. Add dw_pcie_parse_root_ports() API to parse these child nodes. Equalization presets and link width detection currently use common DBI space for all the root ports. Per-port DBI space assignment for these features will be added in future. Signed-off-by: Sumit Kumar --- drivers/pci/controller/dwc/pci-exynos.c | 4 +- drivers/pci/controller/dwc/pci-imx6.c | 15 +- drivers/pci/controller/dwc/pci-meson.c | 1 - drivers/pci/controller/dwc/pcie-designware-host.c | 168 ++++++++++++++++++= ---- drivers/pci/controller/dwc/pcie-designware.c | 32 ++--- drivers/pci/controller/dwc/pcie-designware.h | 17 ++- drivers/pci/controller/dwc/pcie-fu740.c | 6 +- drivers/pci/controller/dwc/pcie-intel-gw.c | 13 +- drivers/pci/controller/dwc/pcie-qcom-common.c | 5 +- drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 +- drivers/pci/controller/dwc/pcie-qcom.c | 4 +- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 13 +- drivers/pci/controller/dwc/pcie-spear13xx.c | 5 +- drivers/pci/controller/dwc/pcie-tegra194.c | 4 +- 14 files changed, 220 insertions(+), 71 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controll= er/dwc/pci-exynos.c index 1f0e98d07109353e7321667e98ead2695151184c..af991a14b52792d2376fd308758= 54c46fd65155a 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -358,6 +358,8 @@ static int exynos_pcie_resume_noirq(struct device *dev) struct exynos_pcie *ep =3D dev_get_drvdata(dev); struct dw_pcie *pci =3D &ep->pci; struct dw_pcie_rp *pp =3D &pci->pp; + struct dw_pcie_port *port =3D list_first_entry(&pci->pp.ports, + struct dw_pcie_port, list); int ret; =20 ret =3D regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep->supplies); @@ -368,7 +370,7 @@ static int exynos_pcie_resume_noirq(struct device *dev) exynos_pcie_host_init(pp); dw_pcie_setup_rc(pp); exynos_pcie_start_link(pci); - return dw_pcie_wait_for_link(pci); + return dw_pcie_wait_for_link(pci, port); } =20 static const struct dev_pm_ops exynos_pcie_pm_ops =3D { diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 80e48746bbaf6815d8b9e879be5fa0bb992d9189..107367b72afc937daf26305dea2= b5ad9ce3f86ae 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -939,6 +939,8 @@ static int imx_pcie_start_link(struct dw_pcie *pci) struct imx_pcie *imx_pcie =3D to_imx_pcie(pci); struct device *dev =3D pci->dev; u8 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + struct dw_pcie_port *port =3D list_first_entry(&pci->pp.ports, + struct dw_pcie_port, list); u32 tmp; int ret; =20 @@ -963,8 +965,8 @@ static int imx_pcie_start_link(struct dw_pcie *pci) /* Start LTSSM. */ imx_pcie_ltssm_enable(dev); =20 - if (pci->max_link_speed > 1) { - ret =3D dw_pcie_wait_for_link(pci); + if (port->max_link_speed > 1) { + ret =3D dw_pcie_wait_for_link(pci, port); if (ret) goto err_reset_phy; =20 @@ -972,7 +974,7 @@ static int imx_pcie_start_link(struct dw_pcie *pci) dw_pcie_dbi_ro_wr_en(pci); tmp =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); tmp &=3D ~PCI_EXP_LNKCAP_SLS; - tmp |=3D pci->max_link_speed; + tmp |=3D port->max_link_speed; dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); =20 /* @@ -1605,6 +1607,7 @@ static int imx_pcie_probe(struct platform_device *pde= v) struct dw_pcie *pci; struct imx_pcie *imx_pcie; struct device_node *np; + struct dw_pcie_port *port; struct device_node *node =3D dev->of_node; int ret, domain; u16 val; @@ -1741,9 +1744,9 @@ static int imx_pcie_probe(struct platform_device *pde= v) &imx_pcie->tx_swing_low)) imx_pcie->tx_swing_low =3D 127; =20 - /* Limit link speed */ - pci->max_link_speed =3D 1; - of_property_read_u32(node, "fsl,max-link-speed", &pci->max_link_speed); + port =3D list_first_entry(&pci->pp.ports, struct dw_pcie_port, list); + port->max_link_speed =3D 1; + of_property_read_u32(node, "fsl,max-link-speed", &port->max_link_speed); =20 imx_pcie->vpcie =3D devm_regulator_get_optional(&pdev->dev, "vpcie"); if (IS_ERR(imx_pcie->vpcie)) { diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controlle= r/dwc/pci-meson.c index 787469d1b396d4c7b3e28edfe276b7b997fb8aee..45d855e72e8479432c66b5c00a9= 755163ecd2741 100644 --- a/drivers/pci/controller/dwc/pci-meson.c +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -411,7 +411,6 @@ static int meson_pcie_probe(struct platform_device *pde= v) pci->dev =3D dev; pci->ops =3D &dw_pcie_ops; pci->pp.ops =3D &meson_pcie_host_ops; - pci->num_lanes =3D 1; =20 mp->phy =3D devm_phy_get(dev, "pcie"); if (IS_ERR(mp->phy)) { diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 952f8594b501254d2b2de5d5e056e16d2aa8d4b7..a864b90bd51ce475a2fd7de8357= 3cf3ddea196e7 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -456,11 +456,86 @@ static int dw_pcie_host_get_resources(struct dw_pcie_= rp *pp) return 0; } =20 +static int dw_pcie_parse_root_ports(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct dw_pcie_port *port, *tmp; + struct device *dev =3D pci->dev; + int max_link_speed; + u32 num_lanes; + int ret; + + if (!of_get_available_child_count(dev->of_node)) { + port =3D devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) + return -ENOMEM; + + port->dev_node =3D dev->of_node; + list_add_tail(&port->list, &pp->ports); + + return 0; + } + + for_each_available_child_of_node_scoped(dev->of_node, of_port) { + num_lanes =3D 0; + max_link_speed =3D 0; + of_property_read_u32(of_port, "num-lanes", &num_lanes); + max_link_speed =3D of_pci_get_max_link_speed(of_port); + + port =3D devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) { + ret =3D -ENOMEM; + goto err_port_del; + } + + port->dev_node =3D of_port; + port->num_lanes =3D num_lanes; + port->max_link_speed =3D max_link_speed; + list_add_tail(&port->list, &pp->ports); + } + + return 0; + +err_port_del: + list_for_each_entry_safe(port, tmp, &pp->ports, list) + list_del(&port->list); + + return ret; +} + +static int dw_pcie_parse_legacy_binding(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct device *dev =3D pci->dev; + struct dw_pcie_port *port; + int max_link_speed; + u32 num_lanes; + int ret; + + ret =3D of_property_read_u32(dev->of_node, "num-lanes", &num_lanes); + max_link_speed =3D of_pci_get_max_link_speed(dev->of_node); + + if (ret && max_link_speed <=3D 0) + return -ENOENT; + + port =3D devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) + return -ENOMEM; + + port->dev_node =3D dev->of_node; + port->num_lanes =3D num_lanes; + port->max_link_speed =3D max_link_speed; + list_add_tail(&port->list, &pp->ports); + + return 0; +} + int dw_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); struct device *dev =3D pci->dev; struct device_node *np =3D dev->of_node; + struct dw_pcie_port *port, *tmp; struct pci_host_bridge *bridge; int ret; =20 @@ -472,6 +547,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) =20 pp->bridge =3D bridge; =20 + INIT_LIST_HEAD(&pp->ports); + ret =3D dw_pcie_host_get_resources(pp); if (ret) return ret; @@ -480,10 +557,25 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) bridge->ops =3D &dw_pcie_ops; bridge->child_ops =3D &dw_child_pcie_ops; =20 + /* + * Try to parse legacy binding first (properties in Host Bridge node). + * If not found, try parsing Root Port child nodes. + */ + ret =3D dw_pcie_parse_legacy_binding(pp); + if (ret =3D=3D -ENOENT) { + ret =3D dw_pcie_parse_root_ports(pp); + if (ret && ret !=3D -ENOENT) { + dev_err(dev, "Failed to parse Root Port: %d\n", ret); + return ret; + } + } else if (ret) { + return ret; + } + if (pp->ops->init) { ret =3D pp->ops->init(pp); if (ret) - return ret; + goto err_cleanup_ports; } =20 if (pci_msi_enabled()) { @@ -518,12 +610,15 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) =20 dw_pcie_iatu_detect(pci); =20 - if (pci->num_lanes < 1) - pci->num_lanes =3D dw_pcie_link_get_max_link_width(pci); + list_for_each_entry(port, &pp->ports, list) { + if (port->num_lanes < 1) + port->num_lanes =3D dw_pcie_link_get_max_link_width(pci, port); =20 - ret =3D of_pci_get_equalization_presets(dev, &pp->presets, pci->num_lanes= ); - if (ret) - goto err_free_msi; + ret =3D of_pci_get_equalization_presets(dev, port->dev_node, + &port->presets, port->num_lanes); + if (ret) + goto err_free_msi; + } =20 /* * Allocate the resource for MSG TLP before programming the iATU @@ -557,8 +652,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) * because that would require users to manually rescan for devices. */ if (!pp->use_linkup_irq) - /* Ignore errors, the link may come up later */ - dw_pcie_wait_for_link(pci); + list_for_each_entry(port, &pp->ports, list) + dw_pcie_wait_for_link(pci, port); =20 bridge->sysdata =3D pp; =20 @@ -586,6 +681,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) err_deinit_host: if (pp->ops->deinit) pp->ops->deinit(pp); +err_cleanup_ports: + list_for_each_entry_safe(port, tmp, &pp->ports, list) + list_del(&port->list); =20 return ret; } @@ -594,6 +692,7 @@ EXPORT_SYMBOL_GPL(dw_pcie_host_init); void dw_pcie_host_deinit(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct dw_pcie_port *port, *tmp; =20 dwc_pcie_debugfs_deinit(pci); =20 @@ -607,6 +706,9 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp) if (pp->has_msi_ctrl) dw_pcie_free_msi(pp); =20 + list_for_each_entry_safe(port, tmp, &pp->ports, list) + list_del(&port->list); + if (pp->ops->deinit) pp->ops->deinit(pp); } @@ -830,7 +932,9 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) return 0; } =20 -static void dw_pcie_program_presets(struct dw_pcie_rp *pp, enum pci_bus_sp= eed speed) +/*TODO: Handling preset values according to dbi space of each port */ +static void dw_pcie_program_presets(struct dw_pcie_rp *pp, struct dw_pcie_= port *port, + enum pci_bus_speed speed) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); u8 lane_eq_offset, lane_reg_size, cap_id; @@ -839,23 +943,23 @@ static void dw_pcie_program_presets(struct dw_pcie_rp= *pp, enum pci_bus_speed sp int i; =20 if (speed =3D=3D PCIE_SPEED_8_0GT) { - presets =3D (u8 *)pp->presets.eq_presets_8gts; + presets =3D (u8 *)port->presets.eq_presets_8gts; lane_eq_offset =3D PCI_SECPCI_LE_CTRL; cap_id =3D PCI_EXT_CAP_ID_SECPCI; /* For data rate of 8 GT/S each lane equalization control is 16bits wide= */ lane_reg_size =3D 0x2; } else if (speed =3D=3D PCIE_SPEED_16_0GT) { - presets =3D pp->presets.eq_presets_Ngts[EQ_PRESET_TYPE_16GTS - 1]; + presets =3D port->presets.eq_presets_Ngts[EQ_PRESET_TYPE_16GTS - 1]; lane_eq_offset =3D PCI_PL_16GT_LE_CTRL; cap_id =3D PCI_EXT_CAP_ID_PL_16GT; lane_reg_size =3D 0x1; } else if (speed =3D=3D PCIE_SPEED_32_0GT) { - presets =3D pp->presets.eq_presets_Ngts[EQ_PRESET_TYPE_32GTS - 1]; + presets =3D port->presets.eq_presets_Ngts[EQ_PRESET_TYPE_32GTS - 1]; lane_eq_offset =3D PCI_PL_32GT_LE_CTRL; cap_id =3D PCI_EXT_CAP_ID_PL_32GT; lane_reg_size =3D 0x1; } else if (speed =3D=3D PCIE_SPEED_64_0GT) { - presets =3D pp->presets.eq_presets_Ngts[EQ_PRESET_TYPE_64GTS - 1]; + presets =3D port->presets.eq_presets_Ngts[EQ_PRESET_TYPE_64GTS - 1]; lane_eq_offset =3D PCI_PL_64GT_LE_CTRL; cap_id =3D PCI_EXT_CAP_ID_PL_64GT; lane_reg_size =3D 0x1; @@ -874,31 +978,38 @@ static void dw_pcie_program_presets(struct dw_pcie_rp= *pp, enum pci_bus_speed sp * Write preset values to the registers byte-by-byte for the given * number of lanes and register size. */ - for (i =3D 0; i < pci->num_lanes * lane_reg_size; i++) + for (i =3D 0; i < port->num_lanes * lane_reg_size; i++) dw_pcie_writeb_dbi(pci, cap + lane_eq_offset + i, presets[i]); } =20 static void dw_pcie_config_presets(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); - enum pci_bus_speed speed =3D pcie_link_speed[pci->max_link_speed]; + enum pci_bus_speed port_speed; + struct dw_pcie_port *port; =20 /* - * Lane equalization settings need to be applied for all data rates the - * controller supports and for all supported lanes. + * Lane equalization settings need to be applied for all data rates each + * port supports and for all supported lanes per port. */ + list_for_each_entry(port, &pp->ports, list) { + if (port->max_link_speed > 0) + port_speed =3D pcie_link_speed[port->max_link_speed]; + else + port_speed =3D PCIE_SPEED_2_5GT; =20 - if (speed >=3D PCIE_SPEED_8_0GT) - dw_pcie_program_presets(pp, PCIE_SPEED_8_0GT); + if (port_speed >=3D PCIE_SPEED_8_0GT) + dw_pcie_program_presets(pp, port, PCIE_SPEED_8_0GT); =20 - if (speed >=3D PCIE_SPEED_16_0GT) - dw_pcie_program_presets(pp, PCIE_SPEED_16_0GT); + if (port_speed >=3D PCIE_SPEED_16_0GT) + dw_pcie_program_presets(pp, port, PCIE_SPEED_16_0GT); =20 - if (speed >=3D PCIE_SPEED_32_0GT) - dw_pcie_program_presets(pp, PCIE_SPEED_32_0GT); + if (port_speed >=3D PCIE_SPEED_32_0GT) + dw_pcie_program_presets(pp, port, PCIE_SPEED_32_0GT); =20 - if (speed >=3D PCIE_SPEED_64_0GT) - dw_pcie_program_presets(pp, PCIE_SPEED_64_0GT); + if (port_speed >=3D PCIE_SPEED_64_0GT) + dw_pcie_program_presets(pp, port, PCIE_SPEED_64_0GT); + } } =20 int dw_pcie_setup_rc(struct dw_pcie_rp *pp) @@ -1054,6 +1165,7 @@ EXPORT_SYMBOL_GPL(dw_pcie_suspend_noirq); =20 int dw_pcie_resume_noirq(struct dw_pcie *pci) { + struct dw_pcie_port *port; int ret; =20 if (!pci->suspended) @@ -1075,9 +1187,9 @@ int dw_pcie_resume_noirq(struct dw_pcie *pci) if (ret) return ret; =20 - ret =3D dw_pcie_wait_for_link(pci); - if (ret) - return ret; + list_for_each_entry(port, &pci->pp.ports, list) + if (dw_pcie_wait_for_link(pci, port)) + return -ETIMEDOUT; =20 return ret; } diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 89aad5a08928cc29870ab258d33bee9ff8f83143..804f633874a7a33c7788e90ea45= b529a5622060c 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -178,11 +178,6 @@ int dw_pcie_get_resources(struct dw_pcie *pci) return ret; } =20 - if (pci->max_link_speed < 1) - pci->max_link_speed =3D of_pci_get_max_link_speed(np); - - of_property_read_u32(np, "num-lanes", &pci->num_lanes); - if (of_property_read_bool(np, "snps,enable-cdm-check")) dw_pcie_cap_set(pci, CDM_CHECK); =20 @@ -696,7 +691,7 @@ void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, = int index) dw_pcie_writel_atu(pci, dir, index, PCIE_ATU_REGION_CTRL2, 0); } =20 -int dw_pcie_wait_for_link(struct dw_pcie *pci) +int dw_pcie_wait_for_link(struct dw_pcie *pci, struct dw_pcie_port *port) { u32 offset, val; int retries; @@ -719,7 +714,7 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) * speeds greater than 5.0 GT/s, software must wait a minimum of 100 ms * after Link training completes before sending a Configuration Request. */ - if (pci->max_link_speed > 2) + if (port && port->max_link_speed > 2) msleep(PCIE_RESET_CONFIG_WAIT_MS); =20 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); @@ -756,10 +751,11 @@ void dw_pcie_upconfig_setup(struct dw_pcie *pci) } EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup); =20 -static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) +static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, struct dw_pcie= _port *port) { u32 cap, ctrl2, link_speed; u8 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + int max_speed =3D port->max_link_speed; =20 cap =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); =20 @@ -768,15 +764,16 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie= *pci) * just cache the hardware default value so that the vendor drivers can * use it to do any link specific configuration. */ - if (pci->max_link_speed < 1) { - pci->max_link_speed =3D FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); + if (max_speed < 1) { + max_speed =3D FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); + port->max_link_speed =3D max_speed; return; } =20 ctrl2 =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2); ctrl2 &=3D ~PCI_EXP_LNKCTL2_TLS; =20 - switch (pcie_link_speed[pci->max_link_speed]) { + switch (pcie_link_speed[max_speed]) { case PCIE_SPEED_2_5GT: link_speed =3D PCI_EXP_LNKCTL2_TLS_2_5GT; break; @@ -800,10 +797,10 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie= *pci) =20 cap &=3D ~((u32)PCI_EXP_LNKCAP_SLS); dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed); - } =20 -int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) +/* TODO: Implement per-port max link width detection using port-specific D= BI space */ +int dw_pcie_link_get_max_link_width(struct dw_pcie *pci, struct dw_pcie_po= rt *port) { u8 cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); @@ -1141,9 +1138,14 @@ void dw_pcie_edma_remove(struct dw_pcie *pci) =20 void dw_pcie_setup(struct dw_pcie *pci) { + struct dw_pcie_port *port; u32 val; =20 - dw_pcie_link_set_max_speed(pci); + /* Configure per-port settings */ + list_for_each_entry(port, &pci->pp.ports, list) { + dw_pcie_link_set_max_speed(pci, port); + dw_pcie_link_set_max_link_width(pci, port->num_lanes); + } =20 /* Configure Gen1 N_FTS */ if (pci->n_fts[0]) { @@ -1173,8 +1175,6 @@ void dw_pcie_setup(struct dw_pcie *pci) val &=3D ~PORT_LINK_FAST_LINK_MODE; val |=3D PORT_LINK_DLL_LINK_EN; dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); - - dw_pcie_link_set_max_link_width(pci, pci->num_lanes); } =20 resource_size_t dw_pcie_parent_bus_offset(struct dw_pcie *pci, diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 00f52d472dcdd794013a865ad6c4c7cc251edb48..5ead9a40f0e91fb33d65d77cfa3= cb61b19dceea7 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -392,6 +393,14 @@ struct dw_pcie_ob_atu_cfg { u64 size; }; =20 +struct dw_pcie_port { + struct list_head list; + struct device_node *dev_node; + u32 num_lanes; + int max_link_speed; + struct pci_eq_presets presets; +}; + struct dw_pcie_host_ops { int (*init)(struct dw_pcie_rp *pp); void (*deinit)(struct dw_pcie_rp *pp); @@ -424,7 +433,7 @@ struct dw_pcie_rp { int msg_atu_index; struct resource *msg_res; bool use_linkup_irq; - struct pci_eq_presets presets; + struct list_head ports; /* List of dw_pcie_port structures */ }; =20 struct dw_pcie_ep_ops { @@ -505,8 +514,6 @@ struct dw_pcie { u32 version; u32 type; unsigned long caps; - int num_lanes; - int max_link_speed; u8 n_fts[2]; struct dw_edma_chip edma; struct clk_bulk_data app_clks[DW_PCIE_NUM_APP_CLKS]; @@ -556,8 +563,8 @@ void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, si= ze_t size, u32 val); void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val= ); bool dw_pcie_link_up(struct dw_pcie *pci); void dw_pcie_upconfig_setup(struct dw_pcie *pci); -int dw_pcie_wait_for_link(struct dw_pcie *pci); -int dw_pcie_link_get_max_link_width(struct dw_pcie *pci); +int dw_pcie_wait_for_link(struct dw_pcie *pci, struct dw_pcie_port *port); +int dw_pcie_link_get_max_link_width(struct dw_pcie *pci, struct dw_pcie_po= rt *port); int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, const struct dw_pcie_ob_atu_cfg *atu); int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, diff --git a/drivers/pci/controller/dwc/pcie-fu740.c b/drivers/pci/controll= er/dwc/pcie-fu740.c index 66367252032b84fd42c719287057471b1fe44e9a..39d9d2c8e1806dd805b669371ae= 4abc194469e57 100644 --- a/drivers/pci/controller/dwc/pcie-fu740.c +++ b/drivers/pci/controller/dwc/pcie-fu740.c @@ -179,6 +179,8 @@ static int fu740_pcie_start_link(struct dw_pcie *pci) { struct device *dev =3D pci->dev; struct fu740_pcie *afp =3D dev_get_drvdata(dev); + struct dw_pcie_port *port =3D list_first_entry(&pci->pp.ports, + struct dw_pcie_port, list); u8 cap_exp =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); int ret; u32 orig, tmp; @@ -202,7 +204,7 @@ static int fu740_pcie_start_link(struct dw_pcie *pci) /* Enable LTSSM */ writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_LTSSM_ENABLE); =20 - ret =3D dw_pcie_wait_for_link(pci); + ret =3D dw_pcie_wait_for_link(pci, port); if (ret) { dev_err(dev, "error: link did not start\n"); goto err; @@ -220,7 +222,7 @@ static int fu740_pcie_start_link(struct dw_pcie *pci) tmp |=3D PORT_LOGIC_SPEED_CHANGE; dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); =20 - ret =3D dw_pcie_wait_for_link(pci); + ret =3D dw_pcie_wait_for_link(pci, port); if (ret) { dev_err(dev, "error: link did not start at new speed\n"); goto err; diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/contr= oller/dwc/pcie-intel-gw.c index c21906eced61896c8a8307dbd6b72d229f9a5c5f..565aaa3da635749c64693268a8e= 5c1a59e1f040e 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -131,7 +131,10 @@ static void intel_pcie_link_setup(struct intel_pcie *p= cie) =20 static void intel_pcie_init_n_fts(struct dw_pcie *pci) { - switch (pci->max_link_speed) { + struct dw_pcie_port *port =3D list_first_entry(&pci->pp.ports, + struct dw_pcie_port, list); + + switch (port->max_link_speed) { case 3: pci->n_fts[1] =3D PORT_AFR_N_FTS_GEN3; break; @@ -250,8 +253,10 @@ static int intel_pcie_wait_l2(struct intel_pcie *pcie) u32 value; int ret; struct dw_pcie *pci =3D &pcie->pci; + struct dw_pcie_port *port =3D list_first_entry(&pci->pp.ports, + struct dw_pcie_port, list); =20 - if (pci->max_link_speed < 3) + if (port->max_link_speed < 3) return 0; =20 /* Send PME_TURN_OFF message */ @@ -282,6 +287,8 @@ static int intel_pcie_host_setup(struct intel_pcie *pci= e) { int ret; struct dw_pcie *pci =3D &pcie->pci; + struct dw_pcie_port *port =3D list_first_entry(&pci->pp.ports, + struct dw_pcie_port, list); =20 intel_pcie_core_rst_assert(pcie); intel_pcie_device_rst_assert(pcie); @@ -313,7 +320,7 @@ static int intel_pcie_host_setup(struct intel_pcie *pci= e) intel_pcie_device_rst_deassert(pcie); intel_pcie_ltssm_enable(pcie); =20 - ret =3D dw_pcie_wait_for_link(pci); + ret =3D dw_pcie_wait_for_link(pci, port); if (ret) goto app_init_err; =20 diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/co= ntroller/dwc/pcie-qcom-common.c index 3aad19b56da8f6ea6525f1aad0102a4d8df0369b..2d0295bd0b377f158017f7dba7a= 64b88e1dd8f68 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-common.c +++ b/drivers/pci/controller/dwc/pcie-qcom-common.c @@ -49,6 +49,8 @@ EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_equalization); void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci) { u32 reg; + struct dw_pcie_port *port =3D list_first_entry(&pci->pp.ports, + struct dw_pcie_port, list); =20 reg =3D dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_1_OFF); reg &=3D ~(MARGINING_MAX_VOLTAGE_OFFSET | @@ -70,7 +72,8 @@ void qcom_pcie_common_set_16gt_lane_margining(struct dw_p= cie *pci) MARGINING_MAXLANES | MARGINING_SAMPLE_RATE_TIMING | MARGINING_SAMPLE_RATE_VOLTAGE); - reg |=3D FIELD_PREP(MARGINING_MAXLANES, pci->num_lanes) | + + reg |=3D FIELD_PREP(MARGINING_MAXLANES, port->num_lanes) | FIELD_PREP(MARGINING_SAMPLE_RATE_TIMING, 0x3f) | FIELD_PREP(MARGINING_SAMPLE_RATE_VOLTAGE, 0x3f); dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_2_OFF, reg); diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index bf7c6ac0f3e3962de8346ab6e75dfff1d9642aad..6812ab020b3bdb99733dc12a061= 5ea98a471da63 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -389,6 +389,8 @@ static void qcom_pcie_disable_resources(struct qcom_pci= e_ep *pcie_ep) =20 static int qcom_pcie_perst_deassert(struct dw_pcie *pci) { + struct dw_pcie_port *port =3D list_first_entry(&pci->pp.ports, + struct dw_pcie_port, list); struct qcom_pcie_ep *pcie_ep =3D to_pcie_ep(pci); struct device *dev =3D pci->dev; u32 val, offset; @@ -511,7 +513,7 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) goto err_disable_resources; } =20 - if (pcie_link_speed[pci->max_link_speed] =3D=3D PCIE_SPEED_16_0GT) { + if (pcie_link_speed[port->max_link_speed] =3D=3D PCIE_SPEED_16_0GT) { qcom_pcie_common_set_16gt_equalization(pci); qcom_pcie_common_set_16gt_lane_margining(pci); } diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 294babe1816e4d0c2b2343fe22d89af72afcd6cd..9690ab97cc01160a26034bf8026= fe4dbafe48731 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -321,8 +321,10 @@ static void qcom_ep_reset_deassert(struct qcom_pcie *p= cie) static int qcom_pcie_start_link(struct dw_pcie *pci) { struct qcom_pcie *pcie =3D to_qcom_pcie(pci); + struct dw_pcie_port *port =3D list_first_entry(&pci->pp.ports, + struct dw_pcie_port, list); =20 - if (pcie_link_speed[pci->max_link_speed] =3D=3D PCIE_SPEED_16_0GT) { + if (pcie_link_speed[port->max_link_speed] =3D=3D PCIE_SPEED_16_0GT) { qcom_pcie_common_set_16gt_equalization(pci); qcom_pcie_common_set_16gt_lane_margining(pci); } diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/cont= roller/dwc/pcie-rcar-gen4.c index 18055807a4f5f9f1233097e1e47604a3555dccf0..f8c85984025a329b092c788dae2= 70911aec9c51f 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -132,6 +132,8 @@ static int rcar_gen4_pcie_speed_change(struct dw_pcie *= dw) static int rcar_gen4_pcie_start_link(struct dw_pcie *dw) { struct rcar_gen4_pcie *rcar =3D to_rcar_gen4_pcie(dw); + struct dw_pcie_port *port =3D list_first_entry(&dw->pp.ports, + struct dw_pcie_port, list); int i, changes, ret; =20 if (rcar->drvdata->ltssm_control) { @@ -144,7 +146,7 @@ static int rcar_gen4_pcie_start_link(struct dw_pcie *dw) * Require direct speed change with retrying here if the max_link_speed * is PCIe Gen2 or higher. */ - changes =3D min_not_zero(dw->max_link_speed, RCAR_MAX_LINK_SPEED) - 1; + changes =3D min_not_zero(port->max_link_speed, RCAR_MAX_LINK_SPEED) - 1; =20 /* * Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained. @@ -173,6 +175,8 @@ static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw) static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar) { struct dw_pcie *dw =3D &rcar->dw; + struct dw_pcie_port *port =3D list_first_entry(&dw->pp.ports, + struct dw_pcie_port, list); u32 val; int ret; =20 @@ -195,7 +199,7 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_= pcie *rcar) goto err_unprepare; } =20 - if (dw->num_lanes < 4) + if (port->num_lanes < 4) val |=3D BIFUR_MOD_SET_ON; =20 writel(val, rcar->base + PCIEMSR0); @@ -563,12 +567,15 @@ static int r8a779f0_pcie_ltssm_control(struct rcar_ge= n4_pcie *rcar, bool enable) static void rcar_gen4_pcie_additional_common_init(struct rcar_gen4_pcie *r= car) { struct dw_pcie *dw =3D &rcar->dw; + struct dw_pcie_port *port =3D list_first_entry(&dw->pp.ports, + struct dw_pcie_port, list); u32 val; =20 val =3D dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW); val &=3D ~PORT_LANE_SKEW_INSERT_MASK; - if (dw->num_lanes < 4) + if (port->num_lanes < 4) val |=3D BIT(6); + dw_pcie_writel_dbi(dw, PCIE_PORT_LANE_SKEW, val); =20 val =3D readl(rcar->base + PCIEPWRMNGCTRL); diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/cont= roller/dwc/pcie-spear13xx.c index 01794a9d3ad293419c9322ca53fe86036689b287..9221b37cc58ec75986bfc2898ab= 2879eee794cdc 100644 --- a/drivers/pci/controller/dwc/pcie-spear13xx.c +++ b/drivers/pci/controller/dwc/pcie-spear13xx.c @@ -191,6 +191,7 @@ static int spear13xx_pcie_probe(struct platform_device = *pdev) struct dw_pcie *pci; struct spear13xx_pcie *spear13xx_pcie; struct device_node *np =3D dev->of_node; + struct dw_pcie_port *port; int ret; =20 spear13xx_pcie =3D devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL); @@ -228,9 +229,9 @@ static int spear13xx_pcie_probe(struct platform_device = *pdev) dev_err(dev, "couldn't enable clk for pcie\n"); return ret; } - + port =3D list_first_entry(&pci->pp.ports, struct dw_pcie_port, list); if (of_property_read_bool(np, "st,pcie-is-gen1")) - pci->max_link_speed =3D 1; + port->max_link_speed =3D 1; =20 platform_set_drvdata(pdev, spear13xx_pcie); =20 diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 4f26086f25daf8e23cafbb2b460e1934734f4103..7b82c2509e966404892a29691f7= c21a27279b71f 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -957,6 +957,8 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *p= p) static int tegra_pcie_dw_start_link(struct dw_pcie *pci) { struct tegra_pcie_dw *pcie =3D to_tegra_pcie(pci); + struct dw_pcie_port *port =3D list_first_entry(&pci->pp.ports, + struct dw_pcie_port, list); struct dw_pcie_rp *pp =3D &pci->pp; u32 val, offset, tmp; bool retry =3D true; @@ -986,7 +988,7 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci) =20 msleep(100); =20 - if (dw_pcie_wait_for_link(pci)) { + if (dw_pcie_wait_for_link(pci, port)) { if (!retry) return 0; /* --=20 2.34.1