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Sun, 04 Jan 2026 08:23:40 -0800 (PST) From: Lisa Robinson To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Huacai Chen Cc: Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , WANG Xuerui , dapeng1.mi@linux.intel.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Lisa Robinson Subject: [PATCH v2] LoongArch: Fix PMU counter allocation for mixed-type event groups Date: Mon, 5 Jan 2026 00:23:04 +0800 Message-ID: <20260104162304.64604-1-lisa@bytefly.space> X-Mailer: git-send-email 2.52.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When validating a perf event group, validate_group() unconditionally attempts to allocate hardware PMU counters for the leader, sibling events and the new event being added. This is incorrect for mixed-type groups. If a PERF_TYPE_SOFTWARE event ispart of the group, the current code still tries to allocate a hardware PMU counter for it, which can wrongly consume hardware PMU resources and cause spurious allocation failures. Fix this by only allocating PMU counters for hardware events during group validation, and skipping software events. A trimmed down reproducer is as simple as this: #include #include #include #include #include #include int main (int argc, char *argv[]) { struct perf_event_attr attr =3D { 0 }; int fds[5]; attr.disabled =3D 1; attr.exclude_kernel =3D 1; attr.exclude_hv =3D 1; attr.read_format =3D PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_TOTAL_TIME_RUNNING | PERF_FORMAT_ID | PERF_FORMAT_GROUP; attr.size =3D sizeof (attr); attr.type =3D PERF_TYPE_SOFTWARE; attr.config =3D PERF_COUNT_SW_DUMMY; fds[0] =3D syscall (SYS_perf_event_open, &attr, 0, -1, -1, 0); assert (fds[0] >=3D 0); attr.type =3D PERF_TYPE_HARDWARE; attr.config =3D PERF_COUNT_HW_CPU_CYCLES; fds[1] =3D syscall (SYS_perf_event_open, &attr, 0, -1, fds[0], 0); assert (fds[1] >=3D 0); attr.type =3D PERF_TYPE_HARDWARE; attr.config =3D PERF_COUNT_HW_INSTRUCTIONS; fds[2] =3D syscall (SYS_perf_event_open, &attr, 0, -1, fds[0], 0); assert (fds[2] >=3D 0); attr.type =3D PERF_TYPE_HARDWARE; attr.config =3D PERF_COUNT_HW_BRANCH_MISSES; fds[3] =3D syscall (SYS_perf_event_open, &attr, 0, -1, fds[0], 0); assert (fds[3] >=3D 0); attr.type =3D PERF_TYPE_HARDWARE; attr.config =3D PERF_COUNT_HW_CACHE_REFERENCES; fds[4] =3D syscall (SYS_perf_event_open, &attr, 0, -1, fds[0], 0); assert (fds[4] >=3D 0); printf ("PASSED\n"); return 0; } Fixes: b37042b2bb7c ("LoongArch: Add perf events support") Signed-off-by: Lisa Robinson --- Changes in v2: - Factor out duplicated perf event type checks into an inline helper. --- arch/loongarch/kernel/perf_event.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/arch/loongarch/kernel/perf_event.c b/arch/loongarch/kernel/per= f_event.c index 9d257c8519c9..e34a6fb33e11 100644 --- a/arch/loongarch/kernel/perf_event.c +++ b/arch/loongarch/kernel/perf_event.c @@ -626,6 +626,18 @@ static const struct loongarch_perf_event *loongarch_pm= u_map_cache_event(u64 conf return pev; } =20 +static inline bool loongarch_pmu_event_requires_counter(const struct perf_= event *event) +{ + switch (event->attr.type) { + case PERF_TYPE_HARDWARE: + case PERF_TYPE_HW_CACHE: + case PERF_TYPE_RAW: + return true; + default: + return false; + } +} + static int validate_group(struct perf_event *event) { struct cpu_hw_events fake_cpuc; @@ -633,15 +645,18 @@ static int validate_group(struct perf_event *event) =20 memset(&fake_cpuc, 0, sizeof(fake_cpuc)); =20 - if (loongarch_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0) + if (loongarch_pmu_event_requires_counter(leader) && + loongarch_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0) return -EINVAL; =20 for_each_sibling_event(sibling, leader) { - if (loongarch_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0) + if (loongarch_pmu_event_requires_counter(sibling) && + loongarch_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0) return -EINVAL; } =20 - if (loongarch_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0) + if (loongarch_pmu_event_requires_counter(event) && + loongarch_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0) return -EINVAL; =20 return 0; --=20 2.52.0