From nobody Tue Feb 10 16:58:08 2026 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DC2B30E829 for ; Sat, 3 Jan 2026 15:24:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767453872; cv=none; b=ri/MxZEK+9F0BWd/MQQmGmsChGDEoxG/0yMMqVZUu7IENJU0sM1o1fHRK+62cAQTjgIOz4BarJkhYBi54dr1VF6sgXWE28tDfMKgWbNZHWOZAQIQAMPZ6LS9vGpt4C4kEKIfi9euuyR/fdUiEZwCrdpgc6y2udfMfXBn2X1ACe8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767453872; c=relaxed/simple; bh=66AeqSMa9PNTEYjXoFNL2B9ycnhwGzMh5GoWHyfpaPk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BnI3m6geoxpQSuiia1molAyh+U39TWyvZ34xsAkmeh2maBwr1K5mxalU36clkQId1jeOy08CoiRMWPlrYo+0g3YuQ3Lqz8VN75ndqpdueTPTlq9A05ZXwh7dGwfgO3gwSeQUCtXyaSNctjWcWBz/Ni67Olj4N5q4NvZsbp9a3VM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=JV59QbbQ; arc=none smtp.client-ip=209.85.214.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JV59QbbQ" Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-2a0eaf55d58so3486215ad.1 for ; Sat, 03 Jan 2026 07:24:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1767453869; x=1768058669; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rY+1CqHRW6wgOOvSa/xPbABDm4UWS4wzkJXrx4Ok40o=; b=JV59QbbQhwEc7gBnq5kz64TUi+3ZEvih5i1UI12hRRn5fjsPoNKdpBo5Iu+khqPzFQ p4MS6RPso+WJlBHrcvxVRpXfYlK8Ya7ay6nZe6ahK+qJoH7KU6Ryd0DhZx8HKeVMvfbV bOzRFUYy67p//2H0bXm9fpGoJoTKnx7zueeY0FtptC0MbkvjLbixnk2mlt4bESrS4I8V zdfGSySE9c8zblXY8xSG+EGiY163Z06sxm8QHy16rzqgCyr/zP6B560kBF34fTgyYyVB 9UKDaDsLMwid44D6keiC0h8h/iIwEV+fvZgA1M/z5GIQprF2oUCmgkjm+deSZ/3OEUVf Gutw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767453869; x=1768058669; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=rY+1CqHRW6wgOOvSa/xPbABDm4UWS4wzkJXrx4Ok40o=; b=l2fQU914icaRtQEhtcMU6UbUO8yh4nIOSHAQRgYj+hV0BjKYT+UanSJTfsZcmxH/vb +gGxaRfJzRTry8UymigqHnaiMNrrC+1IZUxjzX7aJ8a8Gtedmapj2v3s2afJ7VlXwPxL RhMDVS4pgWCFi1kUW+E9PNTjWMGHHnJMGNe3EZvh4VcVTej0XVsBC+Ypgk0ZDzmhiVXh 7O6sxOQsauuPJoxCeYdAel3khgRJXYZOsGT3a8dn3Zh0+Ps72Dp48ze0kFN2nvoFOw4C FNQI/r8o/OFN8NxBFv4eYKdc0EwoYI6pYwLs7/ze8BH3lm0bh6kAr88juVQZJAEZdBQD qThQ== X-Forwarded-Encrypted: i=1; AJvYcCVfCjj0xVcIDjBDeehJ5QUtdQb3gZb3SnMH8n5aD4k9ntHaxZjgCspFT7Y+/mJYsxEvCPnrzLbHR6SBI3o=@vger.kernel.org X-Gm-Message-State: AOJu0YwkbahwrTadceKGf0toT6MNpMlyWalWZHuWwm4MwCVE8wTecGox LYx2Ka+u6++2U0w8kBrLIx4I8mkzBsV/YgJVBgUjDW/vd5ksx8rm29RQVO62y/qSj50= X-Gm-Gg: AY/fxX61A7bLrYl+P6/PbfzZDmmu7PNfY/k725qpQYT3KmirdbmdxHwuwHBZmjiyzeg 5bHQN3sM/bzblxeiC8+zFVqWQCMJ62HDXfGhhN3pQ68M+4iKhRwEDV3TazWa8p6jMAJNFX9Cg2M zCxV3TQZGwoaI2BPrhc7S0b3dOwU0b6GR1fz+kUwiGXDvhYPMXK25HokLTSSOf76IjlRZOYYTcX T031Gi85SgbHKeR/3/2piCltFGQ3m5Cvqaa8dJxm/Yu4qExXDWERyrTATg3AKmoGt/rv9lDugub uPY27ePtYkP1lQ/ZbkdfOMWC810O2ETZe0K57dfIT1PG6krq5l778W4qxR1JU+2p3b6iwMfgOPz SBzUr0TM8JVVVvWdUm7njuaEK99ZIzvhIeRsw8KOI6R63endPwVSTJ30WAWhmAX76SzkZGWmabw qNw63/JnItWBtkvI+5Qm2C/x6xFLHuQxKok8jqGO/K57jFE5mlLLewyQP271Tm02G7tBvLZGDvY rk= X-Google-Smtp-Source: AGHT+IHlp9HPsn8fm7xK5iwgx3KOKWhA+7VN2RCvm7LTYT1W4zfwOzZOihBwzvrzDg7BywoDL8XQrw== X-Received: by 2002:a17:90b:3c8b:b0:32e:23c9:6f41 with SMTP id 98e67ed59e1d1-34f4537da08mr1903713a91.5.1767453869180; Sat, 03 Jan 2026 07:24:29 -0800 (PST) Received: from localhost.localdomain (123-48-16-240.area55c.commufa.jp. [123.48.16.240]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34f4770a256sm2107802a91.12.2026.01.03.07.24.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 03 Jan 2026 07:24:28 -0800 (PST) From: Naohiko Shimizu To: pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: alex@ghiti.fr, anup@brainfault.org, atish.patra@linux.dev, daniel.lezcano@linaro.org, tglx@linutronix.de, nick.hu@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Naohiko Shimizu Subject: [PATCH v2 1/3] riscv: clocksource: Fix stimecmp update hazard on RV32 Date: Sun, 4 Jan 2026 00:23:58 +0900 Message-Id: <20260103152400.552-2-naohiko.shimizu@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260103152400.552-1-naohiko.shimizu@gmail.com> References: <20260103152400.552-1-naohiko.shimizu@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Signed-off-by: Naohiko Shimizu riscv: fix timer register update hazard on RV32 On RV32, updating the 64-bit stimecmp (or vstimecmp) CSR requires two separate 32-bit writes. A race condition exists if the timer triggers during these two writes. The RISC-V Privileged Specification (e.g., Section 3.2.1 for mtimecmp) recommends a specific 3-step sequence to avoid spurious interrupts when updating 64-bit comparison registers on 32-bit systems: 1. Set the low-order bits (stimecmp) to all ones (ULONG_MAX). 2. Set the high-order bits (stimecmph) to the desired value. 3. Set the low-order bits (stimecmp) to the desired value. Current implementation writes the LSB first without ensuring a future value, which may lead to a transient state where the 64-bit comparison is incorrectly evaluated as "expired" by the hardware. This results in spurious timer interrupts. This patch adopts the spec-recommended 3-step sequence to ensure the intermediate 64-bit state is never smaller than the current time. --- drivers/clocksource/timer-riscv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-= riscv.c index 4d7cf338824a..cfc4d83c42c0 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -50,8 +50,9 @@ static int riscv_clock_next_event(unsigned long delta, =20 if (static_branch_likely(&riscv_sstc_available)) { #if defined(CONFIG_32BIT) - csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF); + csr_write(CSR_STIMECMP, ULONG_MAX); csr_write(CSR_STIMECMPH, next_tval >> 32); + csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF); #else csr_write(CSR_STIMECMP, next_tval); #endif --=20 2.39.5