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Fri, 02 Jan 2026 21:25:22 -0800 (PST) Received: from rockpi-5b ([45.112.0.8]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7ff7e48f258sm41658653b3a.47.2026.01.02.21.25.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jan 2026 21:25:21 -0800 (PST) From: Anand Moon To: Heiko Stuebner , Andi Shyti , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-i2c@vger.kernel.org (open list:I2C SUBSYSTEM HOST DRIVERS), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon , David Wu Subject: [PATCH v1] i2c: rk3x: Add support for SCL output enable debounce Date: Sat, 3 Jan 2026 10:55:04 +0530 Message-ID: <20260103052506.6743-1-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: David Wu As per the RK3399 and RK3588 datasheets Rockchip I2C controllers feature a SCL_OE_DB register (0x24). This register is used to configure the debounce time for the SCL output enable signal, which helps prevent glitches and ensures timing compliance during bus handover or slave clock stretching. Introduce a 'has_scl_oe_debounce' flag to rk3x_i2c_soc_data to distinguish between hardware versions. For supported SoCs, calculate the debounce counter dynamically based on the current clock rate and program it during divider adaptation. Signed-off-by: Anand Moon Signed-off-by: David Wu --- v1: This change have been pulled from linux-radxa kernel. --- drivers/i2c/busses/i2c-rk3x.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c index d4e9196445c0..31d7d6487613 100644 --- a/drivers/i2c/busses/i2c-rk3x.c +++ b/drivers/i2c/busses/i2c-rk3x.c @@ -35,6 +35,7 @@ #define REG_IEN 0x18 /* interrupt enable */ #define REG_IPD 0x1c /* interrupt pending */ #define REG_FCNT 0x20 /* finished count */ +#define REG_SCL_OE_DB 0x24 /* Slave hold scl debounce */ =20 /* Data buffer offsets */ #define TXBUFFER_BASE 0x100 @@ -164,6 +165,7 @@ enum rk3x_i2c_state { * @calc_timings: Callback function for i2c timing information calculated */ struct rk3x_i2c_soc_data { + bool has_scl_oe_debounce; int grf_offset; int (*calc_timings)(unsigned long, struct i2c_timings *, struct rk3x_i2c_calced_timings *); @@ -875,6 +877,7 @@ static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, un= signed long clk_rate) { struct i2c_timings *t =3D &i2c->t; struct rk3x_i2c_calced_timings calc; + unsigned long period, time_hold =3D (WAIT_TIMEOUT / 2) * 1000000; u64 t_low_ns, t_high_ns; unsigned long flags; u32 val; @@ -892,6 +895,13 @@ static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, u= nsigned long clk_rate) i2c_writel(i2c, val, REG_CON); i2c_writel(i2c, (calc.div_high << 16) | (calc.div_low & 0xffff), REG_CLKDIV); + + if (i2c->soc_data->has_scl_oe_debounce) { + period =3D DIV_ROUND_UP(1000000000, clk_rate); + val =3D DIV_ROUND_UP(time_hold, period); + i2c_writel(i2c, val, REG_SCL_OE_DB); + } + spin_unlock_irqrestore(&i2c->lock, flags); =20 clk_disable(i2c->pclk); @@ -1198,6 +1208,7 @@ static const struct rk3x_i2c_soc_data rk3288_soc_data= =3D { static const struct rk3x_i2c_soc_data rk3399_soc_data =3D { .grf_offset =3D -1, .calc_timings =3D rk3x_i2c_v1_calc_timings, + .has_scl_oe_debounce =3D true, }; =20 static const struct of_device_id rk3x_i2c_match[] =3D { base-commit: 805f9a061372164d43ddef771d7cd63e3ba6d845 --=20 2.50.1