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Fri, 02 Jan 2026 21:57:23 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34f475f1726sm754760a91.4.2026.01.02.21.57.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jan 2026 21:57:23 -0800 (PST) From: Taniya Das Date: Sat, 03 Jan 2026 11:27:06 +0530 Subject: [PATCH v2 2/3] clk: qcom: gcc-x1e80100: Add missing UFS symbol mux clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260103-ufs_symbol_clk-v2-2-51828cc76236@oss.qualcomm.com> References: <20260103-ufs_symbol_clk-v2-0-51828cc76236@oss.qualcomm.com> In-Reply-To: <20260103-ufs_symbol_clk-v2-0-51828cc76236@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rajendra Nayak , Abel Vesa , Konrad Dybcio , Bryan O'Donoghue Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sibi Sankar , Pradeep P V K , Taniya Das , Abel Vesa X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-GUID: hlw7sulr0BFdlTQ3TB04MWaLb2_EZTga X-Proofpoint-ORIG-GUID: hlw7sulr0BFdlTQ3TB04MWaLb2_EZTga X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTAzMDA1MiBTYWx0ZWRfX57eywwiwnvGg oMUy1nBqN5XXzoJInBK/0KT4SEiST+tTBGQt5P1zUdoRX31QO4c5SKYFLYKyazLVsFL8aIi4Ikb VMbVGvXSw/KiADmWA8SwtNCGghpL4+Tu1iHUXMDn2X31RH53DfW44G6Co3FgJPYFPtoEKlp8H+9 MqaYM8xHzLmYfq5weCG0yxm0luBp0ha2hJIQu7zCNlsfwzb0zhFHo2Sulyy00lHpvYDhbgpC42w Mjz9Zbq+Efver2z+eA6a6VD9Z3F7o5ws4YLy2dnYQ4m7/4zQLnpxsgkTJ1MdrosgNj6Gir0zi3e O+x9Oj+zGEjjpLhwSnLg4C4WxUc/WRGMbY9RTFG0j0pj50zycvFwMqR2Z44RqE4cR5H9oZVZFzp IT41zWPl6/emZACCRV2e8B2OZXkvAzxA08R5BYwt8malWl624qJhuHO430wpIef99Dte1WuYSqy 1QvFyo98vXLu38Hq42A== X-Authority-Analysis: v=2.4 cv=GNkF0+NK c=1 sm=1 tr=0 ts=6958afc5 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=F9uGy5JsO3lP6kdW_XMA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-02_04,2025-12-31_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601030052 The UFS symbol RX/TX mux clocks were not defined previously. Add these mux clocks so that clock rate propagation reaches the muxes correctly. Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver f= or X1E80100") Reviewed-by: Abel Vesa Signed-off-by: Taniya Das Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-x1e80100.c | 72 +++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 69 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e8010= 0.c index e46e65e631513e315de2f663f3dab73e1eb70604..74afd12c158c01c121d9aecd56e= 65c0c302d7cd0 100644 --- a/drivers/clk/qcom/gcc-x1e80100.c +++ b/drivers/clk/qcom/gcc-x1e80100.c @@ -59,6 +59,9 @@ enum { DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, + DT_UFS_PHY_RX_SYMBOL_0_CLK, + DT_UFS_PHY_RX_SYMBOL_1_CLK, + DT_UFS_PHY_TX_SYMBOL_0_CLK, }; =20 enum { @@ -103,6 +106,9 @@ enum { P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, + P_UFS_PHY_RX_SYMBOL_0_CLK, + P_UFS_PHY_RX_SYMBOL_1_CLK, + P_UFS_PHY_TX_SYMBOL_0_CLK, }; =20 static struct clk_alpha_pll gcc_gpll0 =3D { @@ -482,6 +488,48 @@ static const struct clk_parent_data gcc_parent_data_33= [] =3D { { .index =3D DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK }, }; =20 +static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_0_clk_src =3D { + .reg =3D 0x77064, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_rx_symbol_0_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_UFS_PHY_RX_SYMBOL_0_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_1_clk_src =3D { + .reg =3D 0x770e0, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_rx_symbol_1_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_UFS_PHY_RX_SYMBOL_1_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_ufs_phy_tx_symbol_0_clk_src =3D { + .reg =3D 0x77054, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_tx_symbol_0_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_UFS_PHY_TX_SYMBOL_0_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp0_clk_src =3D { .reg =3D 0x9f06c, .clkr =3D { @@ -5148,12 +5196,17 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = =3D { =20 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk =3D { .halt_reg =3D 0x7702c, - .halt_check =3D BRANCH_HALT, + .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { .enable_reg =3D 0x7702c, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_ufs_phy_rx_symbol_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5161,12 +5214,17 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_cl= k =3D { =20 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk =3D { .halt_reg =3D 0x770cc, - .halt_check =3D BRANCH_HALT, + .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { .enable_reg =3D 0x770cc, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_ufs_phy_rx_symbol_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5174,12 +5232,17 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_1_cl= k =3D { =20 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk =3D { .halt_reg =3D 0x77028, - .halt_check =3D BRANCH_HALT, + .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { .enable_reg =3D 0x77028, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_ufs_phy_tx_symbol_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -7180,6 +7243,9 @@ static struct clk_regmap *gcc_x1e80100_clocks[] =3D { [GCC_USB4_2_TMU_CLK_SRC] =3D &gcc_usb4_2_tmu_clk_src.clkr, [GCC_VIDEO_AXI0_CLK] =3D &gcc_video_axi0_clk.clkr, [GCC_VIDEO_AXI1_CLK] =3D &gcc_video_axi1_clk.clkr, + [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] =3D &gcc_ufs_phy_rx_symbol_0_clk_src.cl= kr, + [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] =3D &gcc_ufs_phy_rx_symbol_1_clk_src.cl= kr, + [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] =3D &gcc_ufs_phy_tx_symbol_0_clk_src.cl= kr, }; =20 static struct gdsc *gcc_x1e80100_gdscs[] =3D { --=20 2.34.1