From nobody Sat Feb 7 18:00:43 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DACDD1D88A4; Fri, 2 Jan 2026 17:02:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767373355; cv=none; b=IIk14HGImNjWthYeddrCu4QthYKY3YLtfxii9NcpbtbIGfXZiToexUTbxXDbjm989qHWz0rjs0MUl7SeWRJI4kY9p4YzGHYJxL/HQwwOQKj+m8WyXxloO4yyAAqw9tKYmQXmV9xh9xZixQnIDuN+oZHHR3/s+rKMiPVCzXYccU4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767373355; c=relaxed/simple; bh=b2FcMDI/Onb6TJ2aAIjlXHZ4EvhM59xQTjBh6PFYK+8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gn/+w+83p5gT/fe1uDI4V+653mY5k11Pvh3ND/gkoGvGRJ7ioPiI7DED6ESpSnOPIUVBZnXxsBTkmFfPRbVg1qVu4aMgQrJTTPd04gH2sDOt+ZSjtFs+iYO6ZuUBpuQQRi/KpZUDNjYFjCXTtgo4qzgF5t7J6tsdamTCPUmNOMw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=v9PIpiBM; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="v9PIpiBM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1767373352; x=1798909352; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=b2FcMDI/Onb6TJ2aAIjlXHZ4EvhM59xQTjBh6PFYK+8=; b=v9PIpiBMXIEb4wuyuC6usniS/opNy2qSA6WapTg8iXlE4SAigQ8UlsdI yRbsVkh8Z5tY1JH5OiJ78dU0FFcHBIDiweHRnljFT0xbgoE2s9adDslmc ec0mbF5P3Z6KYLc8nX+9taxp+dkchvr4bmQoKm8WnsWohPtnlcPz/EURQ 5x5TuzTuUbEVkWcsDn7BJ8ZqdEpOdgL/Jj9XPBkHeLMaimjogYXJ2Evq8 giUi1ApQM1Ut9vxKxFDIv87cL+IyAzSCKoeTHVodlXSZKty3q9se2K5cT ic9uzN4dIq5G7wvcVNwqNqv79LTx9YK7g39j0Y8qG8SAjHVBc3PS/LgUJ w==; X-CSE-ConnectionGUID: AQIGzmznQ9aRzmgEiLNGFw== X-CSE-MsgGUID: C2HUDPFbRKOMTMajxM987w== X-IronPort-AV: E=Sophos;i="6.21,197,1763449200"; d="scan'208";a="282656849" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 02 Jan 2026 10:02:32 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 2 Jan 2026 10:01:38 -0700 Received: from ROU-LL-M43238.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 2 Jan 2026 10:01:35 -0700 From: To: , CC: Alexandre Belloni , Claudiu Beznea , Balamanikandan Gunasundar , Ryan Wanner , Conor Dooley , "Hari Prasath Gujulan Elango" , Subject: [PATCH 1/5] ARM: dts: microchip: sama7d65: fix the ranges property for flx9 Date: Fri, 2 Jan 2026 18:01:30 +0100 Message-ID: <20260102170135.70717-2-nicolas.ferre@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260102170135.70717-1-nicolas.ferre@microchip.com> References: <20260102170135.70717-1-nicolas.ferre@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hari Prasath Gujulan Elango Update the ranges property for the flexcom9 as per the datasheet and align with the reg property. Fixes: b51e4aea3ecf ("ARM: dts: microchip: sama7d65: Add FLEXCOMs to sama7d= 65 SoC") Cc: # 6.16+ Signed-off-by: Hari Prasath Gujulan Elango Signed-off-by: Nicolas Ferre --- Note: Hari's email address will bounce. Change to whichever suits you. arch/arm/boot/dts/microchip/sama7d65.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index cd2cf9a6f40b..5f3a7b178aa7 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -676,7 +676,7 @@ i2c8: i2c@600 { flx9: flexcom@e2820000 { compatible =3D "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; reg =3D <0xe2820000 0x200>; - ranges =3D <0x0 0xe281c000 0x800>; + ranges =3D <0x0 0xe2820000 0x800>; clocks =3D <&pmc PMC_TYPE_PERIPHERAL 43>; #address-cells =3D <1>; #size-cells =3D <1>; --=20 2.43.0 From nobody Sat Feb 7 18:00:43 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A928425392D; Fri, 2 Jan 2026 17:02:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767373380; cv=none; b=feGW7ByR7iks+/y+CANV1MnBSkFbOYSIOvYnjXAOrZZsFga6d1ppcnH1DC1rRsCIQt8zg87PEYONQESDdIFxLnj0QKarMGEdhedKtuEVb1jn2C5D1VIcejxdBSiqvb4oq2RmtAdnpJmDR2tUbpCfrhRVxZ4zKr8WiU7TiF625vk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767373380; c=relaxed/simple; bh=ZY+Hrf2RDJpz96DFkZH7AD1GmvyE3tVeKZ338mKSv/g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qRcCDuwaUhhGmQXh3xWtHNhwiFyRcZz44WazJZ01o8OwvVjTZ5R/RVFWgOBLZTN10D11N/tpTn2i68RzwlIBf23F9kmFBs9ThZUTLO2U4SfwVtC+QQxeDS7Si5R3IQFMXYUs3//ZlV7yQRSnV2bfWKB78ntyf371S/mqFnJT2Do= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=AIKbvIxx; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="AIKbvIxx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1767373378; x=1798909378; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZY+Hrf2RDJpz96DFkZH7AD1GmvyE3tVeKZ338mKSv/g=; b=AIKbvIxxFoaSFYaxptcrQZe27PeetMMINJcuYCF9e3bU1LV5CQlV6ENB s+lb7LdQIScwnFJPdPpBUzDxec50yek4/GtHvZFeXNWJxMXVTSmbnAKXV RPzP99nIfMnSJUFsDKnAusLtKomHvqC+tmsl7c7reCmMHgxpeKQAnHAMt TLBV6COUx1Yse80OtbuDRamAdZD2zleVSrQmUajxGNBAff0Uh48tHtdPU NUVC5bTxhUim4sG0Ild/Lf410iMpmFVeyGFmanx8ScI6J9m1mjWVZlIfL 9Uv8kr0JEOMHKRm9dP5+t0J75tP4fxcnq1LhRG0+YrLS2ddP9Fek1iSJR Q==; X-CSE-ConnectionGUID: dCrVUlstT/WCgDlJ76zoeQ== X-CSE-MsgGUID: bmfnSXGJRcikdFj1WZvODw== X-IronPort-AV: E=Sophos;i="6.21,197,1763449200"; d="scan'208";a="58167746" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2026 10:01:48 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.87.71) by chn-vm-ex1.mchp-main.com (10.10.87.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.29; Fri, 2 Jan 2026 10:01:40 -0700 Received: from ROU-LL-M43238.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 2 Jan 2026 10:01:38 -0700 From: To: , CC: Alexandre Belloni , Claudiu Beznea , Balamanikandan Gunasundar , Ryan Wanner , Conor Dooley , Nicolas Ferre , Subject: [PATCH 2/5] ARM: dts: microchip: sama7d65: fix size-cells property for i2c3 Date: Fri, 2 Jan 2026 18:01:31 +0100 Message-ID: <20260102170135.70717-3-nicolas.ferre@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260102170135.70717-1-nicolas.ferre@microchip.com> References: <20260102170135.70717-1-nicolas.ferre@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolas Ferre Fix the #size-cells property for i2c3 node and remove the dtbs_check error telling that "#size-cells: 0 was expected" from schema atmel,at91sam-i2c.yaml and i2c-controller.yaml. Fixes: b51e4aea3ecf ("ARM: dts: microchip: sama7d65: Add FLEXCOMs to sama7d= 65 SoC") Cc: # 6.16+ Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index 5f3a7b178aa7..868045c650a7 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -527,7 +527,7 @@ i2c3: i2c@600 { interrupts =3D ; clocks =3D <&pmc PMC_TYPE_PERIPHERAL 37>; #address-cells =3D <1>; - #size-cells =3D <1>; + #size-cells =3D <0>; dmas =3D <&dma0 AT91_XDMAC_DT_PERID(12)>, <&dma0 AT91_XDMAC_DT_PERID(11)>; dma-names =3D "tx", "rx"; --=20 2.43.0 From nobody Sat Feb 7 18:00:43 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 522A052F88 for ; Fri, 2 Jan 2026 17:02:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767373336; cv=none; b=LAUsMVw7x6tYYG5MAZpVru2DyiLGltpyoJH7223J5e2pjTK4mMNFoIUDJvGO9kg+gPKVYR3wZ+WkW7IKPFjyw860WvLGNCgWWhcgNewVqkZptBiwRWpucgi4QbpPx7WSxb2dRG4s9agfEzOEUPcB0nkCY/MwNNIvwRkji4i18bQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767373336; c=relaxed/simple; bh=UCIBeIMlpa51KZ2u7c6Wg6I0vI29KQaQ4gNKmKjxJFo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=f8qupgLtpRXOCXr2sYsD3T77o50WUFpmsb93B+t3aUzEPAdYF4pqxbykGsJxkLzUpPFS7cJqKUc2tYM/RYs5w5Ok96X9uGttSfTRELTxpQSStuqhs5+evLOZAP9aUYDt8lpMkVZ6QGpuLLWwbDTDlcyPlV3eWr+wuTi9KJC9DkQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=UkNzuyqN; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="UkNzuyqN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1767373335; x=1798909335; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UCIBeIMlpa51KZ2u7c6Wg6I0vI29KQaQ4gNKmKjxJFo=; b=UkNzuyqNmNg1RV+glrxRJE8twhi+c7eRT3u2TkXfkff3IAhDLOB4Bqbw Cn41mbRn6bMkuvolA/1fBCg7s1OnLTpgkHh1IFBT0bWQFry1BqAgaTK1j 53PvhraOZxlhdXnkiHWYvcm0WtIj86yivmd1qEW/GWwgYT9jugvVS+i7/ dhJM5b7qQslxqpPUBc1DR23N9y7ScG1aRwOIv1WSDH6O5JrZi8wS+wM1l xnKP8Ksl7VdnkePiXqPWkZtqMOW9lSN/XfTfp7cBX+EWFOsLv4tPWKoJs KeVyyHzen82I2trB8Y3fYzuQRxmfKfVn/iG1Vb/kaaEUJP88YPAcP7RBs Q==; X-CSE-ConnectionGUID: EEzKUSBWSiqVSkiAY+YL6g== X-CSE-MsgGUID: qsVbTFbYRmWR1u4sO4P7ew== X-IronPort-AV: E=Sophos;i="6.21,197,1763449200"; d="scan'208";a="50579717" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 02 Jan 2026 10:02:13 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 2 Jan 2026 10:01:42 -0700 Received: from ROU-LL-M43238.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 2 Jan 2026 10:01:40 -0700 From: To: , CC: Alexandre Belloni , Claudiu Beznea , Balamanikandan Gunasundar , Ryan Wanner , Conor Dooley , Nicolas Ferre Subject: [PATCH 3/5] ARM: dts: microchip: sama7d65: add dma properties to usart6 Date: Fri, 2 Jan 2026 18:01:32 +0100 Message-ID: <20260102170135.70717-4-nicolas.ferre@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260102170135.70717-1-nicolas.ferre@microchip.com> References: <20260102170135.70717-1-nicolas.ferre@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolas Ferre Add the dma property and associated dma activation for usart6 as part of flx6 node. Is useful for usual default console on this product. Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index 868045c650a7..92d92228f0a5 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -617,6 +617,11 @@ uart6: serial@200 { interrupts =3D ; clocks =3D <&pmc PMC_TYPE_PERIPHERAL 40>; clock-names =3D "usart"; + dmas =3D <&dma1 AT91_XDMAC_DT_PERID(18)>, + <&dma1 AT91_XDMAC_DT_PERID(17)>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; atmel,usart-mode =3D ; atmel,fifo-size =3D <32>; status =3D "disabled"; --=20 2.43.0 From nobody Sat Feb 7 18:00:43 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B3DC176ADE for ; Fri, 2 Jan 2026 17:02:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767373337; cv=none; b=rPbdgUcbGQ84hNox7SSZ1xzjdXlq4hXngsH2p9gf+vCiLGKoI5Xuw8G0oUECPK4RnUz8uCXMiwbD5Lf7mfskZXUIpHY5rOYFJeXWFjwX7bftvXDUnbz25BnMe0MuFo2MC4S73WBoyLQ7yEqawIWFo5rDoChNaHvdUr/kNSc/2IM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767373337; c=relaxed/simple; bh=GO9TkFTYYc1lAE3J6mL7TFl1uMGeLRAzDYmt1vk20x4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=e0s5MLmLo1NUVWmS9IF8aVAYjbEcgTCU90OBLF8J0EASujtMMDZf0FhAAjGupPAuIgdFiDEEW3N5rqaodrvm80uLzTRNalbn8xErUP3mS+GkJJZP8Tttgy/LAfogQ2kWMkINbXkPh9XF5Gqi9ojQrjq9Pw9IbFpweL+SsYGrSoQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=RLQxHQH/; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="RLQxHQH/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1767373336; x=1798909336; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GO9TkFTYYc1lAE3J6mL7TFl1uMGeLRAzDYmt1vk20x4=; b=RLQxHQH/42qxwi2WKIjUlB/7FDizHgzkx7JXnsN7MWgmu310GNgK7fxZ iCoFAGE9RC2gk0ErPNdk4NF78iPzzzOX/DCgJenyGUanTzlmfm3bFbfhk mhtJEarofbeFzdjMU4dLOXYg1NoDrD/J9RBJcT/8cdk9AtuD9jQpFoqOt KaHvp6TvSppsI7n3a0k28FKxa8SgIY42AoiyVpS0VXNujEpjVHOOVN0iH 5E5tSWFHCIxeImc0Hg0uQa7FgOnJd7hmamTGrzjArfPAIG3ELVfqyBLKr UV8HmC5cM6U3T4LWEc9qZoIDQEuMZbW8RiQBie633HLD6LRy+BNWcTIYF A==; X-CSE-ConnectionGUID: AoVct/fNRmqflI0xS4d9hg== X-CSE-MsgGUID: nSu8DN4iQ0uHNgj2X+ahCA== X-IronPort-AV: E=Sophos;i="6.21,197,1763449200"; d="scan'208";a="58167787" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 02 Jan 2026 10:02:15 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Fri, 2 Jan 2026 10:01:45 -0700 Received: from ROU-LL-M43238.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 2 Jan 2026 10:01:43 -0700 From: To: , CC: Alexandre Belloni , Claudiu Beznea , Balamanikandan Gunasundar , Ryan Wanner , Conor Dooley , Nicolas Ferre Subject: [PATCH 4/5] ARM: dts: microchip: sama7d65: add fifo-size to usart Date: Fri, 2 Jan 2026 18:01:33 +0100 Message-ID: <20260102170135.70717-5-nicolas.ferre@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260102170135.70717-1-nicolas.ferre@microchip.com> References: <20260102170135.70717-1-nicolas.ferre@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolas Ferre When missing, add the atmel,fifo-size =3D <32> property for usart nodes in flexcom. Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index 92d92228f0a5..82781a1dbd6d 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -414,6 +414,7 @@ uart0: serial@200 { dma-names =3D "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; + atmel,fifo-size =3D <32>; atmel,usart-mode =3D ; status =3D "disabled"; }; @@ -492,6 +493,7 @@ uart2: serial@200 { dma-names =3D "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; + atmel,fifo-size =3D <32>; atmel,usart-mode =3D ; status =3D "disabled"; }; @@ -517,6 +519,7 @@ uart3: serial@200 { dma-names =3D "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; + atmel,fifo-size =3D <32>; atmel,usart-mode =3D ; status =3D "disabled"; }; --=20 2.43.0 From nobody Sat Feb 7 18:00:43 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43D75269B01 for ; Fri, 2 Jan 2026 17:02:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767373381; cv=none; b=CX/UM8sx4gnNeFwwp5i2rgYStCUq2s0/SeZGpCp1lrOpb6+SPTToSdBZ8id/vKiU3lK73vy/vfBY2Yixf/r0jqnf4RDMKSDsLczTHsW0YDQltrQGfIuJgoLL2wTrhEVHfqI/u04bekx63LaD0oWvEJ2HbxWvTUhpICViDYyxc1k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767373381; c=relaxed/simple; bh=m2csuiSvqhqW6MbfpzWu0Dpjoi7rMVe0Q1kp+hepEd8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=W+8L48gAwgIHJqpMItqzEUUAPt43PtCHunksI2LKM9WYuduwOI+mbwGv/h9e54pL9yOW6n53MeYF6hRA0WiENLUwI6LgJkKkSoah4q7/leRPyfRKhMhA1+su75BgHK+M1nNx0U2lsRMh52aYtgJ87bVTMU7j2y9FWzyniV+y6YA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=erwNQOZh; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="erwNQOZh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1767373379; x=1798909379; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=m2csuiSvqhqW6MbfpzWu0Dpjoi7rMVe0Q1kp+hepEd8=; b=erwNQOZhPgu0YQOOYdpFYbf4kPfz4wQyJh/2cgTNUgp5ocF+O+1oJexN PO2ChvnhgrfQpIK2ch0lgrCyNdzHyxTbowPQmmcjYy5LygMBVwen81jSR 3KnBh7l+S78Vn/BNtz1PjjfTve4fBpTfOanMk0W/E1qOS2oniYCRwTeZ/ 0vT8t+5cTf2jntw1373eAqVzvLW8/M+eYKJlxaW7NxOH0yW7zppkfZ0tM qCH7gUL/DhLchyc5YJpymAWNf8h4gNdzCDxxIL8Enh8vUyrS9q6mpzHR4 AfSas23N8bx6vvd0SqOYPyylnGomYSJcEpIL/LOd65a8iE2eOyhCQH2Ll g==; X-CSE-ConnectionGUID: dCrVUlstT/WCgDlJ76zoeQ== X-CSE-MsgGUID: TW1raM+mT9+5b5vAwHyAaQ== X-IronPort-AV: E=Sophos;i="6.21,197,1763449200"; d="scan'208";a="58167748" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jan 2026 10:01:48 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.87.71) by chn-vm-ex1.mchp-main.com (10.10.87.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.29; Fri, 2 Jan 2026 10:01:47 -0700 Received: from ROU-LL-M43238.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Fri, 2 Jan 2026 10:01:45 -0700 From: To: , CC: Alexandre Belloni , Claudiu Beznea , Balamanikandan Gunasundar , Ryan Wanner , Conor Dooley , Nicolas Ferre Subject: [PATCH 5/5] ARM: dts: microchip: sama7d65: add missing flexcom nodes Date: Fri, 2 Jan 2026 18:01:34 +0100 Message-ID: <20260102170135.70717-6-nicolas.ferre@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260102170135.70717-1-nicolas.ferre@microchip.com> References: <20260102170135.70717-1-nicolas.ferre@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nicolas Ferre Add nodes for usart, spi and i2c when missing to the flexcom nodes. Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 271 ++++++++++++++++++++++ 1 file changed, 271 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index 82781a1dbd6d..e21556f46384 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -419,6 +419,21 @@ uart0: serial@200 { status =3D "disabled"; }; =20 + spi0: spi@400 { + compatible =3D "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 34>; + clock-names =3D "spi_clk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + dmas =3D <&dma1 AT91_XDMAC_DT_PERID(6)>, + <&dma1 AT91_XDMAC_DT_PERID(5)>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; + i2c0: i2c@600 { compatible =3D "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; reg =3D <0x600 0x200>; @@ -443,6 +458,22 @@ flx1: flexcom@e1824000 { #size-cells =3D <1>; status =3D "disabled"; =20 + uart1: serial@200 { + compatible =3D "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 35>; + clock-names =3D "usart"; + dmas =3D <&dma0 AT91_XDMAC_DT_PERID(8)>, + <&dma0 AT91_XDMAC_DT_PERID(7)>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <32>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + spi1: spi@400 { compatible =3D "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; reg =3D <0x400 0x200>; @@ -497,6 +528,35 @@ uart2: serial@200 { atmel,usart-mode =3D ; status =3D "disabled"; }; + + spi2: spi@400 { + compatible =3D "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 36>; + clock-names =3D "spi_clk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + dmas =3D <&dma1 AT91_XDMAC_DT_PERID(10)>, + <&dma1 AT91_XDMAC_DT_PERID(9)>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; + + i2c2: i2c@600 { + compatible =3D "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 36>; + #address-cells =3D <1>; + #size-cells =3D <0>; + dmas =3D <&dma1 AT91_XDMAC_DT_PERID(10)>, + <&dma1 AT91_XDMAC_DT_PERID(9)>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; }; =20 flx3: flexcom@e182c000 { @@ -524,6 +584,21 @@ uart3: serial@200 { status =3D "disabled"; }; =20 + spi3: spi@400 { + compatible =3D "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 37>; + clock-names =3D "spi_clk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + dmas =3D <&dma0 AT91_XDMAC_DT_PERID(12)>, + <&dma0 AT91_XDMAC_DT_PERID(11)>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; + i2c3: i2c@600 { compatible =3D "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; reg =3D <0x600 0x200>; @@ -579,6 +654,20 @@ spi4: spi@400 { atmel,fifo-size =3D <32>; status =3D "disabled"; }; + + i2c4: i2c@600 { + compatible =3D "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 38>; + #address-cells =3D <1>; + #size-cells =3D <0>; + dmas =3D <&dma1 AT91_XDMAC_DT_PERID(14)>, + <&dma1 AT91_XDMAC_DT_PERID(13)>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; }; =20 flx5: flexcom@e201c000 { @@ -590,6 +679,37 @@ flx5: flexcom@e201c000 { #size-cells =3D <1>; status =3D "disabled"; =20 + uart5: serial@200 { + compatible =3D "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 39>; + clock-names =3D "usart"; + dmas =3D <&dma0 AT91_XDMAC_DT_PERID(16)>, + <&dma0 AT91_XDMAC_DT_PERID(15)>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <32>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi5: spi@400 { + compatible =3D "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 39>; + clock-names =3D "spi_clk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + dmas =3D <&dma0 AT91_XDMAC_DT_PERID(16)>, + <&dma0 AT91_XDMAC_DT_PERID(15)>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; + i2c5: i2c@600 { compatible =3D "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; reg =3D <0x600 0x200>; @@ -629,6 +749,35 @@ uart6: serial@200 { atmel,fifo-size =3D <32>; status =3D "disabled"; }; + + spi6: spi@400 { + compatible =3D "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 40>; + clock-names =3D "spi_clk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + dmas =3D <&dma1 AT91_XDMAC_DT_PERID(18)>, + <&dma1 AT91_XDMAC_DT_PERID(17)>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; + + i2c6: i2c@600 { + compatible =3D "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 40>; + #address-cells =3D <1>; + #size-cells =3D <0>; + dmas =3D <&dma1 AT91_XDMAC_DT_PERID(18)>, + <&dma1 AT91_XDMAC_DT_PERID(17)>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; }; =20 flx7: flexcom@e2024000 { @@ -655,6 +804,35 @@ uart7: serial@200 { atmel,usart-mode =3D ; status =3D "disabled"; }; + + spi7: spi@400 { + compatible =3D "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 41>; + clock-names =3D "spi_clk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + dmas =3D <&dma1 AT91_XDMAC_DT_PERID(20)>, + <&dma1 AT91_XDMAC_DT_PERID(19)>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; + + i2c7: i2c@600 { + compatible =3D "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 41>; + #address-cells =3D <1>; + #size-cells =3D <0>; + dmas =3D <&dma1 AT91_XDMAC_DT_PERID(20)>, + <&dma1 AT91_XDMAC_DT_PERID(19)>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; }; =20 flx8: flexcom@e281c000 { @@ -666,6 +844,37 @@ flx8: flexcom@e281c000 { #size-cells =3D <1>; status =3D "disabled"; =20 + uart8: serial@200 { + compatible =3D "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 42>; + clock-names =3D "usart"; + dmas =3D <&dma0 AT91_XDMAC_DT_PERID(22)>, + <&dma0 AT91_XDMAC_DT_PERID(21)>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <32>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi8: spi@400 { + compatible =3D "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 42>; + clock-names =3D "spi_clk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + dmas =3D <&dma0 AT91_XDMAC_DT_PERID(22)>, + <&dma0 AT91_XDMAC_DT_PERID(21)>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; + i2c8: i2c@600 { compatible =3D "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; reg =3D <0x600 0x200>; @@ -690,6 +899,37 @@ flx9: flexcom@e2820000 { #size-cells =3D <1>; status =3D "disabled"; =20 + uart9: serial@200 { + compatible =3D "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 43>; + clock-names =3D "usart"; + dmas =3D <&dma0 AT91_XDMAC_DT_PERID(24)>, + <&dma0 AT91_XDMAC_DT_PERID(23)>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <32>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi9: spi@400 { + compatible =3D "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 43>; + clock-names =3D "spi_clk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + dmas =3D <&dma0 AT91_XDMAC_DT_PERID(24)>, + <&dma0 AT91_XDMAC_DT_PERID(23)>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; + i2c9: i2c@600 { compatible =3D "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; reg =3D <0x600 0x200>; @@ -714,6 +954,37 @@ flx10: flexcom@e2824000 { #size-cells =3D <1>; status =3D "disabled"; =20 + uart10: serial@200 { + compatible =3D "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 44>; + clock-names =3D "usart"; + dmas =3D <&dma0 AT91_XDMAC_DT_PERID(26)>, + <&dma0 AT91_XDMAC_DT_PERID(25)>; + dma-names =3D "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size =3D <32>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi10: spi@400 { + compatible =3D "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 44>; + clock-names =3D "spi_clk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + dmas =3D <&dma0 AT91_XDMAC_DT_PERID(26)>, + <&dma0 AT91_XDMAC_DT_PERID(25)>; + dma-names =3D "tx", "rx"; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; + i2c10: i2c@600 { compatible =3D "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; reg =3D <0x600 0x200>; --=20 2.43.0