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Fri, 02 Jan 2026 05:18:29 -0800 (PST) Received: from rockpi-5b ([45.112.0.8]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c1e7961e039sm35278770a12.7.2026.01.02.05.18.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jan 2026 05:18:29 -0800 (PST) From: Anand Moon To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Niklas Cassel , Shawn Lin , Hans Zhang <18255117159@163.com>, Nicolas Frattaroli , linux-pci@vger.kernel.org (open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Rockchip SoC support), linux-rockchip@lists.infradead.org (open list:ARM/Rockchip SoC support), linux-kernel@vger.kernel.org (open list) Cc: Anand Moon Subject: [PATCH v2] PCI: dw-rockchip: Add runtime PM support to Rockchip PCIe Date: Fri, 2 Jan 2026 18:47:50 +0530 Message-ID: <20260102131819.123745-1-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add runtime powwe manageement functionality into the Rockchip DesignWare PCIe controller driver. Calling devm_pm_runtime_enable() during device probing allows the controller to report its runtime PM status, enabling power management controls to be applied consistently across the entire connected PCIe hierarchy. Signed-off-by: Anand Moon --- v2: improve the commit message Drop the .remove patch Drop the disable_pm_runtime v1: https://lore.kernel.org/all/20251027145602.199154-3-linux.amoon@gmail.com/ --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index f8605fe61a415..2498ff5146a5a 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include =20 @@ -709,6 +710,20 @@ static int rockchip_pcie_probe(struct platform_device = *pdev) if (ret) goto deinit_phy; =20 + ret =3D pm_runtime_set_suspended(dev); + if (ret) + goto deinit_clk; + + ret =3D devm_pm_runtime_enable(dev); + if (ret) { + ret =3D dev_err_probe(dev, ret, "Failed to enable runtime PM\n"); + goto deinit_clk; + } + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + goto deinit_clk; + switch (data->mode) { case DW_PCIE_RC_TYPE: ret =3D rockchip_pcie_configure_rc(pdev, rockchip); @@ -730,6 +745,8 @@ static int rockchip_pcie_probe(struct platform_device *= pdev) =20 deinit_clk: clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks); + pm_runtime_disable(dev); + pm_runtime_no_callbacks(dev); deinit_phy: rockchip_pcie_phy_deinit(rockchip); =20 base-commit: b69053dd3ffbc0d2dedbbc86182cdef6f641fe1b --=20 2.50.1