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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2026 08:55:20.0887 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0abf7fac-300f-45fa-4322-08de49dca877 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000013.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7892 Content-Type: text/plain; charset="utf-8" From: Sean Anderson Device-managed resources are released after manually-managed resources. Therefore, once any manually-managed resource is acquired, all further resources must be manually-managed too. Convert all resources before the MDIO bus is created into device-managed resources. In all cases but one there are already devm variants available. Fixes: 46aa27df8853 ("net: axienet: Use devm_* calls") Signed-off-by: Sean Anderson Co-developed-by: Suraj Gupta Signed-off-by: Suraj Gupta Reviewed-by: Sean Anderson --- .../net/ethernet/xilinx/xilinx_axienet_main.c | 83 ++++++------------- 1 file changed, 27 insertions(+), 56 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/ne= t/ethernet/xilinx/xilinx_axienet_main.c index 284031fb2e2c..998bacd508b8 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -2787,7 +2787,7 @@ static int axienet_probe(struct platform_device *pdev) int addr_width =3D 32; u32 value; =20 - ndev =3D alloc_etherdev(sizeof(*lp)); + ndev =3D devm_alloc_etherdev(&pdev->dev, sizeof(*lp)); if (!ndev) return -ENOMEM; =20 @@ -2815,41 +2815,32 @@ static int axienet_probe(struct platform_device *pd= ev) seqcount_mutex_init(&lp->hw_stats_seqcount, &lp->stats_lock); INIT_DEFERRABLE_WORK(&lp->stats_work, axienet_refresh_stats); =20 - lp->axi_clk =3D devm_clk_get_optional(&pdev->dev, "s_axi_lite_clk"); + lp->axi_clk =3D devm_clk_get_optional_enabled(&pdev->dev, + "s_axi_lite_clk"); if (!lp->axi_clk) { /* For backward compatibility, if named AXI clock is not present, * treat the first clock specified as the AXI clock. */ - lp->axi_clk =3D devm_clk_get_optional(&pdev->dev, NULL); - } - if (IS_ERR(lp->axi_clk)) { - ret =3D PTR_ERR(lp->axi_clk); - goto free_netdev; - } - ret =3D clk_prepare_enable(lp->axi_clk); - if (ret) { - dev_err(&pdev->dev, "Unable to enable AXI clock: %d\n", ret); - goto free_netdev; + lp->axi_clk =3D devm_clk_get_optional_enabled(&pdev->dev, NULL); } + if (IS_ERR(lp->axi_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(lp->axi_clk), + "could not get AXI clock\n"); =20 lp->misc_clks[0].id =3D "axis_clk"; lp->misc_clks[1].id =3D "ref_clk"; lp->misc_clks[2].id =3D "mgt_clk"; =20 - ret =3D devm_clk_bulk_get_optional(&pdev->dev, XAE_NUM_MISC_CLOCKS, lp->m= isc_clks); - if (ret) - goto cleanup_clk; - - ret =3D clk_bulk_prepare_enable(XAE_NUM_MISC_CLOCKS, lp->misc_clks); + ret =3D devm_clk_bulk_get_optional_enable(&pdev->dev, XAE_NUM_MISC_CLOCKS, + lp->misc_clks); if (ret) - goto cleanup_clk; + return dev_err_probe(&pdev->dev, ret, + "could not get/enable misc. clocks\n"); =20 /* Map device registers */ lp->regs =3D devm_platform_get_and_ioremap_resource(pdev, 0, ðres); - if (IS_ERR(lp->regs)) { - ret =3D PTR_ERR(lp->regs); - goto cleanup_clk; - } + if (IS_ERR(lp->regs)) + return PTR_ERR(lp->regs); lp->regs_start =3D ethres->start; =20 /* Setup checksum offload, but default to off if not specified */ @@ -2918,19 +2909,17 @@ static int axienet_probe(struct platform_device *pd= ev) lp->phy_mode =3D PHY_INTERFACE_MODE_1000BASEX; break; default: - ret =3D -EINVAL; - goto cleanup_clk; + return -EINVAL; } } else { ret =3D of_get_phy_mode(pdev->dev.of_node, &lp->phy_mode); if (ret) - goto cleanup_clk; + return ret; } if (lp->switch_x_sgmii && lp->phy_mode !=3D PHY_INTERFACE_MODE_SGMII && lp->phy_mode !=3D PHY_INTERFACE_MODE_1000BASEX) { dev_err(&pdev->dev, "xlnx,switch-x-sgmii only supported with SGMII or 10= 00BaseX\n"); - ret =3D -EINVAL; - goto cleanup_clk; + return -EINVAL; } =20 if (!of_property_present(pdev->dev.of_node, "dmas")) { @@ -2945,7 +2934,7 @@ static int axienet_probe(struct platform_device *pdev) dev_err(&pdev->dev, "unable to get DMA resource\n"); of_node_put(np); - goto cleanup_clk; + return ret; } lp->dma_regs =3D devm_ioremap_resource(&pdev->dev, &dmares); @@ -2962,19 +2951,17 @@ static int axienet_probe(struct platform_device *pd= ev) } if (IS_ERR(lp->dma_regs)) { dev_err(&pdev->dev, "could not map DMA regs\n"); - ret =3D PTR_ERR(lp->dma_regs); - goto cleanup_clk; + return PTR_ERR(lp->dma_regs); } if (lp->rx_irq <=3D 0 || lp->tx_irq <=3D 0) { dev_err(&pdev->dev, "could not determine irqs\n"); - ret =3D -ENOMEM; - goto cleanup_clk; + return -ENOMEM; } =20 /* Reset core now that clocks are enabled, prior to accessing MDIO */ ret =3D __axienet_device_reset(lp); if (ret) - goto cleanup_clk; + return ret; =20 /* Autodetect the need for 64-bit DMA pointers. * When the IP is configured for a bus width bigger than 32 bits, @@ -3001,14 +2988,13 @@ static int axienet_probe(struct platform_device *pd= ev) } if (!IS_ENABLED(CONFIG_64BIT) && lp->features & XAE_FEATURE_DMA_64BIT) { dev_err(&pdev->dev, "64-bit addressable DMA is not compatible with 32-b= it architecture\n"); - ret =3D -EINVAL; - goto cleanup_clk; + return -EINVAL; } =20 ret =3D dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_width)); if (ret) { dev_err(&pdev->dev, "No suitable DMA available\n"); - goto cleanup_clk; + return ret; } netif_napi_add(ndev, &lp->napi_rx, axienet_rx_poll); netif_napi_add(ndev, &lp->napi_tx, axienet_tx_poll); @@ -3018,15 +3004,12 @@ static int axienet_probe(struct platform_device *pd= ev) =20 lp->eth_irq =3D platform_get_irq_optional(pdev, 0); if (lp->eth_irq < 0 && lp->eth_irq !=3D -ENXIO) { - ret =3D lp->eth_irq; - goto cleanup_clk; + return lp->eth_irq; } tx_chan =3D dma_request_chan(lp->dev, "tx_chan0"); - if (IS_ERR(tx_chan)) { - ret =3D PTR_ERR(tx_chan); - dev_err_probe(lp->dev, ret, "No Ethernet DMA (TX) channel found\n"); - goto cleanup_clk; - } + if (IS_ERR(tx_chan)) + return dev_err_probe(lp->dev, PTR_ERR(tx_chan), + "No Ethernet DMA (TX) channel found\n"); =20 cfg.reset =3D 1; /* As name says VDMA but it has support for DMA channel reset */ @@ -3034,7 +3017,7 @@ static int axienet_probe(struct platform_device *pdev) if (ret < 0) { dev_err(&pdev->dev, "Reset channel failed\n"); dma_release_channel(tx_chan); - goto cleanup_clk; + return ret; } =20 dma_release_channel(tx_chan); @@ -3139,13 +3122,6 @@ static int axienet_probe(struct platform_device *pde= v) put_device(&lp->pcs_phy->dev); if (lp->mii_bus) axienet_mdio_teardown(lp); -cleanup_clk: - clk_bulk_disable_unprepare(XAE_NUM_MISC_CLOCKS, lp->misc_clks); - clk_disable_unprepare(lp->axi_clk); - -free_netdev: - free_netdev(ndev); - return ret; } =20 @@ -3163,11 +3139,6 @@ static void axienet_remove(struct platform_device *p= dev) put_device(&lp->pcs_phy->dev); =20 axienet_mdio_teardown(lp); - - clk_bulk_disable_unprepare(XAE_NUM_MISC_CLOCKS, lp->misc_clks); - clk_disable_unprepare(lp->axi_clk); - - free_netdev(ndev); } =20 static void axienet_shutdown(struct platform_device *pdev) --=20 2.25.1