From nobody Mon Feb 9 00:07:56 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58BF51EDA2C; Fri, 2 Jan 2026 15:35:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767368105; cv=none; b=p8i29vxLIpwTiWVZ8euU5p9EYtSWgsaak+mVsk4Kj4Dam2vIwI1Z9nABBaRPAPETrDvs1DAXHxg70NiwXgvBVr9ePCGnIpfRM8ps2WACta6Qq7k8++xjiXaNADdoDwnw0tj8UplasERINeZK5haQPWuT2/NvS6PQIRfAT0fvhKg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767368105; c=relaxed/simple; bh=1TILJpA94tm+NjdIdR07UOJcYaE5858nIVxioO1NGMI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Sjd3FzSj10hduITREmtpR0acgm8cQ5Iv7ugDLSJ37xmtoJYmgPwJxa+kD0wGs9vANwgmckEyJjRml5WWyMyimM0/EmGei7CBhjtqtudXQJS3yjob5sjqgwoW3C/kVL6e6AHN1Tm9XiAotHsRCEdDBplL59Pl5gw/cYJJ6ICKH18= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=N6qnuSRk; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="N6qnuSRk" Received: by smtp.kernel.org (Postfix) with ESMTPS id 721B9C116D0; Fri, 2 Jan 2026 15:35:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1767368104; bh=1TILJpA94tm+NjdIdR07UOJcYaE5858nIVxioO1NGMI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=N6qnuSRkrvEWVnBqyYtCTYC9Lol5VkOc29JzXXnqjJBfu35/hYItKoLx970sCqftc d0WKm9j+dcGywT+8dercKKJRbJfgey2qqF3fTMYv19uVQLukB3xTgQ0YVS0ToIMFos N42/Be6Jrp86UsVBswkXnsicQF8xjjR1utHMn9bs+7DYttQ3R/+OsZc2Yn6zf+aSsT RybdDAOhboySkxTRCzXM7AbM+KBOWulR4m9+Wmma5DQw0oJhYM5G1VwutqW228akUU inHDRCEm+GK4vYDMftmx00uD6OdQwVsa4TT2jumMq5DXO31phrPZQWjpw2FYiqAvqw 6zRNc6dLtNAJw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 599A7FA3752; Fri, 2 Jan 2026 15:35:04 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Fri, 02 Jan 2026 21:04:47 +0530 Subject: [PATCH v3 1/4] PCI: Enable ACS only after configuring IOMMU for OF platforms Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260102-pci_acs-v3-1-72280b94d288@oss.qualcomm.com> References: <20260102-pci_acs-v3-0-72280b94d288@oss.qualcomm.com> In-Reply-To: <20260102-pci_acs-v3-0-72280b94d288@oss.qualcomm.com> To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Naresh Kamboju , Pavankumar Kondeti , Xingang Wang , Marek Szyprowski , Robin Murphy , Jason Gunthorpe , Manivannan Sadhasivam , Manivannan Sadhasivam X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3997; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=5UbTaCqlSfsZh3mFkk650olnLwfrJC/TA0PViCutZMg=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpV+Wm1DB6YPxGpFaNimOGigjiqMZEILNVe2hId 3WdA7gPUuuJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaVflpgAKCRBVnxHm/pHO 9QyWCACWSH1UrGgxuShZFc3H/mSHakZIiuUJWYNWLHowr0+LG8fEbpljGe1qbrPwdfHJmvIq7Nr 4dhgOIWLCncoAc8uEbHVP7XhFQCoYrdIF5fQQR4mgAFUgPSBzY2LF6Fzt3YRNvMJQqWb7QIpknh 1qbq7JPK+S4tG4ggD28ap67z4rmqU/11MNPQ65qzR9toO1KCeLPc12WFBG0AbLI5uWgNqTuyYgy 2xgi/XqW+/8jf3NpQKwpJCAxA5u01SMJtFvLSZ1UgAFiU9sIaW7MGLDjSfAuWKa0kXGbYLwrhjo 0VNbn2LxYQvyN2+kZMgz3K7NOdcE9F+KX/1jtC1PZvtHFirE X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam For enabling ACS without the cmdline params, the platform drivers are expected to call pci_request_acs() API which sets a static flag, 'pci_acs_enable' in drivers/pci/pci.c. And this flag is used to enable ACS in pci_enable_acs() helper, which gets called during pci_acs_init(), as per this call stack: -> pci_device_add() -> pci_init_capabilities() -> pci_acs_init() /* check for pci_acs_enable */ -> pci_enable_acs() For the OF platforms, pci_request_acs() is called during of_iommu_configure() during device_add(), as per this call stack: -> device_add() -> iommu_bus_notifier() -> iommu_probe_device() -> pci_dma_configure() -> of_dma_configure() -> of_iommu_configure() /* set pci_acs_enable */ -> pci_request_acs() As seen from both call stacks, pci_enable_acs() is called way before the invocation of pci_request_acs() for the OF platforms. This means, pci_enable_acs() will not enable ACS for the first device that gets enumerated, which is usally the Root Port device. But since the static flag, 'pci_acs_enable' is set *afterwards*, ACS will be enabled for the ACS capable devices enumerated later. To fix this issue, do not call pci_enable_acs() from pci_acs_init(), but only from pci_dma_configure() after calling of_dma_configure(). This makes sure that pci_enable_acs() only gets called after the IOMMU framework has called pci_request_acs(). The ACS enablement flow now looks like: -> pci_device_add() -> pci_init_capabilities() /* Just store the ACS cap */ -> pci_acs_init() -> device_add() ... -> pci_dma_configure() -> of_dma_configure() -> pci_request_acs() -> pci_enable_acs() For the ACPI platforms, pci_request_acs() is called during ACPI initialization time itself, independent of the IOMMU framework. Tested-by: Marek Szyprowski Tested-by: Naresh Kamboju Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pci-driver.c | 8 ++++++++ drivers/pci/pci.c | 8 -------- drivers/pci/pci.h | 1 + 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index 7c2d9d596258..301a9418e38e 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -1650,6 +1650,14 @@ static int pci_dma_configure(struct device *dev) ret =3D acpi_dma_configure(dev, acpi_get_dma_attr(adev)); } =20 + /* + * Attempt to enable ACS regardless of capability because some Root + * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have + * the standard ACS capability but still support ACS via those + * quirks. + */ + pci_enable_acs(to_pci_dev(dev)); + pci_put_host_bridge_device(bridge); =20 /* @drv may not be valid when we're called from the IOMMU layer */ diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 13dbb405dc31..2c3d0a2d6973 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3648,14 +3648,6 @@ bool pci_acs_path_enabled(struct pci_dev *start, void pci_acs_init(struct pci_dev *dev) { dev->acs_cap =3D pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); - - /* - * Attempt to enable ACS regardless of capability because some Root - * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have - * the standard ACS capability but still support ACS via those - * quirks. - */ - pci_enable_acs(dev); } =20 /** diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 0e67014aa001..4592ede0ebcc 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -939,6 +939,7 @@ static inline resource_size_t pci_resource_alignment(st= ruct pci_dev *dev, } =20 void pci_acs_init(struct pci_dev *dev); +void pci_enable_acs(struct pci_dev *dev); #ifdef CONFIG_PCI_QUIRKS int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); int pci_dev_specific_enable_acs(struct pci_dev *dev); --=20 2.48.1 From nobody Mon Feb 9 00:07:56 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58B801E521A; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260102-pci_acs-v3-2-72280b94d288@oss.qualcomm.com> References: <20260102-pci_acs-v3-0-72280b94d288@oss.qualcomm.com> In-Reply-To: <20260102-pci_acs-v3-0-72280b94d288@oss.qualcomm.com> To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Naresh Kamboju , Pavankumar Kondeti , Xingang Wang , Marek Szyprowski , Robin Murphy , Jason Gunthorpe , Manivannan Sadhasivam , Manivannan Sadhasivam X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3840; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=WNlj98gnBzP8GjtkwGPs6wt/sfHp/QN3NSkkvAVIXtQ=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpV+Wm0uuebZ0Bh1aSfHkMGH9dvwjaLhS2WLos/ KSkWbsN2gGJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaVflpgAKCRBVnxHm/pHO 9YEYCACMjcDP3uQy0Rj+omfbOFgbTz9mNX1Y7XE/+f9xXOBH62vc22vblxpTSfhMSx02s0p6qyg WflootAkgPcpAHnDnd0buKCGWFaJojNQRNnznfPCPXqs+gQ+P8EuHsXl86dt2QGDdabPjq9kXqv eY95BzcfEWzCczMSWsre8o0ApDv9PYjcPe0hkmhxI1RfI9OSX8JRRMkaXHyX4o+crl0NrGJieK7 v6bOx7gG1Dk1Y0E6lIkqNI2SKZz1/ggKgEfJh8MZCRRsFtft9s9zzeHP0YUFpwhs5b9RHwSjMxI eeMXMyQQMTVOqykGwdF7ZTE1jOwK2uoihGk1gLonxQfuaUAS X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam ACS capabilities are the RO values set by the hardware. Cache them to avoid reading it all the time when required and also to override any capability in quirks. Tested-by: Marek Szyprowski Tested-by: Naresh Kamboju Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pci.c | 26 +++++++++++++++----------- include/linux/pci.h | 1 + 2 files changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 2c3d0a2d6973..d89b04451aea 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -892,7 +892,6 @@ static const char *disable_acs_redir_param; static const char *config_acs_param; =20 struct pci_acs { - u16 cap; u16 ctrl; u16 fw_ctrl; }; @@ -995,27 +994,27 @@ static void __pci_config_acs(struct pci_dev *dev, str= uct pci_acs *caps, static void pci_std_enable_acs(struct pci_dev *dev, struct pci_acs *caps) { /* Source Validation */ - caps->ctrl |=3D (caps->cap & PCI_ACS_SV); + caps->ctrl |=3D (dev->acs_capabilities & PCI_ACS_SV); =20 /* P2P Request Redirect */ - caps->ctrl |=3D (caps->cap & PCI_ACS_RR); + caps->ctrl |=3D (dev->acs_capabilities & PCI_ACS_RR); =20 /* P2P Completion Redirect */ - caps->ctrl |=3D (caps->cap & PCI_ACS_CR); + caps->ctrl |=3D (dev->acs_capabilities & PCI_ACS_CR); =20 /* Upstream Forwarding */ - caps->ctrl |=3D (caps->cap & PCI_ACS_UF); + caps->ctrl |=3D (dev->acs_capabilities & PCI_ACS_UF); =20 /* Enable Translation Blocking for external devices and noats */ if (pci_ats_disabled() || dev->external_facing || dev->untrusted) - caps->ctrl |=3D (caps->cap & PCI_ACS_TB); + caps->ctrl |=3D (dev->acs_capabilities & PCI_ACS_TB); } =20 /** * pci_enable_acs - enable ACS if hardware support it * @dev: the PCI device */ -static void pci_enable_acs(struct pci_dev *dev) +void pci_enable_acs(struct pci_dev *dev) { struct pci_acs caps; bool enable_acs =3D false; @@ -1031,7 +1030,6 @@ static void pci_enable_acs(struct pci_dev *dev) if (!pos) return; =20 - pci_read_config_word(dev, pos + PCI_ACS_CAP, &caps.cap); pci_read_config_word(dev, pos + PCI_ACS_CTRL, &caps.ctrl); caps.fw_ctrl =3D caps.ctrl; =20 @@ -3514,7 +3512,7 @@ void pci_configure_ari(struct pci_dev *dev) static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags) { int pos; - u16 cap, ctrl; + u16 ctrl; =20 pos =3D pdev->acs_cap; if (!pos) @@ -3525,8 +3523,7 @@ static bool pci_acs_flags_enabled(struct pci_dev *pde= v, u16 acs_flags) * or only required if controllable. Features missing from the * capability field can therefore be assumed as hard-wired enabled. */ - pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap); - acs_flags &=3D (cap | PCI_ACS_EC); + acs_flags &=3D (pdev->acs_capabilities | PCI_ACS_EC); =20 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl); return (ctrl & acs_flags) =3D=3D acs_flags; @@ -3647,7 +3644,14 @@ bool pci_acs_path_enabled(struct pci_dev *start, */ void pci_acs_init(struct pci_dev *dev) { + int pos; + dev->acs_cap =3D pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); + pos =3D dev->acs_cap; + if (!pos) + return; + + pci_read_config_word(dev, pos + PCI_ACS_CAP, &dev->acs_capabilities); } =20 /** diff --git a/include/linux/pci.h b/include/linux/pci.h index 864775651c6f..6195e040b29c 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -558,6 +558,7 @@ struct pci_dev { struct pci_tsm *tsm; /* TSM operation state */ #endif u16 acs_cap; /* ACS Capability offset */ + u16 acs_capabilities; /* ACS Capabilities */ u8 supported_speeds; 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Fri, 2 Jan 2026 15:35:04 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Fri, 02 Jan 2026 21:04:49 +0530 Subject: [PATCH v3 3/4] PCI: Disable ACS SV capability for the broken IDT switches Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260102-pci_acs-v3-3-72280b94d288@oss.qualcomm.com> References: <20260102-pci_acs-v3-0-72280b94d288@oss.qualcomm.com> In-Reply-To: <20260102-pci_acs-v3-0-72280b94d288@oss.qualcomm.com> To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Naresh Kamboju , Pavankumar Kondeti , Xingang Wang , Marek Szyprowski , Robin Murphy , Jason Gunthorpe , Manivannan Sadhasivam , Manivannan Sadhasivam X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=7330; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=hSq+H8p+b3vKTeIGRylJu/YSgirGGdFRZY95lQVM7wA=; b=owGbwMvMwMUYOl/w2b+J574ynlZLYsgMf7osxH6euZDI7wjG72v4er++yf03tbnvnmO7sJ77n 3wLwwdenYzGLAyMXAyyYoos6UudtRo9Tt9YEqE+HWYQKxPIFAYuTgGYyK3H7P/0jSwP2X58vSFv 4r+O4oNckhL15/hZjOa/Y9d3sc80aLF+xPtlZub7JbFckyR1f+ptli5Pm+9qfPaT3LT5xZGZO6s 5VJM0aq9HbL109TizUdy7X54Xmp/GxycUeH/qjZ5lYj+JLbdMMPfkHKUHxnKtc7LOz2mUs9N5Wr 21clqLqRi/iGGTzqPozj9JZyd27GiQClmvkFmhtOt+d/OMfwcZz7/Zymkv4RjA56k6ec77/EB1v ugHwbxcinE1d3ksLRTc2fgq/i1xlZ4hXPjttc0igZqZXpb5x/K9Naa1bNoWXHnvrvmZ4mP8C+52 hcidCi2Pi+3KiLU+uOT/NdcPTl1FdmevBrtbdT705N8GAA== X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam Some IDT switches behave erratically when ACS Source Validation is enabled. For example, they incorrectly flag an ACS Source Validation error on completions for config read requests even though PCIe r4.0, sec 6.12.1.1, says that completions are never affected by ACS Source Validation. Even though IDT suggests working around this issue by issuing a config write before the first config read, so that the device caches the bus and device number. But it would still be fragile since the device could loose the IDs after the reset and any further access may trigger ACS SV violation. Hence, to properly fix the issue, the respective capability needs to be disabled. Since the ACS Capabilities are RO values, and are cached in the 'pci_dev::acs_capabilities' field, remove the cached broken capabilities by calling pci_disable_broken_acs_cap() from pci_acs_init(). This will allow pci_enable_acs() helper to disable the relevant ACS ctrls. With this, the previous workaround can now be safely removed. Tested-by: Marek Szyprowski Tested-by: Naresh Kamboju Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pci.c | 1 + drivers/pci/pci.h | 3 ++- drivers/pci/probe.c | 12 ----------- drivers/pci/quirks.c | 61 ++++++++++++------------------------------------= ---- 4 files changed, 17 insertions(+), 60 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index d89b04451aea..e16229e7ff6f 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3652,6 +3652,7 @@ void pci_acs_init(struct pci_dev *dev) return; =20 pci_read_config_word(dev, pos + PCI_ACS_CAP, &dev->acs_capabilities); + pci_disable_broken_acs_cap(dev); } =20 /** diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 4592ede0ebcc..5fe5d6e84c95 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -432,7 +432,6 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, in= t devfn, u32 *pl, int rrs_timeout); bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u3= 2 *pl, int rrs_timeout); -int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int rrs_tim= eout); =20 int pci_setup_device(struct pci_dev *dev); void __pci_size_stdbars(struct pci_dev *dev, int count, @@ -944,6 +943,7 @@ void pci_enable_acs(struct pci_dev *dev); int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); int pci_dev_specific_enable_acs(struct pci_dev *dev); int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); +void pci_disable_broken_acs_cap(struct pci_dev *pdev); int pcie_failed_link_retrain(struct pci_dev *dev); #else static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, @@ -959,6 +959,7 @@ static inline int pci_dev_specific_disable_acs_redir(st= ruct pci_dev *dev) { return -ENOTTY; } +static inline void pci_disable_broken_acs_cap(struct pci_dev *dev) { } static inline int pcie_failed_link_retrain(struct pci_dev *dev) { return -ENOTTY; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 41183aed8f5d..c7304ac5afc2 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2547,18 +2547,6 @@ bool pci_bus_generic_read_dev_vendor_id(struct pci_b= us *bus, int devfn, u32 *l, bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, int timeout) { -#ifdef CONFIG_PCI_QUIRKS - struct pci_dev *bridge =3D bus->self; - - /* - * Certain IDT switches have an issue where they improperly trigger - * ACS Source Validation errors on completions for config reads. - */ - if (bridge && bridge->vendor =3D=3D PCI_VENDOR_ID_IDT && - bridge->device =3D=3D 0x80b5) - return pci_idt_bus_quirk(bus, devfn, l, timeout); -#endif - return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); } EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index b9c252aa6fe0..1571a2ef331e 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5778,58 +5778,25 @@ DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_= NVIDIA, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); =20 /* - * Some IDT switches incorrectly flag an ACS Source Validation error on - * completions for config read requests even though PCIe r4.0, sec - * 6.12.1.1, says that completions are never affected by ACS Source - * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: + * Some IDT switches behave erratically when ACS Source Validation is enab= led. + * For example, they incorrectly flag an ACS Source Validation error on + * completions for config read requests even though PCIe r4.0, sec 6.12.1.= 1, + * says that completions are never affected by ACS Source Validation. * - * Item #36 - Downstream port applies ACS Source Validation to Completio= ns - * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that - * completions are never affected by ACS Source Validation. However, - * completions received by a downstream port of the PCIe switch from a - * device that has not yet captured a PCIe bus number are incorrectly - * dropped by ACS Source Validation by the switch downstream port. + * Even though IDT suggests working around this issue by issuing a config = write + * before the first config read, so that the switch caches the bus and dev= ice + * number, it would still be fragile since the device could loose the IDs = after + * the reset. * - * The workaround suggested by IDT is to issue a config write to the - * downstream device before issuing the first config read. This allows the - * downstream device to capture its bus and device numbers (see PCIe r4.0, - * sec 2.2.9), thus avoiding the ACS error on the completion. - * - * However, we don't know when the device is ready to accept the config - * write, so we do config reads until we receive a non-Config Request Retry - * Status, then do the config write. - * - * To avoid hitting the erratum when doing the config reads, we disable ACS - * SV around this process. + * Hence, a reliable fix would be to assume that these switches don't supp= ort + * ACS SV. */ -int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout) +void pci_disable_broken_acs_cap(struct pci_dev *pdev) { - int pos; - u16 ctrl =3D 0; - bool found; - struct pci_dev *bridge =3D bus->self; - - pos =3D bridge->acs_cap; - - /* Disable ACS SV before initial config reads */ - if (pos) { - pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl); - if (ctrl & PCI_ACS_SV) - pci_write_config_word(bridge, pos + PCI_ACS_CTRL, - ctrl & ~PCI_ACS_SV); + if (pdev->vendor =3D=3D PCI_VENDOR_ID_IDT && pdev->device =3D=3D 0x80b5) { + pci_info(pdev, "Disabling broken ACS SV\n"); + pdev->acs_capabilities &=3D ~PCI_ACS_SV; } - - found =3D pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); - - /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ - if (found) - pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0); - - /* Re-enable ACS_SV if it was previously enabled */ - if (ctrl & PCI_ACS_SV) - pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl); - - return found; } =20 /* --=20 2.48.1 From nobody Mon Feb 9 00:07:56 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58CB1221F2F; Fri, 2 Jan 2026 15:35:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260102-pci_acs-v3-4-72280b94d288@oss.qualcomm.com> References: <20260102-pci_acs-v3-0-72280b94d288@oss.qualcomm.com> In-Reply-To: <20260102-pci_acs-v3-0-72280b94d288@oss.qualcomm.com> To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Naresh Kamboju , Pavankumar Kondeti , Xingang Wang , Marek Szyprowski , Robin Murphy , Jason Gunthorpe , Manivannan Sadhasivam , Manivannan Sadhasivam X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1308; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=GUu8Qg859a+VLOI/rgxng234DVNkgR6VO624aAuxydk=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpV+Wm74o/HwnJ04fTQcCSyQO4vFATpeTyjSpAk 8/dpTmAVm2JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaVflpgAKCRBVnxHm/pHO 9RcLB/sEMvU90lbPoTRSvSEIII2sEIQZJK7DLRdmDPIZDhdb4/iHqsMWnXF4ZM/dwwFv5FJ8/HS K4Z710qqzXzZNXSQsXntZhoqwN9AmLhAwGMZbkA6vYX+VMdgNlAasGo5udyvHrn4QOOnbNbzBWn m99ZXef7u8oZXpybOnUctuyOQfBd5fRYxtshy5+1JdSDdir6S3pba9EGCm0nPXFPfQxvFjRTmF7 YqcBYzDEFSwAozGsFlY42iwp01EEQUhrgoLr1qYaxbkfGUJI4UJzjSuR9ZU5YFjzKMHojrpk7oK PlermbNsTL+A9i4anveM1PyteOVhVAZ+oZ3QJyXXq0GsRxzI X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam The IDT switch with Device ID 0x8090 used in the ARM Juno R2 development board incorrectly raises an ACS Source Validation error on Completions for Config Read Requests, even though PCIe r6.0, sec 6.12.1.1, says that Completions are never affected by ACS Source Validation. This is already handled by the pci_disable_broken_acs_cap() quirk for one of the IDT switch 0x80b5. Hence, extend the quirk for this device too. Tested-by: Marek Szyprowski Tested-by: Naresh Kamboju Signed-off-by: Manivannan Sadhasivam --- drivers/pci/quirks.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 1571a2ef331e..11ecb9ba1594 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5793,7 +5793,8 @@ DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NV= IDIA, PCI_ANY_ID, */ void pci_disable_broken_acs_cap(struct pci_dev *pdev) { - if (pdev->vendor =3D=3D PCI_VENDOR_ID_IDT && pdev->device =3D=3D 0x80b5) { + if (pdev->vendor =3D=3D PCI_VENDOR_ID_IDT && (pdev->device =3D=3D 0x80b5 = || + pdev->device =3D=3D 0x8090)) { pci_info(pdev, "Disabling broken ACS SV\n"); pdev->acs_capabilities &=3D ~PCI_ACS_SV; } --=20 2.48.1