From nobody Sun Feb 8 18:30:51 2026 Received: from mail-4323.protonmail.ch (mail-4323.protonmail.ch [185.70.43.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBC2C2EBDFA; Fri, 2 Jan 2026 11:29:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.23 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767353396; cv=none; b=sECc/KFFfOz0DFBdxcxv/9dUv+iKPSCmiYe2iPkI2xYAXUMP84DFgUF2PR95PlkV2hvVjo/yRE+thRe2WIhWAD6qxNvvIXg3cKLuUzXh+de0Fkvhh4CMVBhtyzjboinM8xlhMURgRA0ICnuWEmNRsHYMtBAHwzPHsPTAQ+5G+Cc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767353396; c=relaxed/simple; bh=qzuDAQL6ncaR+g778ifbBHl2XeBed/a8pCB6zp6QPt8=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=E31gsoAZC4bR37aXCFuLDnx1AqDUmYaW//Ns2MzjqZsM5HlbfjUJlhct/tlBFS+IR6oKN7DciBPZOd/nUa/DxCwwZ6l1atUejBBgppgCwTygwsu5TXQWtw72+z8DUvN6Iy8RneW7ZEDdRlOaj0IDt7yp7IUrUJVez85H7bWxW/o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro; spf=pass smtp.mailfrom=chimac.ro; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b=j5kWh/o+; arc=none smtp.client-ip=185.70.43.23 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chimac.ro Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b="j5kWh/o+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chimac.ro; s=protonmail2; t=1767353387; x=1767612587; bh=U84g9CNDZRq+0bG0puOFpJgmnKLOVSi6/RBHeipEFfo=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=j5kWh/o+0+T62O1HHPuRKqTlWBnZ7T1/yY1NPTZoOWijpYTvujeB1OOaGqdIRTnyP NPL12A+T3OHyLNzV/WHoCsEnqcoSa3WSydSIH3ynL0f5ltGm0IByP38YB/Ye7PZ4O2 rjoF2JIgepgFXGR0LrQvyuDsnc6weI7XdGA374ikfVm0CMTU12B37ox0DyXfH1GhMl O77lyvR4DHHKm8ekhaFhyAq+0inHeZDxLZ9Alj2QugYEzWspr8YfXnBDgBfguwxsTw zE0WJFpPj7PvnUd7RpPcC3zKfoUtc67+qrOBQBi+4PMt33FWVJmrLulCQ7BEIFhUN+ vSQsttuXzlFiA== Date: Fri, 02 Jan 2026 11:29:40 +0000 To: Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar , Linus Walleij , Rob Herring , Conor Dooley , Tomasz Figa From: Alexandru Chimac Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexandru Chimac Subject: [PATCH v3 1/3] dt-bindings: pinctrl: samsung: Add exynos9610-pinctrl compatible Message-ID: <20260102-exynos9610-pinctrl-v3-1-3f21f2cfb651@chimac.ro> In-Reply-To: <20260102-exynos9610-pinctrl-v3-0-3f21f2cfb651@chimac.ro> References: <20260102-exynos9610-pinctrl-v3-0-3f21f2cfb651@chimac.ro> Feedback-ID: 139133584:user:proton X-Pm-Message-ID: e38b12d8d708fa3d0c650eecc1e5645b0f2af9fd Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document pin controller support on Exynos9610-series SoCs. Signed-off-by: Alexandru Chimac --- Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml= b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index ddc5e2efff21..7b006009ca0e 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -55,6 +55,7 @@ properties: - samsung,exynos850-pinctrl - samsung,exynos8890-pinctrl - samsung,exynos8895-pinctrl + - samsung,exynos9610-pinctrl - samsung,exynos9810-pinctrl - samsung,exynos990-pinctrl - samsung,exynosautov9-pinctrl --=20 2.51.0 From nobody Sun Feb 8 18:30:51 2026 Received: from mail-4318.protonmail.ch (mail-4318.protonmail.ch [185.70.43.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EFC202EAB82; Fri, 2 Jan 2026 11:29:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767353398; cv=none; b=metA0nTQlZW++poowpRoQcu6BHy9worcjEgtvkLrUJXFCObs+UCwyWGcHc048MIr+39FDEmth/pGpFYZyFqp7SiGMeQXPhSUygaLdnxjV5/luB3RX3pt8/4mdBLUbTtXqpzgmEU0jVgNEfCcmLz0V8pj6KrcdPK+4xEbKCJNDXg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767353398; c=relaxed/simple; bh=hNzG//UEyLoPb3J2DnbNtlBDzS8vc/bHChBjTkB+gsQ=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lLeJrl3M3xw9QNDXU1Jk6bpr0goefIN9tVO5G7RbmkRrGsqoIKEvmBHFH/SYCOGdSy2Yp9IC+1LJqkdLRW2wcfVwAuak0NICQY+mcu5R22/LL7LwhiWpYbqcI5RIxRaE0QviQJjDztqYCZb9fEV7B28hPz0ltwcAmtT2Ss6vBKk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro; spf=pass smtp.mailfrom=chimac.ro; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b=GMlYpKce; arc=none smtp.client-ip=185.70.43.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chimac.ro Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b="GMlYpKce" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chimac.ro; s=protonmail2; t=1767353393; x=1767612593; bh=sjdFgLhyI2gKa4FyGQgRrvSM1TJIstHiEd/eY+0jaDI=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=GMlYpKceZo+pkQUh8HthkRuZsxDUuHDCptD7zEFtJdxeWcmsh2jXqQzg2fyUoRSlw Kq6G53sItOUSFBwHA7TgiGbfnC0O5prq4js2x++thLwIjIut9/1GgkLP+05A45z2Jy bC39PMi7xikzIXdt9YNGd3qh1nVwvGqcmisuzBOpeQd598h5OqEEyC+2z7LJGxxT5P 7dWE9vGv3bhpH+lpUfDFuZUj/MYyh0Y0H6ykLRIUPUJ7jlQaTp1EOml/0fyFZke/8z xj7LYLs2RUq/YU9oGlNQR76T9B/FoKFXJxUdWYFnSGYK3cFZX0QzNB7lDmfYPX6O+9 lluo7jBAk4OtQ== Date: Fri, 02 Jan 2026 11:29:49 +0000 To: Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar , Linus Walleij , Rob Herring , Conor Dooley , Tomasz Figa From: Alexandru Chimac Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexandru Chimac Subject: [PATCH v3 2/3] dt-bindings: pinctrl: samsung: Add exynos9610-wakeup-eint node Message-ID: <20260102-exynos9610-pinctrl-v3-2-3f21f2cfb651@chimac.ro> In-Reply-To: <20260102-exynos9610-pinctrl-v3-0-3f21f2cfb651@chimac.ro> References: <20260102-exynos9610-pinctrl-v3-0-3f21f2cfb651@chimac.ro> Feedback-ID: 139133584:user:proton X-Pm-Message-ID: de7b0ffcfcdd03ed139b527265085e60d44ecdc2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a dedicated compatible for the exynos9610-wakeup-eint node, which is compatbile with Exynos850's implementation (and the Exynos7 fallback). Signed-off-by: Alexandru Chimac --- .../devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml |= 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wake= up-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinct= rl-wakeup-interrupt.yaml index f3c433015b12..2b88f25e80a6 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-inte= rrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-inte= rrupt.yaml @@ -48,6 +48,7 @@ properties: - enum: - google,gs101-wakeup-eint - samsung,exynos2200-wakeup-eint + - samsung,exynos9610-wakeup-eint - samsung,exynos9810-wakeup-eint - samsung,exynos990-wakeup-eint - samsung,exynosautov9-wakeup-eint --=20 2.51.0 From nobody Sun Feb 8 18:30:51 2026 Received: from mail-07.mail-europe.com (mail-0701.mail-europe.com [51.83.17.38]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA2A422F767; Fri, 2 Jan 2026 11:30:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=51.83.17.38 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767353418; cv=none; b=LGYCk/LeKjWIMk9KoVJRGgqwch93ZSkAtlXYpMCTLeR0n45l331EI7E7fqHo8ISa3Hj6TZDrQqhVr58puYoJ9y5FuGekZiySS0AF8HfmAmOo4RrJKRNvQn4xbEShgbhevxxcrf1S12Y9mFwP+zxqk5i7pMyrua/uG5vSmGajyuk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767353418; c=relaxed/simple; bh=2WBWmLDvI+3uWaI6iGjj/oIiCNEaKia41qm7RafJtQM=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cISLK9OovE6AoLA/O090Ywiv2bNYzkSDt8vR5yWN9tBg6xLwKwdTyc+wubIEQmlrmm3yoxgMeOa7UjeDJZWLEL7MiFy1symZnqtZ0j8RMaa92wXe84jISsTrBFOqCb+jPI8VTPELqTkGiS1LwTGgq4NCGfhXQVilDSBErGRzrQc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro; spf=fail smtp.mailfrom=chimac.ro; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b=FIZ4BtwD; arc=none smtp.client-ip=51.83.17.38 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=chimac.ro Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b="FIZ4BtwD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chimac.ro; s=protonmail2; t=1767353405; x=1767612605; bh=Iimb+k4FWtKsauCwXJMg2NmIw/RYvYhly8/W3jnsDME=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=FIZ4BtwDhItGmk78vkot4DkLX1jFfBn6tfQ3o5chw59NdU9dPr9gwYJDyk6kxQbwP xlOv0XyhGj0mjhCtvz59le9rDHYgnc/b88hVZlLkZHUIxwNUDAicBFzDVm5SiouvO0 +rRwAnncT1TZBqD42Zh8FY9zKjwqwFr9pV9ypK01GxelIKKrg5J9Nevl2sKzUOsLgI B43YORmXNDnznBO1WP+q3HMKEPMwvkBw51MkX9qGmRYYZMipKkvA9WM+N3bbA4X7ja MEmuW+DDbivCO/0QaD0qLrVxVZcFYsEH6sqNICHhmfj71CBXKTIAucPEjLtJaENi+S 1uiRZoZ6S3m9A== Date: Fri, 02 Jan 2026 11:29:59 +0000 To: Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar , Linus Walleij , Rob Herring , Conor Dooley , Tomasz Figa From: Alexandru Chimac Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexandru Chimac Subject: [PATCH v3 3/3] pinctrl: samsung: Add Exynos9610 pinctrl configuration Message-ID: <20260102-exynos9610-pinctrl-v3-3-3f21f2cfb651@chimac.ro> In-Reply-To: <20260102-exynos9610-pinctrl-v3-0-3f21f2cfb651@chimac.ro> References: <20260102-exynos9610-pinctrl-v3-0-3f21f2cfb651@chimac.ro> Feedback-ID: 139133584:user:proton X-Pm-Message-ID: ed06c8d23a26a5c1291be26cccef799624ca0eee Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add pinctrl configuration for Exynos9610. The bank types used are the same as on Exynos850 and gs101, so we can reuse the macros. Signed-off-by: Alexandru Chimac --- drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 117 +++++++++++++++++++++= ++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 3 files changed, 120 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinct= rl/samsung/pinctrl-exynos-arm64.c index 627dca504d7a..fe9f92cb037e 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -1770,6 +1770,123 @@ const struct samsung_pinctrl_of_match_data exynos88= 95_of_data __initconst =3D { .num_ctrl =3D ARRAY_SIZE(exynos8895_pin_ctrl), }; =20 +/* pin banks of exynos9610 pin-controller 0 (ALIVE) */ +static const struct samsung_pin_bank_data exynos9610_pin_banks0[] __initco= nst =3D { + EXYNOS850_PIN_BANK_EINTN(6, 0x000, "etc0"), + GS101_PIN_BANK_EINTW(8, 0x020, "gpa0", 0x00, 0x00), + GS101_PIN_BANK_EINTW(8, 0x040, "gpa1", 0x04, 0x08), + GS101_PIN_BANK_EINTW(8, 0x060, "gpa2", 0x08, 0x0c), + EXYNOS850_PIN_BANK_EINTN(5, 0x080, "gpq0"), +}; + +/* pin banks of exynos9610 pin-controller 1 (CMGP) */ +static const struct samsung_pin_bank_data exynos9610_pin_banks1[] __initco= nst =3D { + EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), + EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), + EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), + EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C), + EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), + EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14), + EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18), + EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C), + EXYNOS850_PIN_BANK_EINTW(1, 0x100, "gpm8", 0x20), + EXYNOS850_PIN_BANK_EINTW(1, 0x120, "gpm9", 0x24), + EXYNOS850_PIN_BANK_EINTW(1, 0x140, "gpm10", 0x28), + EXYNOS850_PIN_BANK_EINTW(1, 0x160, "gpm11", 0x2C), + EXYNOS850_PIN_BANK_EINTW(1, 0x180, "gpm12", 0x30), + EXYNOS850_PIN_BANK_EINTW(1, 0x1A0, "gpm13", 0x34), + EXYNOS850_PIN_BANK_EINTW(1, 0x1C0, "gpm14", 0x38), + EXYNOS850_PIN_BANK_EINTW(1, 0x1E0, "gpm15", 0x3C), + EXYNOS850_PIN_BANK_EINTW(1, 0x200, "gpm16", 0x40), + EXYNOS850_PIN_BANK_EINTW(1, 0x220, "gpm17", 0x44), + EXYNOS850_PIN_BANK_EINTW(1, 0x240, "gpm18", 0x48), + EXYNOS850_PIN_BANK_EINTW(1, 0x260, "gpm19", 0x4C), + EXYNOS850_PIN_BANK_EINTW(1, 0x280, "gpm20", 0x50), + EXYNOS850_PIN_BANK_EINTW(1, 0x2A0, "gpm21", 0x54), + EXYNOS850_PIN_BANK_EINTW(1, 0x2C0, "gpm22", 0x58), + EXYNOS850_PIN_BANK_EINTW(1, 0x2E0, "gpm23", 0x5C), + EXYNOS850_PIN_BANK_EINTW(1, 0x300, "gpm24", 0x60), + EXYNOS850_PIN_BANK_EINTW(1, 0x320, "gpm25", 0x64), +}; + +/* pin banks of exynos9610 pin-controller 2 (DISPAUD) */ +static const struct samsung_pin_bank_data exynos9610_pin_banks2[] __initco= nst =3D { + GS101_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00, 0x00), + GS101_PIN_BANK_EINTG(4, 0x020, "gpb1", 0x04, 0x08), + GS101_PIN_BANK_EINTG(5, 0x040, "gpb2", 0x08, 0x0c), +}; + +/* pin banks of exynos9610 pin-controller 3 (FSYS) */ +static const struct samsung_pin_bank_data exynos9610_pin_banks3[] __initco= nst =3D { + GS101_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00, 0x00), + GS101_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04, 0x04), + GS101_PIN_BANK_EINTG(6, 0x040, "gpf2", 0x08, 0x0c), +}; + +/* pin banks of exynos9610 pin-controller 4 (TOP) */ +static const struct samsung_pin_bank_data exynos9610_pin_banks4[] __initco= nst =3D { + GS101_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00, 0x00), + GS101_PIN_BANK_EINTG(6, 0x020, "gpp1", 0x04, 0x08), + GS101_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08, 0x10), + GS101_PIN_BANK_EINTG(8, 0x060, "gpc0", 0x0C, 0x18), + GS101_PIN_BANK_EINTG(8, 0x080, "gpc1", 0x10, 0x20), + GS101_PIN_BANK_EINTG(5, 0x0A0, "gpc2", 0x14, 0x28), + GS101_PIN_BANK_EINTG(8, 0x0C0, "gpg0", 0x18, 0x30), + GS101_PIN_BANK_EINTG(8, 0x0E0, "gpg1", 0x1C, 0x38), + GS101_PIN_BANK_EINTG(8, 0x100, "gpg2", 0x20, 0x40), + GS101_PIN_BANK_EINTG(6, 0x120, "gpg3", 0x24, 0x48), + GS101_PIN_BANK_EINTG(3, 0x140, "gpg4", 0x28, 0x50), +}; + +/* pin banks of exynos9610 pin-controller 5 (SHUB) */ +static const struct samsung_pin_bank_data exynos9610_pin_banks5[] __initco= nst =3D { + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gph0", 0x00), + EXYNOS850_PIN_BANK_EINTG(3, 0x020, "gph1", 0x04), +}; + +static const struct samsung_pin_ctrl exynos9610_pin_ctrl[] __initconst =3D= { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks =3D exynos9610_pin_banks0, + .nr_banks =3D ARRAY_SIZE(exynos9610_pin_banks0), + .eint_wkup_init =3D exynos_eint_wkup_init, + .suspend =3D exynos_pinctrl_suspend, + .resume =3D exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 CMGP data */ + .pin_banks =3D exynos9610_pin_banks1, + .nr_banks =3D ARRAY_SIZE(exynos9610_pin_banks1), + .eint_wkup_init =3D exynos_eint_wkup_init, + .suspend =3D exynos_pinctrl_suspend, + .resume =3D exynos_pinctrl_resume, + }, { + /* pin-controller instance 2 DISPAUD data */ + .pin_banks =3D exynos9610_pin_banks2, + .nr_banks =3D ARRAY_SIZE(exynos9610_pin_banks2), + }, { + /* pin-controller instance 3 FSYS data */ + .pin_banks =3D exynos9610_pin_banks3, + .nr_banks =3D ARRAY_SIZE(exynos9610_pin_banks3), + .suspend =3D exynos_pinctrl_suspend, + .resume =3D exynos_pinctrl_resume, + }, { + /* pin-controller instance 4 TOP data */ + .pin_banks =3D exynos9610_pin_banks4, + .nr_banks =3D ARRAY_SIZE(exynos9610_pin_banks4), + .suspend =3D exynos_pinctrl_suspend, + .resume =3D exynos_pinctrl_resume, + }, { + /* pin-controller instance 5 SHUB data */ + .pin_banks =3D exynos9610_pin_banks5, + .nr_banks =3D ARRAY_SIZE(exynos9610_pin_banks5), + }, +}; + +const struct samsung_pinctrl_of_match_data exynos9610_of_data __initconst = =3D { + .ctrl =3D exynos9610_pin_ctrl, + .num_ctrl =3D ARRAY_SIZE(exynos9610_pin_ctrl), +}; + /* * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three * gpio/pin-mux/pinconfig controllers. diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/sa= msung/pinctrl-samsung.c index e374effba25a..5ac6f6b02327 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1504,6 +1504,8 @@ static const struct of_device_id samsung_pinctrl_dt_m= atch[] =3D { .data =3D &exynos8890_of_data }, { .compatible =3D "samsung,exynos8895-pinctrl", .data =3D &exynos8895_of_data }, + { .compatible =3D "samsung,exynos9610-pinctrl", + .data =3D &exynos9610_of_data }, { .compatible =3D "samsung,exynos9810-pinctrl", .data =3D &exynos9810_of_data }, { .compatible =3D "samsung,exynos990-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/sa= msung/pinctrl-samsung.h index 0f7b2ea98158..937600430a6e 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -398,6 +398,7 @@ extern const struct samsung_pinctrl_of_match_data exyno= s7885_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data exynos8890_of_data; extern const struct samsung_pinctrl_of_match_data exynos8895_of_data; +extern const struct samsung_pinctrl_of_match_data exynos9610_of_data; extern const struct samsung_pinctrl_of_match_data exynos9810_of_data; extern const struct samsung_pinctrl_of_match_data exynos990_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; --=20 2.51.0