From nobody Mon Feb 9 03:14:29 2026 Received: from smtp.gentoo.org (woodpecker.gentoo.org [140.211.166.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66B9D2D0C97; Fri, 2 Jan 2026 07:01:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=140.211.166.183 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767337286; cv=none; b=a20VUacZhVj3VxHEhv8rcLFEu4zuavmUSBA9mag9n6HggV5zxblYil7bzzl8da/Bd5fucKt2uywM746Perv8JrgXDAzZQ2ygxNfWDK6/qMaxBob+Ay1fGGrZd+j74JukhNZk43LwfCuqZjFFQ6KlFGccetjq5Hv9+g2mBLUU/FI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767337286; c=relaxed/simple; bh=/MRpvp+cwdSbDmLiFgi17bE8BWDrGFI3hfVNRzFOP5o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MpYa03tBzGrRp89geZv6azks4iV9gUnIspZeAqCILmxDice6V3vG8qf1WifldGX6M90nMX7DKvax8e0kfN2IN67QQXUj2s/LJ99hxAeGMXzfNkm/NuAgK7O5UZ1OhhoHhrqoHfzFjedhtBiBYabk5niL3wp7jNT1436QYA/qgT4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gentoo.org; spf=pass smtp.mailfrom=gentoo.org; arc=none smtp.client-ip=140.211.166.183 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gentoo.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gentoo.org Received: from [127.0.0.1] (unknown [116.232.18.222]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dlan) by smtp.gentoo.org (Postfix) with ESMTPSA id 559BF340DA1; Fri, 02 Jan 2026 07:01:19 +0000 (UTC) From: Yixun Lan Date: Fri, 02 Jan 2026 15:00:24 +0800 Subject: [PATCH v3 3/4] pinctrl: spacemit: k3: add initial pin support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260102-02-k3-pinctrl-v3-3-30aa104e2847@gentoo.org> References: <20260102-02-k3-pinctrl-v3-0-30aa104e2847@gentoo.org> In-Reply-To: <20260102-02-k3-pinctrl-v3-0-30aa104e2847@gentoo.org> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Troy Mitchell , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, Yixun Lan X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=15217; i=dlan@gentoo.org; h=from:subject:message-id; bh=/MRpvp+cwdSbDmLiFgi17bE8BWDrGFI3hfVNRzFOP5o=; b=owEB6QIW/ZANAwAKATGq6kdZTbvtAcsmYgBpV20pbh+QLHmQMnJHidURSofcEY8SuZidP8Jsj QOv3dH61EeJAq8EAAEKAJkWIQS1urjJwxtxFWcCI9wxqupHWU277QUCaVdtKRsUgAAAAAAEAA5t YW51MiwyLjUrMS4xMSwyLDJfFIAAAAAALgAoaXNzdWVyLWZwckBub3RhdGlvbnMub3BlbnBncC5 maWZ0aGhvcnNlbWFuLm5ldEI1QkFCOEM5QzMxQjcxMTU2NzAyMjNEQzMxQUFFQTQ3NTk0REJCRU QACgkQMarqR1lNu+2IGA/8D1YqsYC9vy2+ZZncd9NtXrwFMbN/ghP1QenjdsHAjcfncLrB/hJD4 E/835Kb9aGt/whyRVMEpK9Vk5dyRArZKJUQqBTKpWNoh3XOnmQHlBJr2Nx+KBT5c2U4v0TKNlS8 cB5PR1KVcFuG4OZZFc9/b1CofY30SXOfz/VlFmWygwNMFHnixHmWcipEYnJ12KM6Fa4dn0RQn8t AHJXqaVqFLSqqbMnhUm82MwZakewVCB758JY7YLtLEh0Ld4TnBq7pskmqjodUjajQGX3ScDVSAm HFH9BHOvJSvX5TgMh+rVvjNKUlO0hMVb6iZCuz5SEu/WKiWAGefYRcD2KQ4z4I1g/igsU12y2Hy 5YY57Vq3nuFCQbhkunsM30x9SH6MyoRnsJL9LyjMXrhrJnzTLezHsuN5aBiI+oR5hlbiybWOKYA 2u20zdYu02qO+RMLHTG7QWMy+q5dUn4shwHyzKzNeBV3PXRhxkLgXNHssuZXcBERAlv7t+w0k9S RTUoluI1NONUypoSBg2BVXxZvCftaHdT9p7iXoJUOQRydcc0UAxzsgnPp2AomRlPkpwiy+NrekD RuCy1O3TV9oVd5yF0ErigkCFx4iM13dQXUyHQtkeMlQNjT+mMIQoofOEh6kuQxGioeTDYlJwgAO xCoWn1Ahw5ZcoQBakEWo+dMrBBuwmg= X-Developer-Key: i=dlan@gentoo.org; a=openpgp; fpr=50B03A1A5CBCD33576EF8CD7920C0DBCAABEFD55 For the pinctrl IP of SpacemiT's K3 SoC, it has different register offset comparing with previous SoC generation, so introduce a function to do the pin to offset mapping. Also add all the pinctrl data. Signed-off-by: Yixun Lan --- drivers/pinctrl/spacemit/Kconfig | 4 +- drivers/pinctrl/spacemit/pinctrl-k1.c | 354 ++++++++++++++++++++++++++++++= +++- 2 files changed, 352 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/spacemit/Kconfig b/drivers/pinctrl/spacemit/Kc= onfig index d6f6017fd097..c021d51033d1 100644 --- a/drivers/pinctrl/spacemit/Kconfig +++ b/drivers/pinctrl/spacemit/Kconfig @@ -4,7 +4,7 @@ # =20 config PINCTRL_SPACEMIT_K1 - bool "SpacemiT K1 SoC Pinctrl driver" + bool "SpacemiT K1/K3 SoC Pinctrl driver" depends on ARCH_SPACEMIT || COMPILE_TEST depends on OF default ARCH_SPACEMIT @@ -12,7 +12,7 @@ config PINCTRL_SPACEMIT_K1 select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF help - Say Y to select the pinctrl driver for K1 SoC. + Say Y to select the pinctrl driver for K1/K3 SoC. This pin controller allows selecting the mux function for each pin. This driver can also be built as a module called pinctrl-k1. diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacem= it/pinctrl-k1.c index 33af9b5791c1..441817f539e3 100644 --- a/drivers/pinctrl/spacemit/pinctrl-k1.c +++ b/drivers/pinctrl/spacemit/pinctrl-k1.c @@ -66,6 +66,7 @@ struct spacemit_pinctrl_data { const struct pinctrl_pin_desc *pins; const struct spacemit_pin *data; u16 npins; + unsigned int (*pin_to_offset)(unsigned int pin); }; =20 struct spacemit_pin_mux_config { @@ -79,7 +80,7 @@ struct spacemit_pin_drv_strength { }; =20 /* map pin id to pinctrl register offset, refer MFPR definition */ -static unsigned int spacemit_pin_to_offset(unsigned int pin) +static unsigned int spacemit_k1_pin_to_offset(unsigned int pin) { unsigned int offset =3D 0; =20 @@ -124,10 +125,17 @@ static unsigned int spacemit_pin_to_offset(unsigned i= nt pin) return offset << 2; } =20 +static unsigned int spacemit_k3_pin_to_offset(unsigned int pin) +{ + unsigned int offset =3D pin > 130 ? (pin + 2) : pin; + + return offset << 2; +} + static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *p= ctrl, unsigned int pin) { - return pctrl->regs + spacemit_pin_to_offset(pin); + return pctrl->regs + pctrl->data->pin_to_offset(pin); } =20 static u16 spacemit_dt_get_pin(u32 value) @@ -177,7 +185,7 @@ static void spacemit_pctrl_dbg_show(struct pinctrl_dev = *pctldev, void __iomem *reg; u32 value; =20 - seq_printf(seq, "offset: 0x%04x ", spacemit_pin_to_offset(pin)); + seq_printf(seq, "offset: 0x%04x ", pctrl->data->pin_to_offset(pin)); seq_printf(seq, "type: %s ", io_type_desc[type]); =20 reg =3D spacemit_pin_to_reg(pctrl, pin); @@ -1042,10 +1050,348 @@ static const struct spacemit_pinctrl_data k1_pinct= rl_data =3D { .pins =3D k1_pin_desc, .data =3D k1_pin_data, .npins =3D ARRAY_SIZE(k1_pin_desc), + .pin_to_offset =3D spacemit_k1_pin_to_offset, +}; + +static const struct pinctrl_pin_desc k3_pin_desc[] =3D { + PINCTRL_PIN(0, "GPIO_00"), + PINCTRL_PIN(1, "GPIO_01"), + PINCTRL_PIN(2, "GPIO_02"), + PINCTRL_PIN(3, "GPIO_03"), + PINCTRL_PIN(4, "GPIO_04"), + PINCTRL_PIN(5, "GPIO_05"), + PINCTRL_PIN(6, "GPIO_06"), + PINCTRL_PIN(7, "GPIO_07"), + PINCTRL_PIN(8, "GPIO_08"), + PINCTRL_PIN(9, "GPIO_09"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "PWR_SCL"), + PINCTRL_PIN(129, "PWR_SDA"), + PINCTRL_PIN(130, "VCXO_EN"), + PINCTRL_PIN(131, "PMIC_INT_N"), + PINCTRL_PIN(132, "MMC1_DAT3"), + PINCTRL_PIN(133, "MMC1_DAT2"), + PINCTRL_PIN(134, "MMC1_DAT1"), + PINCTRL_PIN(135, "MMC1_DAT0"), + PINCTRL_PIN(136, "MMC1_CMD"), + PINCTRL_PIN(137, "MMC1_CLK"), + PINCTRL_PIN(138, "QSPI_DAT0"), + PINCTRL_PIN(139, "QSPI_DAT1"), + PINCTRL_PIN(140, "QSPI_DAT2"), + PINCTRL_PIN(141, "QSPI_DAT3"), + PINCTRL_PIN(142, "QSPI_CS0"), + PINCTRL_PIN(143, "QSPI_CS1"), + PINCTRL_PIN(144, "QSPI_CLK"), + PINCTRL_PIN(145, "PRI_TDI"), + PINCTRL_PIN(146, "PRI_TMS"), + PINCTRL_PIN(147, "PRI_TCK"), + PINCTRL_PIN(148, "PRI_TDO"), + PINCTRL_PIN(149, "PWR_SSP_SCLK"), + PINCTRL_PIN(150, "PWR_SSP_FRM"), + PINCTRL_PIN(151, "PWR_SSP_TXD"), + PINCTRL_PIN(152, "PWR_SSP_RXD"), +}; + +static const struct spacemit_pin k3_pin_data[ARRAY_SIZE(k3_pin_desc)] =3D { + /* GPIO1 bank */ + K1_FUNC_PIN(0, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(1, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(2, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(3, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(4, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(5, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(6, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(7, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(8, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(9, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(10, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(11, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(12, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(13, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(14, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(15, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(16, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(17, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(18, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(19, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(20, 0, IO_TYPE_EXTERNAL), + + /* GPIO2 bank */ + K1_FUNC_PIN(21, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(22, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(23, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(24, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(25, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(26, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(27, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(28, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(29, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(30, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(31, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(32, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(33, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(34, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(35, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(36, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(37, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(38, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(39, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(40, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(41, 0, IO_TYPE_EXTERNAL), + + /* GPIO3 bank */ + K1_FUNC_PIN(42, 0, IO_TYPE_1V8), + K1_FUNC_PIN(43, 0, IO_TYPE_1V8), + K1_FUNC_PIN(44, 0, IO_TYPE_1V8), + K1_FUNC_PIN(45, 0, IO_TYPE_1V8), + K1_FUNC_PIN(46, 0, IO_TYPE_1V8), + K1_FUNC_PIN(47, 0, IO_TYPE_1V8), + K1_FUNC_PIN(48, 0, IO_TYPE_1V8), + K1_FUNC_PIN(49, 0, IO_TYPE_1V8), + K1_FUNC_PIN(50, 0, IO_TYPE_1V8), + K1_FUNC_PIN(51, 0, IO_TYPE_1V8), + K1_FUNC_PIN(52, 0, IO_TYPE_1V8), + K1_FUNC_PIN(53, 0, IO_TYPE_1V8), + K1_FUNC_PIN(54, 0, IO_TYPE_1V8), + K1_FUNC_PIN(55, 0, IO_TYPE_1V8), + K1_FUNC_PIN(56, 0, IO_TYPE_1V8), + K1_FUNC_PIN(57, 0, IO_TYPE_1V8), + K1_FUNC_PIN(58, 0, IO_TYPE_1V8), + K1_FUNC_PIN(59, 0, IO_TYPE_1V8), + K1_FUNC_PIN(60, 0, IO_TYPE_1V8), + K1_FUNC_PIN(61, 0, IO_TYPE_1V8), + K1_FUNC_PIN(62, 0, IO_TYPE_1V8), + K1_FUNC_PIN(63, 0, IO_TYPE_1V8), + K1_FUNC_PIN(64, 0, IO_TYPE_1V8), + K1_FUNC_PIN(65, 0, IO_TYPE_1V8), + K1_FUNC_PIN(66, 0, IO_TYPE_1V8), + K1_FUNC_PIN(67, 0, IO_TYPE_1V8), + K1_FUNC_PIN(68, 0, IO_TYPE_1V8), + K1_FUNC_PIN(69, 0, IO_TYPE_1V8), + K1_FUNC_PIN(70, 0, IO_TYPE_1V8), + K1_FUNC_PIN(71, 0, IO_TYPE_1V8), + K1_FUNC_PIN(72, 0, IO_TYPE_1V8), + K1_FUNC_PIN(73, 0, IO_TYPE_1V8), + K1_FUNC_PIN(74, 0, IO_TYPE_1V8), + K1_FUNC_PIN(75, 0, IO_TYPE_1V8), + + /* GPIO4 bank */ + K1_FUNC_PIN(76, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(77, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(78, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(79, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(80, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(81, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(82, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(83, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(84, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(85, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(86, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(87, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(88, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(89, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(90, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(91, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(92, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(93, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(94, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(95, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(96, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(97, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(98, 0, IO_TYPE_EXTERNAL), + + /* GPIO5 bank */ + K1_FUNC_PIN(99, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(100, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(101, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(102, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(103, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(104, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(105, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(106, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(107, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(108, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(109, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(110, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(111, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(112, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(113, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(114, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(115, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(116, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(117, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(118, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(119, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(120, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(121, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(122, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(123, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(124, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(125, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(126, 0, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(127, 0, IO_TYPE_EXTERNAL), + + /* PMIC */ + K1_FUNC_PIN(128, 0, IO_TYPE_1V8), + K1_FUNC_PIN(129, 0, IO_TYPE_1V8), + K1_FUNC_PIN(130, 0, IO_TYPE_1V8), + K1_FUNC_PIN(131, 0, IO_TYPE_1V8), + + /* SD/MMC1 */ + K1_FUNC_PIN(132, 1, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(133, 1, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(134, 1, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(135, 1, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(136, 1, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(137, 1, IO_TYPE_EXTERNAL), + + /* QSPI */ + K1_FUNC_PIN(138, 1, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(139, 1, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(140, 1, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(141, 1, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(142, 1, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(143, 1, IO_TYPE_EXTERNAL), + K1_FUNC_PIN(144, 1, IO_TYPE_EXTERNAL), + + /* PMIC */ + K1_FUNC_PIN(145, 1, IO_TYPE_1V8), + K1_FUNC_PIN(146, 1, IO_TYPE_1V8), + K1_FUNC_PIN(147, 1, IO_TYPE_1V8), + K1_FUNC_PIN(148, 1, IO_TYPE_1V8), + K1_FUNC_PIN(149, 1, IO_TYPE_1V8), + K1_FUNC_PIN(150, 1, IO_TYPE_1V8), + K1_FUNC_PIN(151, 1, IO_TYPE_1V8), + K1_FUNC_PIN(152, 1, IO_TYPE_1V8), +}; + +static const struct spacemit_pinctrl_data k3_pinctrl_data =3D { + .pins =3D k3_pin_desc, + .data =3D k3_pin_data, + .npins =3D ARRAY_SIZE(k3_pin_desc), + .pin_to_offset =3D spacemit_k3_pin_to_offset, }; =20 static const struct of_device_id k1_pinctrl_ids[] =3D { { .compatible =3D "spacemit,k1-pinctrl", .data =3D &k1_pinctrl_data }, + { .compatible =3D "spacemit,k3-pinctrl", .data =3D &k3_pinctrl_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, k1_pinctrl_ids); @@ -1061,5 +1407,5 @@ static struct platform_driver k1_pinctrl_driver =3D { builtin_platform_driver(k1_pinctrl_driver); =20 MODULE_AUTHOR("Yixun Lan "); -MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1 SoC"); +MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1/K3 SoC"); MODULE_LICENSE("GPL"); --=20 2.52.0