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Thu, 01 Jan 2026 01:03:01 -0800 (PST) From: Nick Chan Date: Thu, 01 Jan 2026 17:01:44 +0800 Subject: [PATCH v10 08/21] drivers/perf: apple_m1: Add Apple A7 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260101-apple-cpmu-v10-8-48812c529ffc@gmail.com> References: <20260101-apple-cpmu-v10-0-48812c529ffc@gmail.com> In-Reply-To: <20260101-apple-cpmu-v10-0-48812c529ffc@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11091; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=Vxh3xXPMwA5ravehvGUi46BNnI9s8ZPMtJUnEDwMDiM=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBpVjgnZDEOtQ3kp+jSzsxlNtW3QbV+XzfZ89ry0 IfSD3yjTvWJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaVY4JwAKCRABygi3psUI JN9sD/0QKltr1O9Kp63u3VQY7Apw+tlpEmMT/SNit4n9TuDPK1c9QXHR9E5Q7+JNnK4LcMDMV5u gmh5aK7CLtjgZsJlQh3x01vJRusIC5NXukpCXjZ8s+xiRiKJRtUlZ5qv375SIluh+YJdj/53RNp YvDirqdX58uDW85/yZL1d27MALJK52fCiTM+9ZrThagWv9xCDoLyBpovgHqnbgki8oiFnAl0U/D 8atZXmb6aTdC+0K5k8EuhlO6z+RrZ4Y8Qaw6wfU24q366y0GscUq7Wk+XPfjeS5pOVmwlj2nGZP w6pRApNfPi1squ82ZImX2OUJVbIyi3U6zVLKbLg9QtrbzNC5zwwhLMh7iG1CFotoQhoE86LwU3P zzoe4aZUu+8M59Bo0FqDXcGNmuGK2w1FWXchAlSQqCAWM9gX2LjZG+brIUdJfNM3zHrHv0mx97o ymss0B7inTmmEius6dl9x8Z5awGARmg87Zphl5K97w3P/KmohO1NwVeWmyWvzp5S4lvd+OEx2xJ V97OywAQwdGZ1qoxlQhth0pT0Zp6Wda1pnJo3fhRfxnHacxA9ALjzS0IApALXBLz3JyIRGuzbnw CqRZu2/EJCoJmMNJqRBa6bqBMvHH+ti/6on6glSX3QekZcIEGKt91EKxYU1TB3DPfGoywigmiTd i2ng2/s3j08Bjrg== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found in the Apple A7 SoC. The PMU has 8 counters and a very different event layout compared to the M1 PMU. Interrupts are delivered as IRQs instead of FIQs like on the M1. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 191 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 191 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index f903cebf566be6b40f260d81a70cefa4858bc085..68c7a1ee0b0e43993d9e4f437de= f15bee771a364 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -19,6 +19,7 @@ #include #include =20 +#define A7_PMU_NR_COUNTERS 8 #define M1_PMU_NR_COUNTERS 10 #define APPLE_PMU_MAX_NR_COUNTERS 10 =20 @@ -45,6 +46,143 @@ * know next to nothing about the events themselves, and we already have * per cpu-type PMU abstractions. */ + +enum a7_pmu_events { + A7_PMU_PERFCTR_INST_ALL =3D 0x0, + A7_PMU_PERFCTR_UNKNOWN_1 =3D 0x1, + A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A7_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0x10, + A7_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0x11, + A7_PMU_PERFCTR_BIU_UPSTREAM_CYCLE =3D 0x19, + A7_PMU_PERFCTR_BIU_DOWNSTREAM_CYCLE =3D 0x20, + A7_PMU_PERFCTR_L2C_AGENT_LD =3D 0x22, + A7_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x23, + A7_PMU_PERFCTR_L2C_AGENT_ST =3D 0x24, + A7_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x25, + A7_PMU_PERFCTR_SCHEDULE_UOP =3D 0x58, + A7_PMU_PERFCTR_MAP_REWIND =3D 0x61, + A7_PMU_PERFCTR_MAP_STALL =3D 0x62, + A7_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x6e, + A7_PMU_PERFCTR_INST_A32 =3D 0x78, + A7_PMU_PERFCTR_INST_T32 =3D 0x79, + A7_PMU_PERFCTR_INST_A64 =3D 0x7a, + A7_PMU_PERFCTR_INST_BRANCH =3D 0x7b, + A7_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x7c, + A7_PMU_PERFCTR_INST_BRANCH_RET =3D 0x7d, + A7_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x7e, + A7_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x81, + A7_PMU_PERFCTR_INST_BRANCH_COND =3D 0x82, + A7_PMU_PERFCTR_INST_INT_LD =3D 0x83, + A7_PMU_PERFCTR_INST_INT_ST =3D 0x84, + A7_PMU_PERFCTR_INST_INT_ALU =3D 0x85, + A7_PMU_PERFCTR_INST_SIMD_LD =3D 0x86, + A7_PMU_PERFCTR_INST_SIMD_ST =3D 0x87, + A7_PMU_PERFCTR_INST_SIMD_ALU =3D 0x88, + A7_PMU_PERFCTR_INST_LDST =3D 0x89, + A7_PMU_PERFCTR_UNKNOWN_8d =3D 0x8d, + A7_PMU_PERFCTR_UNKNOWN_8e =3D 0x8e, + A7_PMU_PERFCTR_UNKNOWN_8f =3D 0x8f, + A7_PMU_PERFCTR_UNKNOWN_90 =3D 0x90, + A7_PMU_PERFCTR_UNKNOWN_93 =3D 0x93, + A7_PMU_PERFCTR_UNKNOWN_94 =3D 0x94, + A7_PMU_PERFCTR_UNKNOWN_95 =3D 0x95, + A7_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0x96, + A7_PMU_PERFCTR_L1D_TLB_MISS =3D 0x97, + A7_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0x98, + A7_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0x99, + A7_PMU_PERFCTR_UNKNOWN_9b =3D 0x9b, + A7_PMU_PERFCTR_LD_UNIT_UOP =3D 0x9c, + A7_PMU_PERFCTR_ST_UNIT_UOP =3D 0x9d, + A7_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0x9e, + A7_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A7_PMU_PERFCTR_LDST_X64_UOP =3D 0xa7, + A7_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xb4, + A7_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xb5, + A7_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xb6, + A7_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xb9, + A7_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xba, + A7_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xbb, + A7_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xbd, + A7_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xbf, + A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xc0, + A7_PMU_PERFCTR_UNKNOWN_c1 =3D 0xc1, + A7_PMU_PERFCTR_UNKNOWN_c4 =3D 0xc4, + A7_PMU_PERFCTR_UNKNOWN_c5 =3D 0xc5, + A7_PMU_PERFCTR_UNKNOWN_c6 =3D 0xc6, + A7_PMU_PERFCTR_UNKNOWN_c8 =3D 0xc8, + A7_PMU_PERFCTR_UNKNOWN_ca =3D 0xca, + A7_PMU_PERFCTR_UNKNOWN_cb =3D 0xcb, + A7_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xce, + A7_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xcf, + A7_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A7_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A7_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A7_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, + A7_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, + A7_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A7_PMU_CFG_COUNT_USER =3D BIT(8), + A7_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a7_pmu_event_affinity[A7_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A7_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A7_PMU_PERFCTR_INST_ALL] =3D ANY_BUT_0_1 | BIT(1), + [A7_PMU_PERFCTR_UNKNOWN_1] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A7_PMU_PERFCTR_INST_A32] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_T32] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_A64] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_ALU] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_ALU] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8d] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8e] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8f] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_90] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_93] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_94] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_95] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_ST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_LD] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_9b] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_LD_UNIT_UOP] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_9f] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c1] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c4] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c5] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c6] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c8] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_ca] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_cb] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -165,6 +303,14 @@ static const u16 m1_pmu_event_affinity[M1_PMU_PERFCTR_= LAST + 1] =3D { [M1_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, }; =20 +static const unsigned int a7_pmu_perf_map[PERF_COUNT_HW_MAX] =3D { + PERF_MAP_ALL_UNSUPPORTED, + [PERF_COUNT_HW_CPU_CYCLES] =3D A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE, + [PERF_COUNT_HW_INSTRUCTIONS] =3D A7_PMU_PERFCTR_INST_ALL, + [PERF_COUNT_HW_BRANCH_MISSES] =3D A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =3D A7_PMU_PERFCTR_INST_BRANCH +}; + static const unsigned m1_pmu_perf_map[PERF_COUNT_HW_MAX] =3D { PERF_MAP_ALL_UNSUPPORTED, [PERF_COUNT_HW_CPU_CYCLES] =3D M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE, @@ -199,6 +345,17 @@ static ssize_t m1_pmu_events_sysfs_show(struct device = *dev, #define M1_PMU_EVENT_ATTR(name, config) \ PMU_EVENT_ATTR_ID(name, m1_pmu_events_sysfs_show, config) =20 +static struct attribute *a7_pmu_event_attrs[] =3D { + M1_PMU_EVENT_ATTR(cycles, A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE), + M1_PMU_EVENT_ATTR(instructions, A7_PMU_PERFCTR_INST_ALL), + NULL, +}; + +static const struct attribute_group a7_pmu_events_attr_group =3D { + .name =3D "events", + .attrs =3D a7_pmu_event_attrs, +}; + static struct attribute *m1_pmu_event_attrs[] =3D { M1_PMU_EVENT_ATTR(cycles, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE), M1_PMU_EVENT_ATTR(instructions, M1_PMU_PERFCTR_INST_ALL), @@ -522,6 +679,13 @@ static int apple_pmu_get_event_idx(struct pmu_hw_event= s *cpuc, return -EAGAIN; } =20 +static int a7_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a7_pmu_event_affinity, + A7_PMU_NR_COUNTERS); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -546,6 +710,11 @@ static void __m1_pmu_set_mode(u8 mode) isb(); } =20 +static void a7_pmu_start(struct arm_pmu *cpu_pmu) +{ + __m1_pmu_set_mode(PMCR0_IMODE_AIC); +} + static void m1_pmu_start(struct arm_pmu *cpu_pmu) { __m1_pmu_set_mode(PMCR0_IMODE_FIQ); @@ -580,6 +749,11 @@ static int apple_pmu_map_event_63(struct perf_event *e= vent, return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); } =20 +static int a7_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_47(event, &a7_pmu_perf_map); +} + static int m1_pmu_map_event(struct perf_event *event) { return apple_pmu_map_event_47(event, &m1_pmu_perf_map); @@ -625,6 +799,11 @@ static void apple_pmu_reset(void *info, u32 counters) isb(); } =20 +static void a7_pmu_reset(void *info) +{ + apple_pmu_reset(info, A7_PMU_NR_COUNTERS); +} + static void m1_pmu_reset(void *info) { apple_pmu_reset(info, M1_PMU_NR_COUNTERS); @@ -675,6 +854,17 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32= nr_counters) } =20 /* Device driver gunk */ +static int a7_pmu_cyclone_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_cyclone_pmu"; + cpu_pmu->get_event_idx =3D a7_pmu_get_event_idx; + cpu_pmu->map_event =3D a7_pmu_map_event; + cpu_pmu->reset =3D a7_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &a7_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -724,6 +914,7 @@ static const struct of_device_id m1_pmu_of_device_ids[]= =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,cyclone-pmu", .data =3D a7_pmu_cyclone_init, }, { }, }; MODULE_DEVICE_TABLE(of, m1_pmu_of_device_ids); --=20 2.52.0