From nobody Sat Feb 7 08:07:12 2026 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEF51749C for ; Thu, 1 Jan 2026 09:03:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767258197; cv=none; b=gnvtu/MfONu17Ookus2U0iyt7+DQRDg3fPz5qthVI2jIb5QGVpYvFrpN3CcdcCQ2k/xqt43XmKUesbITaLCSzjRMGuMCUgVouC1DU/LKGV6Itg1yo8vhgKZgybI3/GSIzPRetPlyyJ03vrnb9hNlJ0KRdNayIK2mqmyYztN7QK0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767258197; c=relaxed/simple; bh=x0Cq2iz5KjiCkyeJ7YF8BxUETaGjpABGcg5ZPiVTUOA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qjq7qtBcfyKBDTGoLVp+4T9/g1eneF1t8dsO7GwdBldPQGrx8zc096o1qEsqGUVHUaUNowe2IzZr4sXpgDeevNfA5YW9QwReD3fM1olBaqk3z4A7fJ51bOne/pdmN6yLX2k6RD9IuNi9QOTh9sHODHiE9GVCbE3f9EThyQyJN6Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=RysTgo0M; arc=none smtp.client-ip=209.85.210.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="RysTgo0M" Received: by mail-pf1-f169.google.com with SMTP id d2e1a72fcca58-7b9c17dd591so9647365b3a.3 for ; Thu, 01 Jan 2026 01:03:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1767258195; x=1767862995; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Y/MCZJZdSCnmXMnq5tn+XRZReSP8mv4rySs4OgIA3WA=; b=RysTgo0MM1qP7qGvwSbR7cDx9viMo88Yk9vz4e0C5I31NQEpDVyPrzl50tmXtxQMcE bsVNCFOke4tt1SGu5dXylzwW+BWoK7WECsj+6NYHZU6Z3FOM30obizjtws9R/RzrNcEq SnfgJN70YKXikHmxn5jDs7z28ISjeeyVa/e3TQ8E3MnabyEDhC1mshQ2J+FOeHlt4prz 9CExoNO0ZcA11CLs6FNR3jDrCHmv/lQeQDbIBD5VxTMK7buhnkEPgvP6AxBfmOjfUE7g Oe01AERhEaj2R5ImCJr3LkxZtYdYj4atf1oIlx4uZPzqUVJHUZ2BRvx82v1X7D+irN+n lZCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767258195; x=1767862995; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Y/MCZJZdSCnmXMnq5tn+XRZReSP8mv4rySs4OgIA3WA=; b=De/NCvnm0V00C3mWsaM3ZoIGvT1unt6AawZdtM0KRyr9VK/XFXr2zDhJKa3FVk7ymc h+Jnh+ph2Qn7uThgHY6xESQx9aP2JCNXqFZjHSEzVBVLFterJ50DA8PlfrErnmNyAiN5 X3as07p3Wne9rHA+jLxE/C7S46V3U2oDRCRgAfwXFnkpJcW3gzzfY0jt9SsNBrJf2QsH mT5XoqoSwXFXfbmnGNi/kI13Q8905AinL0NAtU+s6PiDl/Vv4TWBkbmslaId1bJFwGgo Nc/6vXnhADXiyuVIiRlabRgPT0jYhuZtDecdJFaiN6J0cxRzc0a/v5WVuOTMjD5CjpKg Iupw== X-Forwarded-Encrypted: i=1; AJvYcCXH3yJD4rndweD7s694NHN2j+mjApdRV9KVRrMd5JjkKbctW2OaldFH/fMwa4YWasInHCI2yApey868i6o=@vger.kernel.org X-Gm-Message-State: AOJu0YzoxxyewGDPrLdleo2LUc7YhFWDIn+lg4jP3st2E1yY/ziDT12r O5ThfRYvowQa686RKQqRCHiKXCBy8mmXgy1p2aRuQkCcsVmjpPsE4eXt X-Gm-Gg: AY/fxX6XzblnIG/0ga41lBIAChlgzGJk8mLESnHGotsJlj5Htx6LWm4bqk8c7iMNr/+ IAJgZ4MXKLtnmVBtUeP+rUETnMYctDLmE1ktbfy4QijopTx2ckgM0jqQ6ZN7w4utlACXMv/GSaT SbXV7A6dJ9UAS7I7jM570UwyB3pUqO6qtp5noCvNvNU4faGaKGDuZve168dyo+Q7G+GGhRxgMHy Dd2WpD60Usqt+1hL8t4mScKlDArtYE8z0Illccy5DqLAa+3uawc1sj/P1dIYeJ/7mB1ARFlMqwx E3OF1SAOVCZ9+QCAvVAXmjN/URcGCOcEgL1cd9dujbqmEYeQ/oz1D16nfNTfdlUXS4y9qPZxzsm TxQmdoLe0qAE4oe6rPZyeErKUpEynGoETICgX/d5Uy8snQ0ldltLFZBxSY9RiSwmcI44lg81zss fDTHFV/EEywzGn X-Google-Smtp-Source: AGHT+IFPbMrtQ8L75en86FOgy1+ozYTQh8z4gOoC4ANwDEDFoyox1rgTrNTjsGtbnK26pa2nvdXe+g== X-Received: by 2002:a05:6a00:3285:b0:781:2740:11b2 with SMTP id d2e1a72fcca58-7ff648e61aemr37085450b3a.25.1767258195090; Thu, 01 Jan 2026 01:03:15 -0800 (PST) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d2e1a72fcca58-7ff7dfac29bsm37182957b3a.39.2026.01.01.01.03.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jan 2026 01:03:14 -0800 (PST) From: Nick Chan Date: Thu, 01 Jan 2026 17:01:48 +0800 Subject: [PATCH v10 12/21] drivers/perf: apple_m1: Add Apple A11 Support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260101-apple-cpmu-v10-12-48812c529ffc@gmail.com> References: <20260101-apple-cpmu-v10-0-48812c529ffc@gmail.com> In-Reply-To: <20260101-apple-cpmu-v10-0-48812c529ffc@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7908; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=x0Cq2iz5KjiCkyeJ7YF8BxUETaGjpABGcg5ZPiVTUOA=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBpVjgo05Q8bvLxJVWQ3+PICPel0cx2rwTCZvbSM 7spF9Z+kjWJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaVY4KAAKCRABygi3psUI JKXPD/0a6VER715ut88ocHJj+ZA3cUb1qjvNI1vPsQHZxuEG9UaQ0OUukgod1bPL7NdPclDtZ04 RHKa3/WyeXJiREwrYyBVuvO4DWVv440uX2oPJBAVWn5HPOab98+HJ5/w3z+RhEit8f/IWBlTfA+ KN0JH3PiS4w6PXJV4EsTaGlvtW/lKNn7ztx7v81Yggg671aDjsnQ1hs2ADtO4p7GcwU9zKDxjUE O05AvyUtV8irMXR/k3JIe0/+vIUKY6BAIvE35BFNTV1TJDXqdgyUZurbhEsVFXHb6n3zcS9WdCw VYh/Ptwl7Qy8M4+bCg6zdOd+r8vmhD91JsWeUKThMGhUR5opPHwckcXatxKev6D9q0BsdYqJMKG OfNlbWGwNJQ13yxXTDan4DO0MkinZekDipdqOhuQ/ZeS4fIXQqh3W20XynJxBAbNxiWvbCp/IRq 4VO1ybZWant2/TbvPfmObZVmodVVXxuhMlD0l2EHOIcPDpLd8j+USIDF5HUvi4pjw4jo49+pL6R 07L2BxOgXUBotM0zlaYRMWdJoajJsNDw2v/SAo8sJtd2G/sxEMdcoOXHrsoJ6iA8rDFTxfLOY9X ZrFpqwajXKWIKgq9lsyEYOGxu8D0JlZm1IR5Rau4HECeTJ8F870RMkPK7mEkKKmvNW2Aevfuf5l jMtXOKlbWDHd8zQ== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found attached to the performance and efficiency cores of the Apple A11 SoCs. This PMU can deliver its interrupt via IRQ or FIQ. Use FIQ as that is faster. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 136 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 136 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index c7f58f53a5aab5cf421c5bda82e57acac9b92a81..23cff6e6c4e701b086ffc7fafd7= 2e4be1aa26a8f 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -509,6 +509,111 @@ static const u16 a10_pmu_event_affinity[A10_PMU_PERFC= TR_LAST + 1] =3D { [A10_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, }; =20 +enum a11_pmu_events { + A11_PMU_PERFCTR_RETIRE_UOP =3D 0x1, + A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A11_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A11_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A11_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A11_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A11_PMU_PERFCTR_MAP_STALL =3D 0x76, + A11_PMU_PERFCTR_MAP_INT_UOP =3D 0x7c, + A11_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7d, + A11_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7e, + A11_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A11_PMU_PERFCTR_INST_ALL =3D 0x8c, + A11_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A11_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A11_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A11_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A11_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A11_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A11_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A11_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A11_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A11_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A11_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A11_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A11_PMU_PERFCTR_INST_LDST =3D 0x9b, + A11_PMU_PERFCTR_INST_BARRIER =3D 0x9c, + A11_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A11_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A11_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A11_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A11_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A11_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A11_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A11_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A11_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC =3D 0xb3, + A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL =3D 0xb4, + A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A11_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A11_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A11_PMU_PERFCTR_MAP_DISPATCH_BUBBLE =3D 0xd6, + A11_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND =3D 0xdb, + A11_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A11_PMU_PERFCTR_ST_NT_UOP =3D 0xe5, + A11_PMU_PERFCTR_LD_NT_UOP =3D 0xe6, + A11_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A11_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A11_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A11_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, + A11_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, + A11_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A11_PMU_CFG_COUNT_USER =3D BIT(8), + A11_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a11_pmu_event_affinity[A11_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A11_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A11_PMU_PERFCTR_RETIRE_UOP] =3D BIT(7), + [A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A11_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A11_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_ALU] =3D BIT(7), + [A11_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_SIMD_ALU] =3D BIT(7), + [A11_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BARRIER] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), + [A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f8] =3D ONLY_2_TO_7, + [A11_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -1033,6 +1138,13 @@ static int a10_pmu_get_event_idx(struct pmu_hw_event= s *cpuc, M1_PMU_NR_COUNTERS); } =20 +static int a11_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a11_pmu_event_affinity, + M1_PMU_NR_COUNTERS); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -1245,6 +1357,28 @@ static int a10_pmu_fusion_init(struct arm_pmu *cpu_p= mu) return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 +static int a11_pmu_monsoon_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_monsoon_pmu"; + cpu_pmu->get_event_idx =3D a11_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + +static int a11_pmu_mistral_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_mistral_pmu"; + cpu_pmu->get_event_idx =3D a11_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -1294,6 +1428,8 @@ static const struct of_device_id m1_pmu_of_device_ids= [] =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,monsoon-pmu", .data =3D a11_pmu_monsoon_init, }, + { .compatible =3D "apple,mistral-pmu", .data =3D a11_pmu_mistral_init, }, { .compatible =3D "apple,fusion-pmu", .data =3D a10_pmu_fusion_init, }, { .compatible =3D "apple,twister-pmu", .data =3D a9_pmu_twister_init, }, { .compatible =3D "apple,typhoon-pmu", .data =3D a8_pmu_typhoon_init, }, --=20 2.52.0