From nobody Sat Feb 7 08:07:15 2026 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75C80284B25 for ; Thu, 1 Jan 2026 09:03:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767258191; cv=none; b=napNz0JR78Wg1ebuJ7TK1/F7AtFHNwcyzgR/+nOxICfXTowL1Nk1xsuK3WkKuFbLi1q/fE0xBSlF8LnDMgGyA6E1ZTCKVEhppT5VthzEMrAogMoSYC0eai6JyqPMjZwA+SbI1DnNXiOi1hKh0YQpXMFoC/T49ieCvMk5wIMUuqY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767258191; c=relaxed/simple; bh=oVjy541ZBoiQRLhg3yJtDhlPYNwhomAgw5k8/id/+cE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ccg6IQAgt1dK+1yELh40zM8NuGlk9/zrqRiUIN6MOg8f6R+Dbw5coLFgui94U1sfYdTN4mNbGcGfVt/8GYowcipGY00H6t2ig6DVROYQBGras2PERdZCqzHm6w/FdB7riNW4IAGq8iyxV0kNJxOTNmbOADfoMfTquq4Q6OGYoCw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=cTbHNbWh; arc=none smtp.client-ip=209.85.214.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="cTbHNbWh" Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-2a0bb2f093aso114260965ad.3 for ; Thu, 01 Jan 2026 01:03:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1767258189; x=1767862989; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=R9+piKMs9G1VmQiTpap3yj2Hp00XA4sCypGJ/MWdS5Q=; b=cTbHNbWhhRMaXwXHvclCx7RVfwPWlQiw1aDrbVnP9s7p6EmmaxlkmAItvMIfsL+dZ5 gMWUEIueITNA520FPZCOAi1u5pJyn3bbTGkd8DWGI9ni+s5UNhZRBk/hp4vN4cKNAshe jb0wNYAFlKKYsMllBk+wgwVSGvT/oQYfgYcObo+U7RkyMzF6j5XNThiEYv6kSbEmttdG 3Z9JP+O62Qxgjankknb0ZRlF8kC9ZtCeRPVIIL/0K91sxxRmPQ7ZBiQJIvHs0F0bi8iM +QJXnw41l2kfSIivXAmmUgAwMx+Adr7n9A+IlmSXyyMmyMsm5kGJZ2tjzHdIW+zsUdYs Q9sQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1767258189; x=1767862989; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=R9+piKMs9G1VmQiTpap3yj2Hp00XA4sCypGJ/MWdS5Q=; b=KgXzFe8u+V4mt4BFTfRoGJ/M4vCQKfcfv4UHnFHw94oXUo3c46nFtlAFpL6hCvhSQX skg08onh1UYso9K2Kt69Pu7glQWTvFyRKHBU4ecZFn0wkwzKROCLJzza3fzREzXgB7Fz McCo1krgr+QBJUDUVuXCK0jF+jvK7pY4IDJroM+zQ/ppk6YuDwULzkffQCB9eWp5/sr8 P/Gj/kqQua7xG61akIOOPy8YDPEwiknfeRCiFE/ynXic46ROVL802ZGMW8ZkhkPPNzoo H9Mm3bvHYnlymPKNdRc9l+3dnUrXyhZzhoRdM7sKH09eDWO2+Iqtb9j9Yt/SocWNODMd G7Cg== X-Forwarded-Encrypted: i=1; AJvYcCVDXQGiBKektNWXHBtQUVejBLHz2Oai8VG1e7vzQj8Sq+itJ1z/zUE05Nt0o/osYUn+IF5XJJddpUgciqg=@vger.kernel.org X-Gm-Message-State: AOJu0Yz0FKPRcCrwR0fl9Ad6itWurMdadNgZYNlsY6hZ1zokdkPNFBi4 Oi1UJa+us3aqrA2RDmBwsy3eRCDHoHe0Cbvo3DD4UWsI4yZIb8h9LSm8C2l0Vg== X-Gm-Gg: AY/fxX7bhjYfkiaP6o/8Bygzx3bXFQMrogaE88IwyoVJ7NiQDA/SBjCE0wI28fUjZ6x nsgzcbaZ7plzHAd1esfXLx7SejYo8Sq182PcqnZY6qoDmJ1c1icHjWDMxV+Vet3pP7FLkRASviM LMhY/nyRcphcdFMIowVmHl3AXNn/61eyE7VSWsScj5ZY8hQiP5YPw7MlpLZA8QPYIg9SrFvHdRo tKuyoQHajMUQd0N96ZdLIEWhyTCoWi7wfSrEp6PVEDcIa196OSCT7wqtNT6euRSnuThsvNBtU7y 4Jn34JTl0+C3XJ1UFviT5tdoM0OMyZxb7a+SSOgkpM49VQ3kuW7rC7WTaFKGcty/ZLmMX6ASt9w pKyqyNmHHXdYmIToTrNZn1i5jJ3rULnKnJu0ES0v14tIR9YK3+7jCzF7c/BQl8EP8sKPzox13tB vx4zwsTGMvqTJ8 X-Google-Smtp-Source: AGHT+IG5e2xC8neFWXScdjmBlYktxqiTkUekJYUnYqefzLOE2TQp1Vdct7IJHfwRyqzlQJMS2iUOMw== X-Received: by 2002:a17:902:ecc8:b0:2a0:a4b7:44af with SMTP id d9443c01a7336-2a2f232bb66mr312113185ad.26.1767258188670; Thu, 01 Jan 2026 01:03:08 -0800 (PST) Received: from [127.0.1.1] ([59.188.211.98]) by smtp.googlemail.com with ESMTPSA id d2e1a72fcca58-7ff7dfac29bsm37182957b3a.39.2026.01.01.01.03.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jan 2026 01:03:08 -0800 (PST) From: Nick Chan Date: Thu, 01 Jan 2026 17:01:46 +0800 Subject: [PATCH v10 10/21] drivers/perf: apple_m1: Add A9/A9X support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260101-apple-cpmu-v10-10-48812c529ffc@gmail.com> References: <20260101-apple-cpmu-v10-0-48812c529ffc@gmail.com> In-Reply-To: <20260101-apple-cpmu-v10-0-48812c529ffc@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Neal Gompa , Sven Peter Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7154; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=oVjy541ZBoiQRLhg3yJtDhlPYNwhomAgw5k8/id/+cE=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBpVjgncoCTt+ciC+1PLUm11mFFPV2nA2i1R1w9X lHzlgeHgVqJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaVY4JwAKCRABygi3psUI JHY9D/0aADWM1apo1lxJlfin56ZAnvAD6UHgG7mD8ziOpcxv8mesbSBVwmQZD4VWk5YUs0RISS2 tuuCSHFw+//wZFa59pV9TLuKV+5tPif2pXdBFCyK0OMBN2VTNBJA/fGID4ntnA2f/UObT0Iau2D eY1t1fMxdweyfmahdw7EkbMSqXRlLeINMOYSSby/egqFsWa6QxZHyzLav9/Vt7nCfjCjJqu2x56 6VzBM20Hy4y+oVVhnoBkI6vHbr8o4zNfFwPpPk6ZDVUrsv4qCye1ikCj/93zxM15jC/zgMGU5DQ b4Xp7tMfIOhEiFfLBOm+2bRzeHOCkeRCKl7ab60QhyI1d8eAEGwkkkpzTq0rMAB+mL0mlbhyTi9 LjL9z1lt0Bz+6I0giYbQEUGbSUkz1WUgcbOGGMHO8lf7uD7ku6jeV6zqN8ys71jx0TyMAB67ZIJ 9G94S6EdNlVlQEjHujrVUCi2XC7YL9o/6E55zs12esFI8RvilElHuHEKeSO+TZc2krohy3dJCLN DBhlgqHyHdRTfx1Jq7onXJ5R3m/VOaMVrHQvE5k1Q/z+e/nJwIy29iWfQKWq2KZguIjSqORHAmP GrFPw6uVCE62KxcCbAHDUjFcXX6LlzeU3LMgeqtFlm8SMinaGCksqow3Xr2tXIIs2uOr+06un1X kPMLPXOrdCJOLGg== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for CPU PMU found in the Apple A9 and A9X SoCs. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 126 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 126 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 512b3186326b12627febd033886774ba44641846..fbf13e1ab5c0b61f60a1bcf1e66= cb179ae7dc809 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -289,6 +289,113 @@ static const u16 a8_pmu_event_affinity[A8_PMU_PERFCTR= _LAST + 1] =3D { [A8_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, }; =20 + +enum a9_pmu_events { + A9_PMU_PERFCTR_UNKNOWN_1 =3D 0x1, + A9_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A9_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A9_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A9_PMU_PERFCTR_L2C_AGENT_LD =3D 0x1a, + A9_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x1b, + A9_PMU_PERFCTR_L2C_AGENT_ST =3D 0x1c, + A9_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x1d, + A9_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A9_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A9_PMU_PERFCTR_MAP_STALL =3D 0x76, + A9_PMU_PERFCTR_MAP_INT_UOP =3D 0x7c, + A9_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7d, + A9_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7e, + A9_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A9_PMU_PERFCTR_INST_A32 =3D 0x8a, + A9_PMU_PERFCTR_INST_T32 =3D 0x8b, + A9_PMU_PERFCTR_INST_ALL =3D 0x8c, + A9_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A9_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A9_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A9_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A9_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A9_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A9_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A9_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A9_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A9_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A9_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A9_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A9_PMU_PERFCTR_INST_LDST =3D 0x9b, + A9_PMU_PERFCTR_INST_BARRIER =3D 0x9c, + A9_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A9_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A9_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A9_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A9_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A9_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A9_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A9_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A9_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A9_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC =3D 0xb3, + A9_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL =3D 0xb4, + A9_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A9_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A9_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A9_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A9_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A9_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A9_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A9_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A9_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A9_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A9_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A9_PMU_PERFCTR_MAP_DISPATCH_BUBBLE =3D 0xd6, + A9_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A9_PMU_PERFCTR_ST_NT_UOP =3D 0xe5, + A9_PMU_PERFCTR_LD_NT_UOP =3D 0xe6, + A9_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A9_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A9_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A9_PMU_CFG_COUNT_USER =3D BIT(8), + A9_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a9_pmu_event_affinity[A9_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A9_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A9_PMU_PERFCTR_UNKNOWN_1] =3D BIT(7), + [A9_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A9_PMU_PERFCTR_INST_A32] =3D BIT(7), + [A9_PMU_PERFCTR_INST_T32] =3D BIT(7), + [A9_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A9_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_ALU] =3D BIT(7), + [A9_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_SIMD_ALU] =3D BIT(7), + [A9_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BARRIER] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), + [A9_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_3_5_7, + [A9_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -799,6 +906,13 @@ static int a8_pmu_get_event_idx(struct pmu_hw_events *= cpuc, A7_PMU_NR_COUNTERS); } =20 +static int a9_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a9_pmu_event_affinity, + A7_PMU_NR_COUNTERS); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -989,6 +1103,17 @@ static int a8_pmu_typhoon_init(struct arm_pmu *cpu_pm= u) return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); } =20 +static int a9_pmu_twister_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_twister_pmu"; + cpu_pmu->get_event_idx =3D a9_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D a7_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -1038,6 +1163,7 @@ static const struct of_device_id m1_pmu_of_device_ids= [] =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,twister-pmu", .data =3D a9_pmu_twister_init, }, { .compatible =3D "apple,typhoon-pmu", .data =3D a8_pmu_typhoon_init, }, { .compatible =3D "apple,cyclone-pmu", .data =3D a7_pmu_cyclone_init, }, { }, --=20 2.52.0