From nobody Sat Feb 7 18:20:28 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E08C215B998; Wed, 31 Dec 2025 22:49:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767221382; cv=none; b=hEfw32Hp466Uwij7f/abx7irLwviT60pXaYapqMVD8zGikVuFxJHoVkDa7CWvPpNF2qcKawhnqYr9YqHM1GFbSWcWJr10AZetMbprZkXXZ/LUDzbHJptBvw+TnXXcXe+jqhs2TwQHbm77LcSu3V0xC+/82QJ7+B+q00nIIyyugM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767221382; c=relaxed/simple; bh=+B9k2LapldhEnhYpbP7FbCC2iA89rokPv+/1k44Le5c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jXuvDOKXopDdigqgk44MVP60Vk/v2aXEGmVEvp5UUhqpARF+76WUuV45zWh6PgIW/3BZvyrwhvV6otx8CoJfd31nfGtRRmniZZengybKizP3id5kmb+rri2Ot2Y4Pxcc9crJRThzdX1ZRQ2VaW2xqkbpRNNVmOFXZPnT25yXUP8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MisbDMzt; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MisbDMzt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1767221381; x=1798757381; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+B9k2LapldhEnhYpbP7FbCC2iA89rokPv+/1k44Le5c=; b=MisbDMztjaRrLDvi/HcHU7s2xdB/zbfR2JhDEVq5/LJSSU8O8F+3ojej gnquxSzaDXVU7RkgB97Y/Xy3ylOGff0wXER7Fwh0EKjJp5Zt39gtFwy0J BCfgmmnOsJiI2rTsV2g5hsyg4KvUhqk/BA8doMisC+6iT/H2R8HbMl91r WY4sOlv3/YO0X9SJQnNK5XAb3HKXWdMV+dt+8G28w1re0N3LiBL6NuvWz tlf5YSgkbTT3mAoFRcbgVIwkcr8u0Y5dd4kipFu/u7AlCcFbpSQVftW2U ED7xtUBNpFtD9ZU0BKteU0uXMbv485LdmuPEcraVHNns7KmwnAP5hYwqN w==; X-CSE-ConnectionGUID: GZEoyy7oT7GxQKDWTESd+g== X-CSE-MsgGUID: 1+fen45ZQYqMhfCI8pDUjQ== X-IronPort-AV: E=McAfee;i="6800,10657,11658"; a="68816603" X-IronPort-AV: E=Sophos;i="6.21,193,1763452800"; d="scan'208";a="68816603" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Dec 2025 14:49:39 -0800 X-CSE-ConnectionGUID: 3xG7iYO9QMGihn0h40zxpw== X-CSE-MsgGUID: mUycKkQuQtGKmD+Orxqr1g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,193,1763452800"; d="scan'208";a="232611004" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Dec 2025 14:49:39 -0800 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Xudong Hao , Falcon Thomas Subject: [PATCH V2 01/13] perf/x86/intel/uncore: Move uncore discovery init struct to header Date: Wed, 31 Dec 2025 14:42:18 -0800 Message-ID: <20251231224233.113839-2-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251231224233.113839-1-zide.chen@intel.com> References: <20251231224233.113839-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The discovery base MSR or PCI device is platform-specific and must be defined statically in the per-platform init table and passed to the discovery code. Move the definition of struct intel_uncore_init_fun to uncore.h so it can be accessed by discovery code, and rename it to reflect that it now carries more than just init callbacks. Shorten intel_uncore_has_discovery_tables[_pci/msr] to uncore_discovery[_pci/msr] for improved readability and alignment. Drop the `intel_` prefix from new names since the code is under the intel directory and long identifiers make alignment harder. Further cleanups will continue removing `intel_` prefixes. No functional change intended. Signed-off-by: Zide Chen Reviewed-by:=C2=A0 Dapeng Mi --- V2: New patch arch/x86/events/intel/uncore.c | 72 ++++++++++-------------- arch/x86/events/intel/uncore.h | 10 ++++ arch/x86/events/intel/uncore_discovery.c | 12 ++-- arch/x86/events/intel/uncore_discovery.h | 2 +- 4 files changed, 49 insertions(+), 47 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index e228e564b15e..cd561290be8c 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1697,133 +1697,123 @@ static int __init uncore_mmio_init(void) return ret; } =20 -struct intel_uncore_init_fun { - void (*cpu_init)(void); - int (*pci_init)(void); - void (*mmio_init)(void); - /* Discovery table is required */ - bool use_discovery; - /* The units in the discovery table should be ignored. */ - int *uncore_units_ignore; -}; - -static const struct intel_uncore_init_fun nhm_uncore_init __initconst =3D { +static const struct uncore_plat_init nhm_uncore_init __initconst =3D { .cpu_init =3D nhm_uncore_cpu_init, }; =20 -static const struct intel_uncore_init_fun snb_uncore_init __initconst =3D { +static const struct uncore_plat_init snb_uncore_init __initconst =3D { .cpu_init =3D snb_uncore_cpu_init, .pci_init =3D snb_uncore_pci_init, }; =20 -static const struct intel_uncore_init_fun ivb_uncore_init __initconst =3D { +static const struct uncore_plat_init ivb_uncore_init __initconst =3D { .cpu_init =3D snb_uncore_cpu_init, .pci_init =3D ivb_uncore_pci_init, }; =20 -static const struct intel_uncore_init_fun hsw_uncore_init __initconst =3D { +static const struct uncore_plat_init hsw_uncore_init __initconst =3D { .cpu_init =3D snb_uncore_cpu_init, .pci_init =3D hsw_uncore_pci_init, }; =20 -static const struct intel_uncore_init_fun bdw_uncore_init __initconst =3D { +static const struct uncore_plat_init bdw_uncore_init __initconst =3D { .cpu_init =3D snb_uncore_cpu_init, .pci_init =3D bdw_uncore_pci_init, }; =20 -static const struct intel_uncore_init_fun snbep_uncore_init __initconst = =3D { +static const struct uncore_plat_init snbep_uncore_init __initconst =3D { .cpu_init =3D snbep_uncore_cpu_init, .pci_init =3D snbep_uncore_pci_init, }; =20 -static const struct intel_uncore_init_fun nhmex_uncore_init __initconst = =3D { +static const struct uncore_plat_init nhmex_uncore_init __initconst =3D { .cpu_init =3D nhmex_uncore_cpu_init, }; =20 -static const struct intel_uncore_init_fun ivbep_uncore_init __initconst = =3D { +static const struct uncore_plat_init ivbep_uncore_init __initconst =3D { .cpu_init =3D ivbep_uncore_cpu_init, .pci_init =3D ivbep_uncore_pci_init, }; =20 -static const struct intel_uncore_init_fun hswep_uncore_init __initconst = =3D { +static const struct uncore_plat_init hswep_uncore_init __initconst =3D { .cpu_init =3D hswep_uncore_cpu_init, .pci_init =3D hswep_uncore_pci_init, }; =20 -static const struct intel_uncore_init_fun bdx_uncore_init __initconst =3D { +static const struct uncore_plat_init bdx_uncore_init __initconst =3D { .cpu_init =3D bdx_uncore_cpu_init, .pci_init =3D bdx_uncore_pci_init, }; =20 -static const struct intel_uncore_init_fun knl_uncore_init __initconst =3D { +static const struct uncore_plat_init knl_uncore_init __initconst =3D { .cpu_init =3D knl_uncore_cpu_init, .pci_init =3D knl_uncore_pci_init, }; =20 -static const struct intel_uncore_init_fun skl_uncore_init __initconst =3D { +static const struct uncore_plat_init skl_uncore_init __initconst =3D { .cpu_init =3D skl_uncore_cpu_init, .pci_init =3D skl_uncore_pci_init, }; =20 -static const struct intel_uncore_init_fun skx_uncore_init __initconst =3D { +static const struct uncore_plat_init skx_uncore_init __initconst =3D { .cpu_init =3D skx_uncore_cpu_init, .pci_init =3D skx_uncore_pci_init, }; =20 -static const struct intel_uncore_init_fun icl_uncore_init __initconst =3D { +static const struct uncore_plat_init icl_uncore_init __initconst =3D { .cpu_init =3D icl_uncore_cpu_init, .pci_init =3D skl_uncore_pci_init, }; =20 -static const struct intel_uncore_init_fun tgl_uncore_init __initconst =3D { +static const struct uncore_plat_init tgl_uncore_init __initconst =3D { .cpu_init =3D tgl_uncore_cpu_init, .mmio_init =3D tgl_uncore_mmio_init, }; =20 -static const struct intel_uncore_init_fun tgl_l_uncore_init __initconst = =3D { +static const struct uncore_plat_init tgl_l_uncore_init __initconst =3D { .cpu_init =3D tgl_uncore_cpu_init, .mmio_init =3D tgl_l_uncore_mmio_init, }; =20 -static const struct intel_uncore_init_fun rkl_uncore_init __initconst =3D { +static const struct uncore_plat_init rkl_uncore_init __initconst =3D { .cpu_init =3D tgl_uncore_cpu_init, .pci_init =3D skl_uncore_pci_init, }; =20 -static const struct intel_uncore_init_fun adl_uncore_init __initconst =3D { +static const struct uncore_plat_init adl_uncore_init __initconst =3D { .cpu_init =3D adl_uncore_cpu_init, .mmio_init =3D adl_uncore_mmio_init, }; =20 -static const struct intel_uncore_init_fun mtl_uncore_init __initconst =3D { +static const struct uncore_plat_init mtl_uncore_init __initconst =3D { .cpu_init =3D mtl_uncore_cpu_init, .mmio_init =3D adl_uncore_mmio_init, }; =20 -static const struct intel_uncore_init_fun lnl_uncore_init __initconst =3D { +static const struct uncore_plat_init lnl_uncore_init __initconst =3D { .cpu_init =3D lnl_uncore_cpu_init, .mmio_init =3D lnl_uncore_mmio_init, }; =20 -static const struct intel_uncore_init_fun ptl_uncore_init __initconst =3D { +static const struct uncore_plat_init ptl_uncore_init __initconst =3D { .cpu_init =3D ptl_uncore_cpu_init, .mmio_init =3D ptl_uncore_mmio_init, .use_discovery =3D true, }; =20 -static const struct intel_uncore_init_fun icx_uncore_init __initconst =3D { +static const struct uncore_plat_init icx_uncore_init __initconst =3D { .cpu_init =3D icx_uncore_cpu_init, .pci_init =3D icx_uncore_pci_init, .mmio_init =3D icx_uncore_mmio_init, }; =20 -static const struct intel_uncore_init_fun snr_uncore_init __initconst =3D { +static const struct uncore_plat_init snr_uncore_init __initconst =3D { .cpu_init =3D snr_uncore_cpu_init, .pci_init =3D snr_uncore_pci_init, .mmio_init =3D snr_uncore_mmio_init, }; =20 -static const struct intel_uncore_init_fun spr_uncore_init __initconst =3D { +static const struct uncore_plat_init spr_uncore_init __initconst =3D { .cpu_init =3D spr_uncore_cpu_init, .pci_init =3D spr_uncore_pci_init, .mmio_init =3D spr_uncore_mmio_init, @@ -1831,7 +1821,7 @@ static const struct intel_uncore_init_fun spr_uncore_= init __initconst =3D { .uncore_units_ignore =3D spr_uncore_units_ignore, }; =20 -static const struct intel_uncore_init_fun gnr_uncore_init __initconst =3D { +static const struct uncore_plat_init gnr_uncore_init __initconst =3D { .cpu_init =3D gnr_uncore_cpu_init, .pci_init =3D gnr_uncore_pci_init, .mmio_init =3D gnr_uncore_mmio_init, @@ -1839,7 +1829,7 @@ static const struct intel_uncore_init_fun gnr_uncore_= init __initconst =3D { .uncore_units_ignore =3D gnr_uncore_units_ignore, }; =20 -static const struct intel_uncore_init_fun generic_uncore_init __initconst = =3D { +static const struct uncore_plat_init generic_uncore_init __initconst =3D { .cpu_init =3D intel_uncore_generic_uncore_cpu_init, .pci_init =3D intel_uncore_generic_uncore_pci_init, .mmio_init =3D intel_uncore_generic_uncore_mmio_init, @@ -1910,7 +1900,7 @@ MODULE_DEVICE_TABLE(x86cpu, intel_uncore_match); static int __init intel_uncore_init(void) { const struct x86_cpu_id *id; - struct intel_uncore_init_fun *uncore_init; + struct uncore_plat_init *uncore_init; int pret =3D 0, cret =3D 0, mret =3D 0, ret; =20 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) @@ -1921,16 +1911,16 @@ static int __init intel_uncore_init(void) =20 id =3D x86_match_cpu(intel_uncore_match); if (!id) { - if (!uncore_no_discover && intel_uncore_has_discovery_tables(NULL)) - uncore_init =3D (struct intel_uncore_init_fun *)&generic_uncore_init; + if (!uncore_no_discover && uncore_discovery(NULL)) + uncore_init =3D (struct uncore_plat_init *)&generic_uncore_init; else return -ENODEV; } else { - uncore_init =3D (struct intel_uncore_init_fun *)id->driver_data; + uncore_init =3D (struct uncore_plat_init *)id->driver_data; if (uncore_no_discover && uncore_init->use_discovery) return -ENODEV; if (uncore_init->use_discovery && - !intel_uncore_has_discovery_tables(uncore_init->uncore_units_ignore)) + !uncore_discovery(uncore_init)) return -ENODEV; } =20 diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index d8815fff7588..568536ef28ee 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -47,6 +47,16 @@ struct uncore_event_desc; struct freerunning_counters; struct intel_uncore_topology; =20 +struct uncore_plat_init { + void (*cpu_init)(void); + int (*pci_init)(void); + void (*mmio_init)(void); + /* Discovery table is required */ + bool use_discovery; + /* The units in the discovery table should be ignored. */ + int *uncore_units_ignore; +}; + struct intel_uncore_type { const char *name; int num_counters; diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index 7d57ce706feb..d39f6a0b8cc3 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -350,7 +350,7 @@ static int parse_discovery_table(struct pci_dev *dev, i= nt die, return __parse_discovery_table(addr, die, parsed, ignore); } =20 -static bool intel_uncore_has_discovery_tables_pci(int *ignore) +static bool uncore_discovery_pci(int *ignore) { u32 device, val, entry_id, bar_offset; int die, dvsec =3D 0, ret =3D true; @@ -399,7 +399,7 @@ static bool intel_uncore_has_discovery_tables_pci(int *= ignore) return ret; } =20 -static bool intel_uncore_has_discovery_tables_msr(int *ignore) +static bool uncore_discovery_msr(int *ignore) { unsigned long *die_mask; bool parsed =3D false; @@ -432,10 +432,12 @@ static bool intel_uncore_has_discovery_tables_msr(int= *ignore) return parsed; } =20 -bool intel_uncore_has_discovery_tables(int *ignore) +bool uncore_discovery(struct uncore_plat_init *init) { - return intel_uncore_has_discovery_tables_msr(ignore) || - intel_uncore_has_discovery_tables_pci(ignore); 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a="68816608" X-IronPort-AV: E=Sophos;i="6.21,193,1763452800"; d="scan'208";a="68816608" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Dec 2025 14:49:40 -0800 X-CSE-ConnectionGUID: VazQpf8OTWau7+eASf6GnA== X-CSE-MsgGUID: fEcHY+l4RraRw4EIhWJWMA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,193,1763452800"; d="scan'208";a="232611007" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Dec 2025 14:49:39 -0800 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Xudong Hao , Falcon Thomas Subject: [PATCH V2 02/13] perf/x86/intel/uncore: Support per-platform discovery base devices Date: Wed, 31 Dec 2025 14:42:19 -0800 Message-ID: <20251231224233.113839-3-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251231224233.113839-1-zide.chen@intel.com> References: <20251231224233.113839-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On DMR platforms, IMH discovery tables are enumerated via PCI, while CBB domains use MSRs, unlike earlier platforms which relied on either PCI or MSR exclusively. DMR also uses different MSRs and PCI devices, requiring support for multiple, platform-specific discovery bases. Introduce struct uncore_discovery_domain to hold the discovery base and other domain-specific configuration. Move uncore_units_ignore into uncore_discovery_domain so a single structure can be passed to uncore_discovery_[pci/msr]. No functional change intended. Co-developed-by: Dapeng Mi Signed-off-by: Dapeng Mi Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi --- v2: - Introduce uncore_discovery_domain[] to support possible any combination of MSR or PCI discovery base. - Move has_generic_discovery_table() related code to a separate patch for easier review. - Update commit messages. arch/x86/events/intel/uncore.c | 32 ++++++++----- arch/x86/events/intel/uncore.h | 15 +++++-- arch/x86/events/intel/uncore_discovery.c | 57 +++++++++++++++--------- 3 files changed, 69 insertions(+), 35 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index cd561290be8c..844030ef87c4 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1798,7 +1798,7 @@ static const struct uncore_plat_init lnl_uncore_init = __initconst =3D { static const struct uncore_plat_init ptl_uncore_init __initconst =3D { .cpu_init =3D ptl_uncore_cpu_init, .mmio_init =3D ptl_uncore_mmio_init, - .use_discovery =3D true, + .domain[0].discovery_base =3D UNCORE_DISCOVERY_MSR, }; =20 static const struct uncore_plat_init icx_uncore_init __initconst =3D { @@ -1817,16 +1817,18 @@ static const struct uncore_plat_init spr_uncore_ini= t __initconst =3D { .cpu_init =3D spr_uncore_cpu_init, .pci_init =3D spr_uncore_pci_init, .mmio_init =3D spr_uncore_mmio_init, - .use_discovery =3D true, - .uncore_units_ignore =3D spr_uncore_units_ignore, + .domain[0].base_is_pci =3D true, + .domain[0].discovery_base =3D UNCORE_DISCOVERY_TABLE_DEVICE, + .domain[0].units_ignore =3D spr_uncore_units_ignore, }; =20 static const struct uncore_plat_init gnr_uncore_init __initconst =3D { .cpu_init =3D gnr_uncore_cpu_init, .pci_init =3D gnr_uncore_pci_init, .mmio_init =3D gnr_uncore_mmio_init, - .use_discovery =3D true, - .uncore_units_ignore =3D gnr_uncore_units_ignore, + .domain[0].base_is_pci =3D true, + .domain[0].discovery_base =3D UNCORE_DISCOVERY_TABLE_DEVICE, + .domain[0].units_ignore =3D gnr_uncore_units_ignore, }; =20 static const struct uncore_plat_init generic_uncore_init __initconst =3D { @@ -1897,6 +1899,17 @@ static const struct x86_cpu_id intel_uncore_match[] = __initconst =3D { }; MODULE_DEVICE_TABLE(x86cpu, intel_uncore_match); =20 +static bool ucore_use_discovery(struct uncore_plat_init *config) +{ + int i; + + for (i =3D 0; i < UNCORE_DISCOVERY_DOMAINS; i++) + if (config->domain[i].discovery_base) + return true; + + return false; +} + static int __init intel_uncore_init(void) { const struct x86_cpu_id *id; @@ -1911,15 +1924,14 @@ static int __init intel_uncore_init(void) =20 id =3D x86_match_cpu(intel_uncore_match); if (!id) { - if (!uncore_no_discover && uncore_discovery(NULL)) - uncore_init =3D (struct uncore_plat_init *)&generic_uncore_init; - else + uncore_init =3D (struct uncore_plat_init *)&generic_uncore_init; + if (uncore_no_discover || !uncore_discovery(uncore_init)) return -ENODEV; } else { uncore_init =3D (struct uncore_plat_init *)id->driver_data; - if (uncore_no_discover && uncore_init->use_discovery) + if (uncore_no_discover && ucore_use_discovery(uncore_init)) return -ENODEV; - if (uncore_init->use_discovery && + if (ucore_use_discovery(uncore_init) && !uncore_discovery(uncore_init)) return -ENODEV; } diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index 568536ef28ee..1574ffc7ee05 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -47,14 +47,21 @@ struct uncore_event_desc; struct freerunning_counters; struct intel_uncore_topology; =20 +struct uncore_discovery_domain { + /* MSR address or PCI device used as the discovery base */ + u32 discovery_base; + bool base_is_pci; + /* The units in the discovery table should be ignored. */ + int *units_ignore; +}; + +#define UNCORE_DISCOVERY_DOMAINS 2 struct uncore_plat_init { void (*cpu_init)(void); int (*pci_init)(void); void (*mmio_init)(void); - /* Discovery table is required */ - bool use_discovery; - /* The units in the discovery table should be ignored. */ - int *uncore_units_ignore; + + struct uncore_discovery_domain domain[UNCORE_DISCOVERY_DOMAINS]; }; =20 struct intel_uncore_type { diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index d39f6a0b8cc3..3bcbf974d3a8 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -259,23 +259,24 @@ uncore_insert_box_info(struct uncore_unit_discovery *= unit, } =20 static bool -uncore_ignore_unit(struct uncore_unit_discovery *unit, int *ignore) +uncore_ignore_unit(struct uncore_unit_discovery *unit, + struct uncore_discovery_domain *domain) { int i; =20 - if (!ignore) + if (!domain || !domain->units_ignore) return false; =20 - for (i =3D 0; ignore[i] !=3D UNCORE_IGNORE_END ; i++) { - if (unit->box_type =3D=3D ignore[i]) + for (i =3D 0; domain->units_ignore[i] !=3D UNCORE_IGNORE_END ; i++) { + if (unit->box_type =3D=3D domain->units_ignore[i]) return true; } =20 return false; } =20 -static int __parse_discovery_table(resource_size_t addr, int die, - bool *parsed, int *ignore) +static int __parse_discovery_table(struct uncore_discovery_domain *domain, + resource_size_t addr, int die, bool *parsed) { struct uncore_global_discovery global; struct uncore_unit_discovery unit; @@ -314,7 +315,7 @@ static int __parse_discovery_table(resource_size_t addr= , int die, if (unit.access_type >=3D UNCORE_ACCESS_MAX) continue; =20 - if (uncore_ignore_unit(&unit, ignore)) + if (uncore_ignore_unit(&unit, domain)) continue; =20 uncore_insert_box_info(&unit, die); @@ -325,9 +326,9 @@ static int __parse_discovery_table(resource_size_t addr= , int die, return 0; } =20 -static int parse_discovery_table(struct pci_dev *dev, int die, - u32 bar_offset, bool *parsed, - int *ignore) +static int parse_discovery_table(struct uncore_discovery_domain *domain, + struct pci_dev *dev, int die, + u32 bar_offset, bool *parsed) { resource_size_t addr; u32 val; @@ -347,17 +348,19 @@ static int parse_discovery_table(struct pci_dev *dev,= int die, } #endif =20 - return __parse_discovery_table(addr, die, parsed, ignore); + return __parse_discovery_table(domain, addr, die, parsed); } =20 -static bool uncore_discovery_pci(int *ignore) +static bool uncore_discovery_pci(struct uncore_discovery_domain *domain) { u32 device, val, entry_id, bar_offset; int die, dvsec =3D 0, ret =3D true; struct pci_dev *dev =3D NULL; bool parsed =3D false; =20 - if (has_generic_discovery_table()) + if (domain->discovery_base) + device =3D domain->discovery_base; + else if (has_generic_discovery_table()) device =3D UNCORE_DISCOVERY_TABLE_DEVICE; else device =3D PCI_ANY_ID; @@ -386,7 +389,7 @@ static bool uncore_discovery_pci(int *ignore) if (die < 0) continue; =20 - parse_discovery_table(dev, die, bar_offset, &parsed, ignore); + parse_discovery_table(domain, dev, die, bar_offset, &parsed); } } =20 @@ -399,11 +402,11 @@ static bool uncore_discovery_pci(int *ignore) return ret; } =20 -static bool uncore_discovery_msr(int *ignore) +static bool uncore_discovery_msr(struct uncore_discovery_domain *domain) { unsigned long *die_mask; bool parsed =3D false; - int cpu, die; + int cpu, die, msr; u64 base; =20 die_mask =3D kcalloc(BITS_TO_LONGS(uncore_max_dies()), @@ -411,19 +414,22 @@ static bool uncore_discovery_msr(int *ignore) if (!die_mask) return false; =20 + msr =3D domain->discovery_base ? + domain->discovery_base : UNCORE_DISCOVERY_MSR; + cpus_read_lock(); for_each_online_cpu(cpu) { die =3D topology_logical_die_id(cpu); if (__test_and_set_bit(die, die_mask)) continue; =20 - if (rdmsrq_safe_on_cpu(cpu, UNCORE_DISCOVERY_MSR, &base)) + if (rdmsrq_safe_on_cpu(cpu, msr, &base)) continue; =20 if (!base) continue; =20 - __parse_discovery_table(base, die, &parsed, ignore); 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a="68816613" X-IronPort-AV: E=Sophos;i="6.21,193,1763452800"; d="scan'208";a="68816613" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Dec 2025 14:49:40 -0800 X-CSE-ConnectionGUID: B2SNRGcJTuy7CmFrNOMjwQ== X-CSE-MsgGUID: NhxRp2JgRXSbj68C3i8LfQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,193,1763452800"; d="scan'208";a="232611010" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Dec 2025 14:49:40 -0800 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Xudong Hao , Falcon Thomas Subject: [PATCH V2 03/13] perf/x86/intel/uncore: Remove has_generic_discovery_table() Date: Wed, 31 Dec 2025 14:42:20 -0800 Message-ID: <20251231224233.113839-4-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251231224233.113839-1-zide.chen@intel.com> References: <20251231224233.113839-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the !x86_match_cpu() fallback path, has_generic_discovery_table() is removed because it does not handle multiple PCI devices. Instead, use PCI_ANY_ID in generic_uncore_init[] to probe all PCI devices. For MSR portals, only probe MSR 0x201e to keep the fallback simple, as this path is best-effort only. Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi --- V2: Separate patch from [PATCH V1 1/7] - Move has_generic_discovery_table() related code to its own patch for easier review. arch/x86/events/intel/uncore.c | 3 ++ arch/x86/events/intel/uncore_discovery.c | 42 +++++------------------- 2 files changed, 12 insertions(+), 33 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 844030ef87c4..2a1c6dce8a35 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1835,6 +1835,9 @@ static const struct uncore_plat_init generic_uncore_i= nit __initconst =3D { .cpu_init =3D intel_uncore_generic_uncore_cpu_init, .pci_init =3D intel_uncore_generic_uncore_pci_init, .mmio_init =3D intel_uncore_generic_uncore_mmio_init, + .domain[0].base_is_pci =3D true, + .domain[0].discovery_base =3D PCI_ANY_ID, + .domain[1].discovery_base =3D UNCORE_DISCOVERY_MSR, }; =20 static const struct x86_cpu_id intel_uncore_match[] __initconst =3D { diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index 3bcbf974d3a8..6f409e0b4722 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -12,24 +12,6 @@ static struct rb_root discovery_tables =3D RB_ROOT; static int num_discovered_types[UNCORE_ACCESS_MAX]; =20 -static bool has_generic_discovery_table(void) -{ - struct pci_dev *dev; - int dvsec; - - dev =3D pci_get_device(PCI_VENDOR_ID_INTEL, UNCORE_DISCOVERY_TABLE_DEVICE= , NULL); - if (!dev) - return false; - - /* A discovery table device has the unique capability ID. */ - dvsec =3D pci_find_next_ext_capability(dev, 0, UNCORE_EXT_CAP_ID_DISCOVER= Y); - pci_dev_put(dev); - if (dvsec) - return true; - - return false; -} - static int logical_die_id; =20 static int get_device_die_id(struct pci_dev *dev) @@ -358,12 +340,7 @@ static bool uncore_discovery_pci(struct uncore_discove= ry_domain *domain) struct pci_dev *dev =3D NULL; bool parsed =3D false; =20 - if (domain->discovery_base) - device =3D domain->discovery_base; - else if (has_generic_discovery_table()) - device =3D UNCORE_DISCOVERY_TABLE_DEVICE; - else - device =3D PCI_ANY_ID; + device =3D domain->discovery_base; =20 /* * Start a new search and iterates through the list of @@ -406,7 +383,7 @@ static bool uncore_discovery_msr(struct uncore_discover= y_domain *domain) { unsigned long *die_mask; bool parsed =3D false; - int cpu, die, msr; + int cpu, die; u64 base; =20 die_mask =3D kcalloc(BITS_TO_LONGS(uncore_max_dies()), @@ -414,16 +391,13 @@ static bool uncore_discovery_msr(struct uncore_discov= ery_domain *domain) if (!die_mask) return false; =20 - msr =3D domain->discovery_base ? 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DMR also introduces additional PMON units: SCA, HAMVF, D2D_ULA, UBR, PCIE4, CRS, CPC, ITC, OTC, CMS, and PCIE6. Among these, PCIE4 and PCIE6 use different unit types, but share the same config register layout, and the generic PCIe PMON events apply to both. Additionally, ignore the broken MSE unit. Signed-off-by: Zide Chen --- V2: - Add missing format_attr_umask in dmr_imc_uncore_formats_attr[]. - Separate dmr_uncore_imh_units_ignore[] from dmr_uncore_units_ignore[]. arch/x86/events/intel/uncore.c | 9 + arch/x86/events/intel/uncore.h | 3 + arch/x86/events/intel/uncore_discovery.h | 2 + arch/x86/events/intel/uncore_snbep.c | 229 +++++++++++++++++++++++ 4 files changed, 243 insertions(+) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 2a1c6dce8a35..dc2b2b272bc8 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1831,6 +1831,14 @@ static const struct uncore_plat_init gnr_uncore_init= __initconst =3D { .domain[0].units_ignore =3D gnr_uncore_units_ignore, }; =20 +static const struct uncore_plat_init dmr_uncore_init __initconst =3D { + .pci_init =3D dmr_uncore_pci_init, + .mmio_init =3D dmr_uncore_mmio_init, + .domain[0].base_is_pci =3D true, + .domain[0].discovery_base =3D DMR_UNCORE_DISCOVERY_TABLE_DEVICE, + .domain[0].units_ignore =3D dmr_uncore_imh_units_ignore, +}; + static const struct uncore_plat_init generic_uncore_init __initconst =3D { .cpu_init =3D intel_uncore_generic_uncore_cpu_init, .pci_init =3D intel_uncore_generic_uncore_pci_init, @@ -1898,6 +1906,7 @@ static const struct x86_cpu_id intel_uncore_match[] _= _initconst =3D { X86_MATCH_VFM(INTEL_ATOM_CRESTMONT_X, &gnr_uncore_init), X86_MATCH_VFM(INTEL_ATOM_CRESTMONT, &gnr_uncore_init), X86_MATCH_VFM(INTEL_ATOM_DARKMONT_X, &gnr_uncore_init), + X86_MATCH_VFM(INTEL_DIAMONDRAPIDS_X, &dmr_uncore_init), {}, }; MODULE_DEVICE_TABLE(x86cpu, intel_uncore_match); diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index 1574ffc7ee05..1e4b3a22403c 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -614,6 +614,7 @@ extern struct pci_extra_dev *uncore_extra_pci_dev; extern struct event_constraint uncore_constraint_empty; extern int spr_uncore_units_ignore[]; extern int gnr_uncore_units_ignore[]; +extern int dmr_uncore_imh_units_ignore[]; =20 /* uncore_snb.c */ int snb_uncore_pci_init(void); @@ -662,6 +663,8 @@ void spr_uncore_mmio_init(void); int gnr_uncore_pci_init(void); void gnr_uncore_cpu_init(void); void gnr_uncore_mmio_init(void); +int dmr_uncore_pci_init(void); +void dmr_uncore_mmio_init(void); =20 /* uncore_nhmex.c */ void nhmex_uncore_cpu_init(void); diff --git a/arch/x86/events/intel/uncore_discovery.h b/arch/x86/events/int= el/uncore_discovery.h index dfc237a2b6df..618788c30ac6 100644 --- a/arch/x86/events/intel/uncore_discovery.h +++ b/arch/x86/events/intel/uncore_discovery.h @@ -5,6 +5,8 @@ =20 /* Generic device ID of a discovery table device */ #define UNCORE_DISCOVERY_TABLE_DEVICE 0x09a7 +/* Device ID used on DMR */ +#define DMR_UNCORE_DISCOVERY_TABLE_DEVICE 0x09a1 /* Capability ID for a discovery table device */ #define UNCORE_EXT_CAP_ID_DISCOVERY 0x23 /* First DVSEC offset */ diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index e1f370b8d065..4b72560dc13f 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -471,6 +471,14 @@ =20 #define SPR_C0_MSR_PMON_BOX_FILTER0 0x200e =20 +/* DMR */ +#define DMR_CXLCM_EVENT_MASK_EXT 0xf +#define DMR_HAMVF_EVENT_MASK_EXT 0xffffffff +#define DMR_PCIE4_EVENT_MASK_EXT 0xffffff + +#define DMR_IMC_PMON_FIXED_CTR 0x18 +#define DMR_IMC_PMON_FIXED_CTL 0x10 + DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7"); DEFINE_UNCORE_FORMAT_ATTR(event2, event, "config:0-6"); DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21"); @@ -486,6 +494,10 @@ DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18"); DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19"); DEFINE_UNCORE_FORMAT_ATTR(tid_en2, tid_en, "config:16"); DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23"); +DEFINE_UNCORE_FORMAT_ATTR(inv2, inv, "config:21"); +DEFINE_UNCORE_FORMAT_ATTR(thresh_ext, thresh_ext, "config:32-35"); +DEFINE_UNCORE_FORMAT_ATTR(thresh10, thresh, "config:23-32"); +DEFINE_UNCORE_FORMAT_ATTR(thresh9_2, thresh, "config:23-31"); DEFINE_UNCORE_FORMAT_ATTR(thresh9, thresh, "config:24-35"); DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31"); DEFINE_UNCORE_FORMAT_ATTR(thresh6, thresh, "config:24-29"); @@ -494,6 +506,13 @@ DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14= -15"); DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30"); DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51"); DEFINE_UNCORE_FORMAT_ATTR(occ_edge_det, occ_edge_det, "config:31"); +DEFINE_UNCORE_FORMAT_ATTR(port_en, port_en, "config:32-35"); +DEFINE_UNCORE_FORMAT_ATTR(rs3_sel, rs3_sel, "config:36"); +DEFINE_UNCORE_FORMAT_ATTR(rx_sel, rx_sel, "config:37"); +DEFINE_UNCORE_FORMAT_ATTR(tx_sel, tx_sel, "config:38"); +DEFINE_UNCORE_FORMAT_ATTR(iep_sel, iep_sel, "config:39"); +DEFINE_UNCORE_FORMAT_ATTR(vc_sel, vc_sel, "config:40-47"); +DEFINE_UNCORE_FORMAT_ATTR(port_sel, port_sel, "config:48-55"); DEFINE_UNCORE_FORMAT_ATTR(ch_mask, ch_mask, "config:36-43"); DEFINE_UNCORE_FORMAT_ATTR(ch_mask2, ch_mask, "config:36-47"); DEFINE_UNCORE_FORMAT_ATTR(fc_mask, fc_mask, "config:44-46"); @@ -6709,3 +6728,213 @@ void gnr_uncore_mmio_init(void) } =20 /* end of GNR uncore support */ + +/* DMR uncore support */ +#define UNCORE_DMR_NUM_UNCORE_TYPES 52 + +static struct attribute *dmr_imc_uncore_formats_attr[] =3D { + &format_attr_event.attr, + &format_attr_umask.attr, + &format_attr_edge.attr, + &format_attr_inv.attr, + &format_attr_thresh10.attr, + NULL, +}; + +static const struct attribute_group dmr_imc_uncore_format_group =3D { + .name =3D "format", + .attrs =3D dmr_imc_uncore_formats_attr, +}; + +static struct intel_uncore_type dmr_uncore_imc =3D { + .name =3D "imc", + .fixed_ctr_bits =3D 48, + .fixed_ctr =3D DMR_IMC_PMON_FIXED_CTR, + .fixed_ctl =3D DMR_IMC_PMON_FIXED_CTL, + .ops =3D &spr_uncore_mmio_ops, + .format_group =3D &dmr_imc_uncore_format_group, + .attr_update =3D uncore_alias_groups, +}; + +static struct attribute *dmr_sca_uncore_formats_attr[] =3D { + &format_attr_event.attr, + &format_attr_umask_ext5.attr, + &format_attr_edge.attr, + &format_attr_inv.attr, + &format_attr_thresh8.attr, + NULL, +}; + +static const struct attribute_group dmr_sca_uncore_format_group =3D { + .name =3D "format", + .attrs =3D dmr_sca_uncore_formats_attr, +}; + +static struct intel_uncore_type dmr_uncore_sca =3D { + .name =3D "sca", + .event_mask_ext =3D DMR_HAMVF_EVENT_MASK_EXT, + .format_group =3D &dmr_sca_uncore_format_group, + .attr_update =3D uncore_alias_groups, +}; + +static struct attribute *dmr_cxlcm_uncore_formats_attr[] =3D { + &format_attr_event.attr, + &format_attr_umask.attr, + &format_attr_edge.attr, + &format_attr_inv2.attr, + &format_attr_thresh9_2.attr, + &format_attr_port_en.attr, + NULL, +}; + +static const struct attribute_group dmr_cxlcm_uncore_format_group =3D { + .name =3D "format", + .attrs =3D dmr_cxlcm_uncore_formats_attr, +}; + +static struct intel_uncore_type dmr_uncore_cxlcm =3D { + .name =3D "cxlcm", + .event_mask =3D GENERIC_PMON_RAW_EVENT_MASK, + .event_mask_ext =3D DMR_CXLCM_EVENT_MASK_EXT, + .format_group =3D &dmr_cxlcm_uncore_format_group, + .attr_update =3D uncore_alias_groups, +}; + +static struct intel_uncore_type dmr_uncore_hamvf =3D { + .name =3D "hamvf", + .event_mask_ext =3D DMR_HAMVF_EVENT_MASK_EXT, + .format_group =3D &dmr_sca_uncore_format_group, + .attr_update =3D uncore_alias_groups, +}; + +static struct intel_uncore_type dmr_uncore_ula =3D { + .name =3D "ula", + .event_mask_ext =3D DMR_HAMVF_EVENT_MASK_EXT, + .format_group =3D &dmr_sca_uncore_format_group, + .attr_update =3D uncore_alias_groups, +}; + +static struct intel_uncore_type dmr_uncore_ubr =3D { + .name =3D "ubr", + .event_mask_ext =3D DMR_HAMVF_EVENT_MASK_EXT, + .format_group =3D &dmr_sca_uncore_format_group, + .attr_update =3D uncore_alias_groups, +}; + +static struct attribute *dmr_pcie4_uncore_formats_attr[] =3D { + &format_attr_event.attr, + &format_attr_umask.attr, + &format_attr_edge.attr, + &format_attr_inv.attr, + &format_attr_thresh8.attr, + &format_attr_thresh_ext.attr, + &format_attr_rs3_sel.attr, + &format_attr_rx_sel.attr, + &format_attr_tx_sel.attr, + &format_attr_iep_sel.attr, + &format_attr_vc_sel.attr, + &format_attr_port_sel.attr, + NULL, +}; + +static const struct attribute_group dmr_pcie4_uncore_format_group =3D { + .name =3D "format", + .attrs =3D dmr_pcie4_uncore_formats_attr, +}; + +static struct intel_uncore_type dmr_uncore_pcie4 =3D { + .name =3D "pcie4", + .event_mask_ext =3D DMR_PCIE4_EVENT_MASK_EXT, + .format_group =3D &dmr_pcie4_uncore_format_group, + .attr_update =3D uncore_alias_groups, +}; + +static struct intel_uncore_type dmr_uncore_crs =3D { + .name =3D "crs", + .attr_update =3D uncore_alias_groups, +}; + +static struct intel_uncore_type dmr_uncore_cpc =3D { + .name =3D "cpc", + .event_mask_ext =3D DMR_HAMVF_EVENT_MASK_EXT, + .format_group =3D &dmr_sca_uncore_format_group, + .attr_update =3D uncore_alias_groups, +}; + +static struct intel_uncore_type dmr_uncore_itc =3D { + .name =3D "itc", + .event_mask_ext =3D DMR_HAMVF_EVENT_MASK_EXT, + .format_group =3D &dmr_sca_uncore_format_group, + .attr_update =3D uncore_alias_groups, +}; + +static struct intel_uncore_type dmr_uncore_otc =3D { + .name =3D "otc", + .event_mask_ext =3D DMR_HAMVF_EVENT_MASK_EXT, + .format_group =3D &dmr_sca_uncore_format_group, + .attr_update =3D uncore_alias_groups, +}; + +static struct intel_uncore_type dmr_uncore_cms =3D { + .name =3D "cms", + .attr_update =3D uncore_alias_groups, +}; + +static struct intel_uncore_type dmr_uncore_pcie6 =3D { + .name =3D "pcie6", + .event_mask_ext =3D DMR_PCIE4_EVENT_MASK_EXT, + .format_group =3D &dmr_pcie4_uncore_format_group, + .attr_update =3D uncore_alias_groups, +}; + +static struct intel_uncore_type *dmr_uncores[UNCORE_DMR_NUM_UNCORE_TYPES] = =3D { + NULL, NULL, NULL, NULL, + &spr_uncore_pcu, + &gnr_uncore_ubox, + &dmr_uncore_imc, + NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, + &dmr_uncore_sca, + &dmr_uncore_cxlcm, + NULL, NULL, NULL, + NULL, NULL, + &dmr_uncore_hamvf, + NULL, + NULL, NULL, NULL, + &dmr_uncore_ula, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, + &dmr_uncore_ubr, + NULL, + &dmr_uncore_pcie4, + &dmr_uncore_crs, + &dmr_uncore_cpc, + &dmr_uncore_itc, + &dmr_uncore_otc, + &dmr_uncore_cms, + &dmr_uncore_pcie6, +}; + +int dmr_uncore_imh_units_ignore[] =3D { + 0x13, /* MSE */ + UNCORE_IGNORE_END +}; + +int dmr_uncore_pci_init(void) +{ + uncore_pci_uncores =3D uncore_get_uncores(UNCORE_ACCESS_PCI, 0, NULL, + UNCORE_DMR_NUM_UNCORE_TYPES, + dmr_uncores); + return 0; +} +void dmr_uncore_mmio_init(void) +{ + uncore_mmio_uncores =3D uncore_get_uncores(UNCORE_ACCESS_MMIO, 0, NULL, + UNCORE_DMR_NUM_UNCORE_TYPES, + dmr_uncores); +} + +/* end of DMR uncore support */ --=20 2.52.0 From nobody Sat Feb 7 18:20:28 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E0DB30F7F3; Wed, 31 Dec 2025 22:49:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767221385; cv=none; b=Ei0suV3s7UQ59I8AJ5LHzDjBGHxs43gJTOGuZkN+T88+PUJZHLSc6XlW0FJ6fTvQA38z43gMVqg5yJ2uWkMyzsn7H6zYcLE8mUjbJAl6PWToCzD3M/pupQspWc7q8PwgTWG+hXr8r4nXx28GBJK6xvFL8Z/fllRqE0POHsKS+9E= ARC-Message-Signature: i=1; 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d="scan'208";a="232611016" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Dec 2025 14:49:40 -0800 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Xudong Hao , Falcon Thomas Subject: [PATCH V2 05/13] perf/x86/intel/uncore: Add CBB PMON support for Diamond Rapids Date: Wed, 31 Dec 2025 14:42:22 -0800 Message-ID: <20251231224233.113839-6-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251231224233.113839-1-zide.chen@intel.com> References: <20251231224233.113839-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On DMR, PMON units inside the Core Building Block (CBB) are enumerated separately from those in the Integrated Memory and I/O Hub (IMH). A new per-CBB MSR (0x710) is introduced for discovery table enumeration. For counter control registers, the tid_en bit (bit 16) exists on CBO, SBO, and Santa, but it is not used by any events. Mark this bit as reserved. Similarly, disallow extended umask (bits 32=E2=80=9363) on Santa and sNCU. Additionally, ignore broken SB2UCIE unit. Reviewed-by: Dapeng Mi Signed-off-by: Zide Chen --- V2: - Rename DMR_UNCORE_DISCOVERY_MSR to CBB_UNCORE_DISCOVERY_MSR to reflect that the MSR is not DMR-specific and allow reuse on future platforms. arch/x86/events/intel/uncore.c | 2 + arch/x86/events/intel/uncore.h | 1 + arch/x86/events/intel/uncore_discovery.h | 2 + arch/x86/events/intel/uncore_snbep.c | 52 ++++++++++++++++++++++-- 4 files changed, 54 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index dc2b2b272bc8..1565c0418fb1 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1837,6 +1837,8 @@ static const struct uncore_plat_init dmr_uncore_init = __initconst =3D { .domain[0].base_is_pci =3D true, .domain[0].discovery_base =3D DMR_UNCORE_DISCOVERY_TABLE_DEVICE, .domain[0].units_ignore =3D dmr_uncore_imh_units_ignore, + .domain[1].discovery_base =3D CBB_UNCORE_DISCOVERY_MSR, + .domain[1].units_ignore =3D dmr_uncore_cbb_units_ignore, }; =20 static const struct uncore_plat_init generic_uncore_init __initconst =3D { diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index 1e4b3a22403c..83d01a9cefc0 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -615,6 +615,7 @@ extern struct event_constraint uncore_constraint_empty; extern int spr_uncore_units_ignore[]; extern int gnr_uncore_units_ignore[]; extern int dmr_uncore_imh_units_ignore[]; +extern int dmr_uncore_cbb_units_ignore[]; =20 /* uncore_snb.c */ int snb_uncore_pci_init(void); diff --git a/arch/x86/events/intel/uncore_discovery.h b/arch/x86/events/int= el/uncore_discovery.h index 618788c30ac6..63b8f7634e42 100644 --- a/arch/x86/events/intel/uncore_discovery.h +++ b/arch/x86/events/intel/uncore_discovery.h @@ -2,6 +2,8 @@ =20 /* Store the full address of the global discovery table */ #define UNCORE_DISCOVERY_MSR 0x201e +/* Base address of uncore perfmon discovery table for CBB domain */ +#define CBB_UNCORE_DISCOVERY_MSR 0x710 =20 /* Generic device ID of a discovery table device */ #define UNCORE_DISCOVERY_TABLE_DEVICE 0x09a7 diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index 4b72560dc13f..df173534637a 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -6807,6 +6807,28 @@ static struct intel_uncore_type dmr_uncore_hamvf =3D= { .attr_update =3D uncore_alias_groups, }; =20 +static struct intel_uncore_type dmr_uncore_cbo =3D { + .name =3D "cbo", + .event_mask_ext =3D DMR_HAMVF_EVENT_MASK_EXT, + .format_group =3D &dmr_sca_uncore_format_group, + .attr_update =3D uncore_alias_groups, +}; + +static struct intel_uncore_type dmr_uncore_santa =3D { + .name =3D "santa", + .attr_update =3D uncore_alias_groups, +}; + +static struct intel_uncore_type dmr_uncore_cncu =3D { + .name =3D "cncu", + .attr_update =3D uncore_alias_groups, +}; + +static struct intel_uncore_type dmr_uncore_sncu =3D { + .name =3D "sncu", + .attr_update =3D uncore_alias_groups, +}; + static struct intel_uncore_type dmr_uncore_ula =3D { .name =3D "ula", .event_mask_ext =3D DMR_HAMVF_EVENT_MASK_EXT, @@ -6814,6 +6836,20 @@ static struct intel_uncore_type dmr_uncore_ula =3D { .attr_update =3D uncore_alias_groups, }; =20 +static struct intel_uncore_type dmr_uncore_dda =3D { + .name =3D "dda", + .event_mask_ext =3D DMR_HAMVF_EVENT_MASK_EXT, + .format_group =3D &dmr_sca_uncore_format_group, + .attr_update =3D uncore_alias_groups, +}; + +static struct intel_uncore_type dmr_uncore_sbo =3D { + .name =3D "sbo", + .event_mask_ext =3D DMR_HAMVF_EVENT_MASK_EXT, + .format_group =3D &dmr_sca_uncore_format_group, + .attr_update =3D uncore_alias_groups, +}; + static struct intel_uncore_type dmr_uncore_ubr =3D { .name =3D "ubr", .event_mask_ext =3D DMR_HAMVF_EVENT_MASK_EXT, @@ -6902,10 +6938,15 @@ static struct intel_uncore_type *dmr_uncores[UNCORE= _DMR_NUM_UNCORE_TYPES] =3D { NULL, NULL, NULL, NULL, NULL, &dmr_uncore_hamvf, - NULL, - NULL, NULL, NULL, + &dmr_uncore_cbo, + &dmr_uncore_santa, + &dmr_uncore_cncu, + &dmr_uncore_sncu, &dmr_uncore_ula, - NULL, NULL, NULL, NULL, + &dmr_uncore_dda, + NULL, + &dmr_uncore_sbo, + NULL, NULL, NULL, NULL, &dmr_uncore_ubr, NULL, @@ -6923,6 +6964,11 @@ int dmr_uncore_imh_units_ignore[] =3D { UNCORE_IGNORE_END }; =20 +int dmr_uncore_cbb_units_ignore[] =3D { + 0x25, /* SB2UCIE */ + UNCORE_IGNORE_END +}; + int dmr_uncore_pci_init(void) { uncore_pci_uncores =3D uncore_get_uncores(UNCORE_ACCESS_PCI, 0, NULL, --=20 2.52.0 From nobody Sat Feb 7 18:20:28 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A827030F80C; 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a="68816629" X-IronPort-AV: E=Sophos;i="6.21,193,1763452800"; d="scan'208";a="68816629" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Dec 2025 14:49:41 -0800 X-CSE-ConnectionGUID: KvW9KyX2RRylRnmqhJ/lQg== X-CSE-MsgGUID: gZVMNUD+SmiYe/cIt+HZ/w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,193,1763452800"; d="scan'208";a="232611019" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Dec 2025 14:49:41 -0800 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Xudong Hao , Falcon Thomas Subject: [PATCH V2 06/13] perf/x86/intel/uncore: Add domain global init callback Date: Wed, 31 Dec 2025 14:42:23 -0800 Message-ID: <20251231224233.113839-7-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251231224233.113839-1-zide.chen@intel.com> References: <20251231224233.113839-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the Intel uncore self-describing mechanism, the Global Control Register freeze_all bit is SoC-wide and propagates to all uncore PMUs. On Diamond Rapids, this bit is set at power-on, unlike some prior platforms. Add a global_init callback to unfreeze all PMON units. Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi --- V2: New patch arch/x86/events/intel/uncore.c | 16 ++++++++++++++++ arch/x86/events/intel/uncore.h | 2 ++ arch/x86/events/intel/uncore_discovery.c | 3 +++ 3 files changed, 21 insertions(+) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 1565c0418fb1..080b6870a88d 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1697,6 +1697,21 @@ static int __init uncore_mmio_init(void) return ret; } =20 +static int uncore_mmio_global_init(u64 ctl) +{ + void __iomem *io_addr; + + io_addr =3D ioremap(ctl, sizeof(ctl)); + if (!io_addr) + return -ENOMEM; + + /* Clear bit 0, all other bits are reserved */ + writel(0, io_addr); + + iounmap(io_addr); + return 0; +} + static const struct uncore_plat_init nhm_uncore_init __initconst =3D { .cpu_init =3D nhm_uncore_cpu_init, }; @@ -1839,6 +1854,7 @@ static const struct uncore_plat_init dmr_uncore_init = __initconst =3D { .domain[0].units_ignore =3D dmr_uncore_imh_units_ignore, .domain[1].discovery_base =3D CBB_UNCORE_DISCOVERY_MSR, .domain[1].units_ignore =3D dmr_uncore_cbb_units_ignore, + .domain[1].global_init =3D uncore_mmio_global_init, }; =20 static const struct uncore_plat_init generic_uncore_init __initconst =3D { diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index 83d01a9cefc0..55e3aebf4b5e 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -51,6 +51,8 @@ struct uncore_discovery_domain { /* MSR address or PCI device used as the discovery base */ u32 discovery_base; bool base_is_pci; + int (*global_init)(u64 ctl); + /* The units in the discovery table should be ignored. */ int *units_ignore; }; diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index 6f409e0b4722..3a5a3876b74c 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -286,6 +286,9 @@ static int __parse_discovery_table(struct uncore_discov= ery_domain *domain, if (!io_addr) return -ENOMEM; =20 + if (domain->global_init && domain->global_init(global.ctl)) + return -ENODEV; + /* Parsing Unit Discovery State */ for (i =3D 0; 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31 Dec 2025 14:49:41 -0800 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Xudong Hao , Falcon Thomas Subject: [PATCH V2 07/13] perf/x86/intel/uncore: Add freerunning event descriptor helper macro Date: Wed, 31 Dec 2025 14:42:24 -0800 Message-ID: <20251231224233.113839-8-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251231224233.113839-1-zide.chen@intel.com> References: <20251231224233.113839-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Freerunning counter events are repetitive: the event code is fixed to 0xff, the unit is always "MiB", and the scale is identical across all counters on a given PMON unit. Introduce a new helper macro, INTEL_UNCORE_FR_EVENT_DESC(), to populate the event, scale, and unit descriptor triplet. This reduces duplicated lines and improves readability. No functional change intended. Reviewed-by: Dapeng Mi Signed-off-by: Zide Chen --- arch/x86/events/intel/uncore_snbep.c | 95 ++++++++-------------------- 1 file changed, 28 insertions(+), 67 deletions(-) diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index df173534637a..09a3bdbd188a 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -4068,34 +4068,24 @@ static struct freerunning_counters skx_iio_freerunn= ing[] =3D { [SKX_IIO_MSR_UTIL] =3D { 0xb08, 0x1, 0x10, 8, 36 }, }; =20 +#define INTEL_UNCORE_FR_EVENT_DESC(name, umask, scl) \ + INTEL_UNCORE_EVENT_DESC(name, \ + "event=3D0xff,umask=3D" __stringify(umask)), \ + INTEL_UNCORE_EVENT_DESC(name.scale, __stringify(scl)), \ + INTEL_UNCORE_EVENT_DESC(name.unit, "MiB") + static struct uncore_event_desc skx_uncore_iio_freerunning_events[] =3D { /* Free-Running IO CLOCKS Counter */ INTEL_UNCORE_EVENT_DESC(ioclk, "event=3D0xff,umask=3D0x10"), /* Free-Running IIO BANDWIDTH Counters */ - INTEL_UNCORE_EVENT_DESC(bw_in_port0, "event=3D0xff,umask=3D0x20"), - INTEL_UNCORE_EVENT_DESC(bw_in_port0.scale, "3.814697266e-6"), - INTEL_UNCORE_EVENT_DESC(bw_in_port0.unit, "MiB"), - INTEL_UNCORE_EVENT_DESC(bw_in_port1, "event=3D0xff,umask=3D0x21"), - INTEL_UNCORE_EVENT_DESC(bw_in_port1.scale, "3.814697266e-6"), - INTEL_UNCORE_EVENT_DESC(bw_in_port1.unit, "MiB"), - INTEL_UNCORE_EVENT_DESC(bw_in_port2, "event=3D0xff,umask=3D0x22"), - INTEL_UNCORE_EVENT_DESC(bw_in_port2.scale, "3.814697266e-6"), - INTEL_UNCORE_EVENT_DESC(bw_in_port2.unit, "MiB"), - INTEL_UNCORE_EVENT_DESC(bw_in_port3, "event=3D0xff,umask=3D0x23"), - INTEL_UNCORE_EVENT_DESC(bw_in_port3.scale, "3.814697266e-6"), - INTEL_UNCORE_EVENT_DESC(bw_in_port3.unit, "MiB"), - INTEL_UNCORE_EVENT_DESC(bw_out_port0, "event=3D0xff,umask=3D0x24"), - INTEL_UNCORE_EVENT_DESC(bw_out_port0.scale, "3.814697266e-6"), - INTEL_UNCORE_EVENT_DESC(bw_out_port0.unit, "MiB"), - INTEL_UNCORE_EVENT_DESC(bw_out_port1, "event=3D0xff,umask=3D0x25"), - INTEL_UNCORE_EVENT_DESC(bw_out_port1.scale, "3.814697266e-6"), - INTEL_UNCORE_EVENT_DESC(bw_out_port1.unit, "MiB"), - INTEL_UNCORE_EVENT_DESC(bw_out_port2, "event=3D0xff,umask=3D0x26"), - INTEL_UNCORE_EVENT_DESC(bw_out_port2.scale, "3.814697266e-6"), - INTEL_UNCORE_EVENT_DESC(bw_out_port2.unit, "MiB"), - INTEL_UNCORE_EVENT_DESC(bw_out_port3, "event=3D0xff,umask=3D0x27"), - INTEL_UNCORE_EVENT_DESC(bw_out_port3.scale, "3.814697266e-6"), - INTEL_UNCORE_EVENT_DESC(bw_out_port3.unit, "MiB"), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port0, 0x20, 3.814697266e-6), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port1, 0x21, 3.814697266e-6), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port2, 0x22, 3.814697266e-6), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port3, 0x23, 3.814697266e-6), + INTEL_UNCORE_FR_EVENT_DESC(bw_out_port0, 0x24, 3.814697266e-6), + INTEL_UNCORE_FR_EVENT_DESC(bw_out_port1, 0x25, 3.814697266e-6), + INTEL_UNCORE_FR_EVENT_DESC(bw_out_port2, 0x26, 3.814697266e-6), + INTEL_UNCORE_FR_EVENT_DESC(bw_out_port3, 0x27, 3.814697266e-6), /* Free-running IIO UTILIZATION Counters */ INTEL_UNCORE_EVENT_DESC(util_in_port0, "event=3D0xff,umask=3D0x30"), INTEL_UNCORE_EVENT_DESC(util_out_port0, "event=3D0xff,umask=3D0x31"), @@ -4910,30 +4900,14 @@ static struct uncore_event_desc snr_uncore_iio_free= running_events[] =3D { /* Free-Running IIO CLOCKS Counter */ INTEL_UNCORE_EVENT_DESC(ioclk, "event=3D0xff,umask=3D0x10"), /* Free-Running IIO BANDWIDTH IN Counters */ - INTEL_UNCORE_EVENT_DESC(bw_in_port0, "event=3D0xff,umask=3D0x20"), - INTEL_UNCORE_EVENT_DESC(bw_in_port0.scale, "3.0517578125e-5"), - INTEL_UNCORE_EVENT_DESC(bw_in_port0.unit, "MiB"), - INTEL_UNCORE_EVENT_DESC(bw_in_port1, "event=3D0xff,umask=3D0x21"), - INTEL_UNCORE_EVENT_DESC(bw_in_port1.scale, "3.0517578125e-5"), - INTEL_UNCORE_EVENT_DESC(bw_in_port1.unit, "MiB"), - INTEL_UNCORE_EVENT_DESC(bw_in_port2, "event=3D0xff,umask=3D0x22"), - INTEL_UNCORE_EVENT_DESC(bw_in_port2.scale, "3.0517578125e-5"), - INTEL_UNCORE_EVENT_DESC(bw_in_port2.unit, "MiB"), - INTEL_UNCORE_EVENT_DESC(bw_in_port3, "event=3D0xff,umask=3D0x23"), - INTEL_UNCORE_EVENT_DESC(bw_in_port3.scale, "3.0517578125e-5"), - INTEL_UNCORE_EVENT_DESC(bw_in_port3.unit, "MiB"), - INTEL_UNCORE_EVENT_DESC(bw_in_port4, "event=3D0xff,umask=3D0x24"), - INTEL_UNCORE_EVENT_DESC(bw_in_port4.scale, "3.0517578125e-5"), - INTEL_UNCORE_EVENT_DESC(bw_in_port4.unit, "MiB"), - INTEL_UNCORE_EVENT_DESC(bw_in_port5, "event=3D0xff,umask=3D0x25"), - INTEL_UNCORE_EVENT_DESC(bw_in_port5.scale, "3.0517578125e-5"), - INTEL_UNCORE_EVENT_DESC(bw_in_port5.unit, "MiB"), - INTEL_UNCORE_EVENT_DESC(bw_in_port6, "event=3D0xff,umask=3D0x26"), - INTEL_UNCORE_EVENT_DESC(bw_in_port6.scale, "3.0517578125e-5"), - INTEL_UNCORE_EVENT_DESC(bw_in_port6.unit, "MiB"), - INTEL_UNCORE_EVENT_DESC(bw_in_port7, "event=3D0xff,umask=3D0x27"), - INTEL_UNCORE_EVENT_DESC(bw_in_port7.scale, "3.0517578125e-5"), - INTEL_UNCORE_EVENT_DESC(bw_in_port7.unit, "MiB"), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port0, 0x20, 3.0517578125e-5), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port1, 0x21, 3.0517578125e-5), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port2, 0x22, 3.0517578125e-5), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port3, 0x23, 3.0517578125e-5), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port4, 0x24, 3.0517578125e-5), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port5, 0x25, 3.0517578125e-5), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port6, 0x26, 3.0517578125e-5), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port7, 0x27, 3.0517578125e-5), { /* end: all zeroes */ }, }; =20 @@ -5266,12 +5240,8 @@ static struct freerunning_counters snr_imc_freerunni= ng[] =3D { static struct uncore_event_desc snr_uncore_imc_freerunning_events[] =3D { INTEL_UNCORE_EVENT_DESC(dclk, "event=3D0xff,umask=3D0x10"), =20 - INTEL_UNCORE_EVENT_DESC(read, "event=3D0xff,umask=3D0x20"), - INTEL_UNCORE_EVENT_DESC(read.scale, "6.103515625e-5"), - INTEL_UNCORE_EVENT_DESC(read.unit, "MiB"), - INTEL_UNCORE_EVENT_DESC(write, "event=3D0xff,umask=3D0x21"), - INTEL_UNCORE_EVENT_DESC(write.scale, "6.103515625e-5"), - INTEL_UNCORE_EVENT_DESC(write.unit, "MiB"), + INTEL_UNCORE_FR_EVENT_DESC(read, 0x20, 6.103515625e-5), + INTEL_UNCORE_FR_EVENT_DESC(write, 0x21, 6.103515625e-5), { /* end: all zeroes */ }, }; =20 @@ -5836,19 +5806,10 @@ static struct freerunning_counters icx_imc_freerunn= ing[] =3D { static struct uncore_event_desc icx_uncore_imc_freerunning_events[] =3D { INTEL_UNCORE_EVENT_DESC(dclk, "event=3D0xff,umask=3D0x10"), =20 - INTEL_UNCORE_EVENT_DESC(read, "event=3D0xff,umask=3D0x20"), - INTEL_UNCORE_EVENT_DESC(read.scale, "6.103515625e-5"), - INTEL_UNCORE_EVENT_DESC(read.unit, "MiB"), - INTEL_UNCORE_EVENT_DESC(write, "event=3D0xff,umask=3D0x21"), - INTEL_UNCORE_EVENT_DESC(write.scale, "6.103515625e-5"), - INTEL_UNCORE_EVENT_DESC(write.unit, "MiB"), - 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The counters are MMIO based. - Only a subset of IP blocks implement free-running counters: HIOP0 (IP Base Addr: 2E7000h) HIOP1 (IP Base Addr: 2EF000h) HIOP3 (IP Base Addr: 2FF000h) HIOP4 (IP Base Addr: 307000h) - IMH2 (Secondary IMH) does not provide free-running counters. Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi --- V2: - Remove pr_warn() from dmr_uncore_freerunning_init_box(). arch/x86/events/intel/uncore_snbep.c | 118 +++++++++++++++++++++++++-- 1 file changed, 113 insertions(+), 5 deletions(-) diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index 09a3bdbd188a..28bcccf5cdfe 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -472,10 +472,14 @@ #define SPR_C0_MSR_PMON_BOX_FILTER0 0x200e =20 /* DMR */ +#define DMR_IMH1_HIOP_MMIO_BASE 0x1ffff6ae7000 +#define DMR_HIOP_MMIO_SIZE 0x8000 #define DMR_CXLCM_EVENT_MASK_EXT 0xf #define DMR_HAMVF_EVENT_MASK_EXT 0xffffffff #define DMR_PCIE4_EVENT_MASK_EXT 0xffffff =20 +#define UNCORE_DMR_ITC 0x30 + #define DMR_IMC_PMON_FIXED_CTR 0x18 #define DMR_IMC_PMON_FIXED_CTL 0x10 =20 @@ -6442,7 +6446,11 @@ static int uncore_type_max_boxes(struct intel_uncore= _type **types, for (node =3D rb_first(type->boxes); node; node =3D rb_next(node)) { unit =3D rb_entry(node, struct intel_uncore_discovery_unit, node); =20 - if (unit->id > max) + /* + * on DMR IMH2, the unit id starts from 0x8000, + * and we don't need to count it. + */ + if ((unit->id > max) && (unit->id < 0x8000)) max =3D unit->id; } return max + 1; @@ -6930,6 +6938,101 @@ int dmr_uncore_cbb_units_ignore[] =3D { UNCORE_IGNORE_END }; =20 +static unsigned int dmr_iio_freerunning_box_offsets[] =3D { + 0x0, 0x8000, 0x18000, 0x20000 +}; + +static void dmr_uncore_freerunning_init_box(struct intel_uncore_box *box) +{ + struct intel_uncore_type *type =3D box->pmu->type; + u64 mmio_base; + + if (box->pmu->pmu_idx >=3D type->num_boxes) + return; + + mmio_base =3D DMR_IMH1_HIOP_MMIO_BASE; + mmio_base +=3D dmr_iio_freerunning_box_offsets[box->pmu->pmu_idx]; + + box->io_addr =3D ioremap(mmio_base, type->mmio_map_size); + if (!box->io_addr) + pr_warn("perf uncore: Failed to ioremap for %s.\n", type->name); +} + +static struct intel_uncore_ops dmr_uncore_freerunning_ops =3D { + .init_box =3D dmr_uncore_freerunning_init_box, + .exit_box =3D uncore_mmio_exit_box, + .read_counter =3D uncore_mmio_read_counter, + .hw_config =3D uncore_freerunning_hw_config, +}; + +enum perf_uncore_dmr_iio_freerunning_type_id { + DMR_ITC_INB_DATA_BW, + DMR_ITC_BW_IN, + DMR_OTC_BW_OUT, + DMR_OTC_CLOCK_TICKS, + + DMR_IIO_FREERUNNING_TYPE_MAX, +}; + +static struct freerunning_counters dmr_iio_freerunning[] =3D { + [DMR_ITC_INB_DATA_BW] =3D { 0x4d40, 0x8, 0, 8, 48}, + [DMR_ITC_BW_IN] =3D { 0x6b00, 0x8, 0, 8, 48}, + [DMR_OTC_BW_OUT] =3D { 0x6b60, 0x8, 0, 8, 48}, + [DMR_OTC_CLOCK_TICKS] =3D { 0x6bb0, 0x8, 0, 1, 48}, +}; + +static struct uncore_event_desc dmr_uncore_iio_freerunning_events[] =3D { + /* ITC Free Running Data BW counter for inbound traffic */ + INTEL_UNCORE_FR_EVENT_DESC(inb_data_port0, 0x10, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(inb_data_port1, 0x11, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(inb_data_port2, 0x12, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(inb_data_port3, 0x13, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(inb_data_port4, 0x14, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(inb_data_port5, 0x15, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(inb_data_port6, 0x16, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(inb_data_port7, 0x17, "3.814697266e-6"), + + /* ITC Free Running BW IN counters */ + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port0, 0x20, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port1, 0x21, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port2, 0x22, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port3, 0x23, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port4, 0x24, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port5, 0x25, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port6, 0x26, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_in_port7, 0x27, "3.814697266e-6"), + + /* ITC Free Running BW OUT counters */ + INTEL_UNCORE_FR_EVENT_DESC(bw_out_port0, 0x30, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_out_port1, 0x31, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_out_port2, 0x32, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_out_port3, 0x33, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_out_port4, 0x34, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_out_port5, 0x35, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_out_port6, 0x36, "3.814697266e-6"), + INTEL_UNCORE_FR_EVENT_DESC(bw_out_port7, 0x37, "3.814697266e-6"), + + /* Free Running Clock Counter */ + INTEL_UNCORE_EVENT_DESC(clockticks, "event=3D0xff,umask=3D0x40"), + { /* end: all zeroes */ }, +}; + +static struct intel_uncore_type dmr_uncore_iio_free_running =3D { + .name =3D "iio_free_running", + .num_counters =3D 25, + .mmio_map_size =3D DMR_HIOP_MMIO_SIZE, + .num_freerunning_types =3D DMR_IIO_FREERUNNING_TYPE_MAX, + .freerunning =3D dmr_iio_freerunning, + .ops =3D &dmr_uncore_freerunning_ops, + .event_descs =3D dmr_uncore_iio_freerunning_events, + .format_group =3D &skx_uncore_iio_freerunning_format_group, +}; + +#define UNCORE_DMR_MMIO_EXTRA_UNCORES 1 +static struct intel_uncore_type *dmr_mmio_uncores[UNCORE_DMR_MMIO_EXTRA_UN= CORES] =3D { + &dmr_uncore_iio_free_running, +}; + int dmr_uncore_pci_init(void) { uncore_pci_uncores =3D uncore_get_uncores(UNCORE_ACCESS_PCI, 0, NULL, @@ -6937,11 +7040,16 @@ int dmr_uncore_pci_init(void) dmr_uncores); return 0; } + void dmr_uncore_mmio_init(void) { - uncore_mmio_uncores =3D uncore_get_uncores(UNCORE_ACCESS_MMIO, 0, NULL, - UNCORE_DMR_NUM_UNCORE_TYPES, - dmr_uncores); -} + uncore_mmio_uncores =3D uncore_get_uncores(UNCORE_ACCESS_MMIO, + UNCORE_DMR_MMIO_EXTRA_UNCORES, + dmr_mmio_uncores, + UNCORE_DMR_NUM_UNCORE_TYPES, + dmr_uncores); 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31 Dec 2025 14:49:41 -0800 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Xudong Hao , Falcon Thomas Subject: [PATCH V2 09/13] perf/x86/intel/uncore: Support uncore constraint ranges Date: Wed, 31 Dec 2025 14:42:26 -0800 Message-ID: <20251231224233.113839-10-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251231224233.113839-1-zide.chen@intel.com> References: <20251231224233.113839-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add UNCORE_EVENT_CONSTRAINT_RANGE macro for uncore constraints, similar to INTEL_EVENT_CONSTRAINT_RANGE, to reduce duplication when defining consecutive uncore event constraints. No functional change intended. Suggested-by: Dapeng Mi Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi --- V2: new patch arch/x86/events/intel/uncore.c | 2 +- arch/x86/events/intel/uncore.h | 2 + arch/x86/events/intel/uncore_snbep.c | 183 ++++++--------------------- 3 files changed, 44 insertions(+), 143 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 080b6870a88d..54b3c1e3af32 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -436,7 +436,7 @@ uncore_get_event_constraint(struct intel_uncore_box *bo= x, struct perf_event *eve =20 if (type->constraints) { for_each_event_constraint(c, type->constraints) { - if ((event->hw.config & c->cmask) =3D=3D c->code) + if (constraint_match(c, event->hw.config)) return c; } } diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index 55e3aebf4b5e..564cb26c4468 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -33,6 +33,8 @@ #define UNCORE_EXTRA_PCI_DEV_MAX 4 =20 #define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff) +#define UNCORE_EVENT_CONSTRAINT_RANGE(c, e, n) \ + EVENT_CONSTRAINT_RANGE(c, e, n, 0xff) =20 #define UNCORE_IGNORE_END -1 =20 diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index 28bcccf5cdfe..fac2be780276 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -836,76 +836,37 @@ static struct intel_uncore_ops snbep_uncore_pci_ops = =3D { static struct event_constraint snbep_uncore_cbox_constraints[] =3D { UNCORE_EVENT_CONSTRAINT(0x01, 0x1), UNCORE_EVENT_CONSTRAINT(0x02, 0x3), - UNCORE_EVENT_CONSTRAINT(0x04, 0x3), - UNCORE_EVENT_CONSTRAINT(0x05, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x04, 0x5, 0x3), UNCORE_EVENT_CONSTRAINT(0x07, 0x3), UNCORE_EVENT_CONSTRAINT(0x09, 0x3), UNCORE_EVENT_CONSTRAINT(0x11, 0x1), - UNCORE_EVENT_CONSTRAINT(0x12, 0x3), - UNCORE_EVENT_CONSTRAINT(0x13, 0x3), - UNCORE_EVENT_CONSTRAINT(0x1b, 0xc), - UNCORE_EVENT_CONSTRAINT(0x1c, 0xc), - UNCORE_EVENT_CONSTRAINT(0x1d, 0xc), - UNCORE_EVENT_CONSTRAINT(0x1e, 0xc), + UNCORE_EVENT_CONSTRAINT_RANGE(0x12, 0x13, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x1b, 0x1e, 0xc), UNCORE_EVENT_CONSTRAINT(0x1f, 0xe), UNCORE_EVENT_CONSTRAINT(0x21, 0x3), UNCORE_EVENT_CONSTRAINT(0x23, 0x3), - UNCORE_EVENT_CONSTRAINT(0x31, 0x3), - UNCORE_EVENT_CONSTRAINT(0x32, 0x3), - UNCORE_EVENT_CONSTRAINT(0x33, 0x3), - UNCORE_EVENT_CONSTRAINT(0x34, 0x3), - UNCORE_EVENT_CONSTRAINT(0x35, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x31, 0x35, 0x3), UNCORE_EVENT_CONSTRAINT(0x36, 0x1), - UNCORE_EVENT_CONSTRAINT(0x37, 0x3), - UNCORE_EVENT_CONSTRAINT(0x38, 0x3), - UNCORE_EVENT_CONSTRAINT(0x39, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x37, 0x39, 0x3), UNCORE_EVENT_CONSTRAINT(0x3b, 0x1), EVENT_CONSTRAINT_END }; =20 static struct event_constraint snbep_uncore_r2pcie_constraints[] =3D { - UNCORE_EVENT_CONSTRAINT(0x10, 0x3), - UNCORE_EVENT_CONSTRAINT(0x11, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x10, 0x11, 0x3), UNCORE_EVENT_CONSTRAINT(0x12, 0x1), UNCORE_EVENT_CONSTRAINT(0x23, 0x3), - UNCORE_EVENT_CONSTRAINT(0x24, 0x3), - UNCORE_EVENT_CONSTRAINT(0x25, 0x3), - UNCORE_EVENT_CONSTRAINT(0x26, 0x3), - UNCORE_EVENT_CONSTRAINT(0x32, 0x3), - UNCORE_EVENT_CONSTRAINT(0x33, 0x3), - UNCORE_EVENT_CONSTRAINT(0x34, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x24, 0x26, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x32, 0x34, 0x3), EVENT_CONSTRAINT_END }; =20 static struct event_constraint snbep_uncore_r3qpi_constraints[] =3D { - UNCORE_EVENT_CONSTRAINT(0x10, 0x3), - UNCORE_EVENT_CONSTRAINT(0x11, 0x3), - UNCORE_EVENT_CONSTRAINT(0x12, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x10, 0x12, 0x3), UNCORE_EVENT_CONSTRAINT(0x13, 0x1), - UNCORE_EVENT_CONSTRAINT(0x20, 0x3), - UNCORE_EVENT_CONSTRAINT(0x21, 0x3), - UNCORE_EVENT_CONSTRAINT(0x22, 0x3), - UNCORE_EVENT_CONSTRAINT(0x23, 0x3), - UNCORE_EVENT_CONSTRAINT(0x24, 0x3), - UNCORE_EVENT_CONSTRAINT(0x25, 0x3), - UNCORE_EVENT_CONSTRAINT(0x26, 0x3), - UNCORE_EVENT_CONSTRAINT(0x28, 0x3), - UNCORE_EVENT_CONSTRAINT(0x29, 0x3), - UNCORE_EVENT_CONSTRAINT(0x2a, 0x3), - UNCORE_EVENT_CONSTRAINT(0x2b, 0x3), - UNCORE_EVENT_CONSTRAINT(0x2c, 0x3), - UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), - UNCORE_EVENT_CONSTRAINT(0x2e, 0x3), - UNCORE_EVENT_CONSTRAINT(0x2f, 0x3), - UNCORE_EVENT_CONSTRAINT(0x30, 0x3), - UNCORE_EVENT_CONSTRAINT(0x31, 0x3), - UNCORE_EVENT_CONSTRAINT(0x32, 0x3), - UNCORE_EVENT_CONSTRAINT(0x33, 0x3), - UNCORE_EVENT_CONSTRAINT(0x34, 0x3), - UNCORE_EVENT_CONSTRAINT(0x36, 0x3), - UNCORE_EVENT_CONSTRAINT(0x37, 0x3), - UNCORE_EVENT_CONSTRAINT(0x38, 0x3), - UNCORE_EVENT_CONSTRAINT(0x39, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x20, 0x26, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x28, 0x34, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x36, 0x39, 0x3), EVENT_CONSTRAINT_END }; =20 @@ -3034,24 +2995,15 @@ static struct intel_uncore_type hswep_uncore_qpi = =3D { }; =20 static struct event_constraint hswep_uncore_r2pcie_constraints[] =3D { - UNCORE_EVENT_CONSTRAINT(0x10, 0x3), - UNCORE_EVENT_CONSTRAINT(0x11, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x10, 0x11, 0x3), UNCORE_EVENT_CONSTRAINT(0x13, 0x1), - UNCORE_EVENT_CONSTRAINT(0x23, 0x1), - UNCORE_EVENT_CONSTRAINT(0x24, 0x1), - UNCORE_EVENT_CONSTRAINT(0x25, 0x1), + UNCORE_EVENT_CONSTRAINT_RANGE(0x23, 0x25, 0x1), UNCORE_EVENT_CONSTRAINT(0x26, 0x3), UNCORE_EVENT_CONSTRAINT(0x27, 0x1), - UNCORE_EVENT_CONSTRAINT(0x28, 0x3), - UNCORE_EVENT_CONSTRAINT(0x29, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x28, 0x29, 0x3), UNCORE_EVENT_CONSTRAINT(0x2a, 0x1), - UNCORE_EVENT_CONSTRAINT(0x2b, 0x3), - UNCORE_EVENT_CONSTRAINT(0x2c, 0x3), - UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), - UNCORE_EVENT_CONSTRAINT(0x32, 0x3), - UNCORE_EVENT_CONSTRAINT(0x33, 0x3), - UNCORE_EVENT_CONSTRAINT(0x34, 0x3), - UNCORE_EVENT_CONSTRAINT(0x35, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x2b, 0x2d, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x32, 0x35, 0x3), EVENT_CONSTRAINT_END }; =20 @@ -3066,38 +3018,17 @@ static struct intel_uncore_type hswep_uncore_r2pcie= =3D { =20 static struct event_constraint hswep_uncore_r3qpi_constraints[] =3D { UNCORE_EVENT_CONSTRAINT(0x01, 0x3), - UNCORE_EVENT_CONSTRAINT(0x07, 0x7), - UNCORE_EVENT_CONSTRAINT(0x08, 0x7), - UNCORE_EVENT_CONSTRAINT(0x09, 0x7), - UNCORE_EVENT_CONSTRAINT(0x0a, 0x7), + UNCORE_EVENT_CONSTRAINT_RANGE(0x7, 0x0a, 0x7), UNCORE_EVENT_CONSTRAINT(0x0e, 0x7), - UNCORE_EVENT_CONSTRAINT(0x10, 0x3), - UNCORE_EVENT_CONSTRAINT(0x11, 0x3), - UNCORE_EVENT_CONSTRAINT(0x12, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x10, 0x12, 0x3), UNCORE_EVENT_CONSTRAINT(0x13, 0x1), - UNCORE_EVENT_CONSTRAINT(0x14, 0x3), - UNCORE_EVENT_CONSTRAINT(0x15, 0x3), - UNCORE_EVENT_CONSTRAINT(0x1f, 0x3), - UNCORE_EVENT_CONSTRAINT(0x20, 0x3), - UNCORE_EVENT_CONSTRAINT(0x21, 0x3), - UNCORE_EVENT_CONSTRAINT(0x22, 0x3), - UNCORE_EVENT_CONSTRAINT(0x23, 0x3), - UNCORE_EVENT_CONSTRAINT(0x25, 0x3), - UNCORE_EVENT_CONSTRAINT(0x26, 0x3), - UNCORE_EVENT_CONSTRAINT(0x28, 0x3), - UNCORE_EVENT_CONSTRAINT(0x29, 0x3), - UNCORE_EVENT_CONSTRAINT(0x2c, 0x3), - UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), - UNCORE_EVENT_CONSTRAINT(0x2e, 0x3), - UNCORE_EVENT_CONSTRAINT(0x2f, 0x3), - UNCORE_EVENT_CONSTRAINT(0x31, 0x3), - UNCORE_EVENT_CONSTRAINT(0x32, 0x3), - UNCORE_EVENT_CONSTRAINT(0x33, 0x3), - UNCORE_EVENT_CONSTRAINT(0x34, 0x3), - UNCORE_EVENT_CONSTRAINT(0x36, 0x3), - UNCORE_EVENT_CONSTRAINT(0x37, 0x3), - UNCORE_EVENT_CONSTRAINT(0x38, 0x3), - UNCORE_EVENT_CONSTRAINT(0x39, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x14, 0x15, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x1f, 0x23, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x25, 0x26, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x28, 0x29, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x2c, 0x2f, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x31, 0x34, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x36, 0x39, 0x3), EVENT_CONSTRAINT_END }; =20 @@ -3371,8 +3302,7 @@ static struct event_constraint bdx_uncore_r2pcie_cons= traints[] =3D { UNCORE_EVENT_CONSTRAINT(0x25, 0x1), UNCORE_EVENT_CONSTRAINT(0x26, 0x3), UNCORE_EVENT_CONSTRAINT(0x28, 0x3), - UNCORE_EVENT_CONSTRAINT(0x2c, 0x3), - UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x2c, 0x2d, 0x3), EVENT_CONSTRAINT_END }; =20 @@ -3387,35 +3317,18 @@ static struct intel_uncore_type bdx_uncore_r2pcie = =3D { =20 static struct event_constraint bdx_uncore_r3qpi_constraints[] =3D { UNCORE_EVENT_CONSTRAINT(0x01, 0x7), - UNCORE_EVENT_CONSTRAINT(0x07, 0x7), - UNCORE_EVENT_CONSTRAINT(0x08, 0x7), - UNCORE_EVENT_CONSTRAINT(0x09, 0x7), - UNCORE_EVENT_CONSTRAINT(0x0a, 0x7), + UNCORE_EVENT_CONSTRAINT_RANGE(0x07, 0x0a, 0x7), UNCORE_EVENT_CONSTRAINT(0x0e, 0x7), - UNCORE_EVENT_CONSTRAINT(0x10, 0x3), - UNCORE_EVENT_CONSTRAINT(0x11, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x10, 0x11, 0x3), UNCORE_EVENT_CONSTRAINT(0x13, 0x1), - UNCORE_EVENT_CONSTRAINT(0x14, 0x3), - UNCORE_EVENT_CONSTRAINT(0x15, 0x3), - UNCORE_EVENT_CONSTRAINT(0x1f, 0x3), - UNCORE_EVENT_CONSTRAINT(0x20, 0x3), - UNCORE_EVENT_CONSTRAINT(0x21, 0x3), - UNCORE_EVENT_CONSTRAINT(0x22, 0x3), - UNCORE_EVENT_CONSTRAINT(0x23, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x14, 0x15, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x1f, 0x23, 0x3), UNCORE_EVENT_CONSTRAINT(0x25, 0x3), UNCORE_EVENT_CONSTRAINT(0x26, 0x3), - UNCORE_EVENT_CONSTRAINT(0x28, 0x3), - UNCORE_EVENT_CONSTRAINT(0x29, 0x3), - UNCORE_EVENT_CONSTRAINT(0x2c, 0x3), - UNCORE_EVENT_CONSTRAINT(0x2d, 0x3), - UNCORE_EVENT_CONSTRAINT(0x2e, 0x3), - UNCORE_EVENT_CONSTRAINT(0x2f, 0x3), - UNCORE_EVENT_CONSTRAINT(0x33, 0x3), - UNCORE_EVENT_CONSTRAINT(0x34, 0x3), - UNCORE_EVENT_CONSTRAINT(0x36, 0x3), - UNCORE_EVENT_CONSTRAINT(0x37, 0x3), - UNCORE_EVENT_CONSTRAINT(0x38, 0x3), - UNCORE_EVENT_CONSTRAINT(0x39, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x28, 0x29, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x2c, 0x2f, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x33, 0x34, 0x3), + UNCORE_EVENT_CONSTRAINT_RANGE(0x36, 0x39, 0x3), EVENT_CONSTRAINT_END }; =20 @@ -3722,8 +3635,7 @@ static struct event_constraint skx_uncore_iio_constra= ints[] =3D { UNCORE_EVENT_CONSTRAINT(0x95, 0xc), UNCORE_EVENT_CONSTRAINT(0xc0, 0xc), UNCORE_EVENT_CONSTRAINT(0xc5, 0xc), - UNCORE_EVENT_CONSTRAINT(0xd4, 0xc), - UNCORE_EVENT_CONSTRAINT(0xd5, 0xc), + UNCORE_EVENT_CONSTRAINT_RANGE(0xd4, 0xd5, 0xc), EVENT_CONSTRAINT_END }; =20 @@ -4479,14 +4391,9 @@ static struct intel_uncore_type skx_uncore_m2pcie = =3D { }; =20 static struct event_constraint skx_uncore_m3upi_constraints[] =3D { - UNCORE_EVENT_CONSTRAINT(0x1d, 0x1), - UNCORE_EVENT_CONSTRAINT(0x1e, 0x1), + UNCORE_EVENT_CONSTRAINT_RANGE(0x1d, 0x1e, 0x1), UNCORE_EVENT_CONSTRAINT(0x40, 0x7), - UNCORE_EVENT_CONSTRAINT(0x4e, 0x7), - UNCORE_EVENT_CONSTRAINT(0x4f, 0x7), - UNCORE_EVENT_CONSTRAINT(0x50, 0x7), - UNCORE_EVENT_CONSTRAINT(0x51, 0x7), - UNCORE_EVENT_CONSTRAINT(0x52, 0x7), + UNCORE_EVENT_CONSTRAINT_RANGE(0x4e, 0x52, 0x7), EVENT_CONSTRAINT_END }; =20 @@ -5652,14 +5559,9 @@ static struct intel_uncore_type icx_uncore_upi =3D { }; =20 static struct event_constraint icx_uncore_m3upi_constraints[] =3D { - UNCORE_EVENT_CONSTRAINT(0x1c, 0x1), - UNCORE_EVENT_CONSTRAINT(0x1d, 0x1), - UNCORE_EVENT_CONSTRAINT(0x1e, 0x1), - UNCORE_EVENT_CONSTRAINT(0x1f, 0x1), + UNCORE_EVENT_CONSTRAINT_RANGE(0x1c, 0x1f, 0x1), UNCORE_EVENT_CONSTRAINT(0x40, 0x7), - UNCORE_EVENT_CONSTRAINT(0x4e, 0x7), - UNCORE_EVENT_CONSTRAINT(0x4f, 0x7), - UNCORE_EVENT_CONSTRAINT(0x50, 0x7), + UNCORE_EVENT_CONSTRAINT_RANGE(0x4e, 0x50, 0x7), EVENT_CONSTRAINT_END }; =20 @@ -6142,10 +6044,7 @@ static struct intel_uncore_ops spr_uncore_mmio_offs8= _ops =3D { static struct event_constraint spr_uncore_cxlcm_constraints[] =3D { UNCORE_EVENT_CONSTRAINT(0x02, 0x0f), UNCORE_EVENT_CONSTRAINT(0x05, 0x0f), - UNCORE_EVENT_CONSTRAINT(0x40, 0xf0), - UNCORE_EVENT_CONSTRAINT(0x41, 0xf0), - UNCORE_EVENT_CONSTRAINT(0x42, 0xf0), - UNCORE_EVENT_CONSTRAINT(0x43, 0xf0), + UNCORE_EVENT_CONSTRAINT_RANGE(0x40, 0x43, 0xf0), UNCORE_EVENT_CONSTRAINT(0x4b, 0xf0), UNCORE_EVENT_CONSTRAINT(0x52, 0xf0), EVENT_CONSTRAINT_END --=20 2.52.0 From nobody Sat Feb 7 18:20:28 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 155E13101D4; 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a="68816649" X-IronPort-AV: E=Sophos;i="6.21,193,1763452800"; d="scan'208";a="68816649" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Dec 2025 14:49:42 -0800 X-CSE-ConnectionGUID: 5W4zaJ+PR82T/4OwXbCu5Q== X-CSE-MsgGUID: Z4f9f+DTTbyerje5fO9SjA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,193,1763452800"; d="scan'208";a="232611031" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Dec 2025 14:49:42 -0800 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Xudong Hao , Falcon Thomas Subject: [PATCH V2 10/13] perf/x86/intel/uncore: Update DMR uncore constraints preliminarily Date: Wed, 31 Dec 2025 14:42:27 -0800 Message-ID: <20251231224233.113839-11-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251231224233.113839-1-zide.chen@intel.com> References: <20251231224233.113839-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update event constraints base on the latest DMR uncore event list. Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi --- V2: - make use of the new UNCORE_EVENT_CONSTRAINT_RANGE arch/x86/events/intel/uncore_snbep.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index fac2be780276..3f96fcc8562b 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -6660,10 +6660,19 @@ static const struct attribute_group dmr_cxlcm_uncor= e_format_group =3D { .attrs =3D dmr_cxlcm_uncore_formats_attr, }; =20 +static struct event_constraint dmr_uncore_cxlcm_constraints[] =3D { + UNCORE_EVENT_CONSTRAINT_RANGE(0x1, 0x24, 0x0f), + UNCORE_EVENT_CONSTRAINT_RANGE(0x41, 0x41, 0xf0), + UNCORE_EVENT_CONSTRAINT_RANGE(0x50, 0x5e, 0xf0), + UNCORE_EVENT_CONSTRAINT_RANGE(0x60, 0x61, 0xf0), + EVENT_CONSTRAINT_END +}; + static struct intel_uncore_type dmr_uncore_cxlcm =3D { .name =3D "cxlcm", .event_mask =3D GENERIC_PMON_RAW_EVENT_MASK, .event_mask_ext =3D DMR_CXLCM_EVENT_MASK_EXT, + .constraints =3D dmr_uncore_cxlcm_constraints, .format_group =3D &dmr_cxlcm_uncore_format_group, .attr_update =3D uncore_alias_groups, }; @@ -6675,9 +6684,20 @@ static struct intel_uncore_type dmr_uncore_hamvf =3D= { .attr_update =3D uncore_alias_groups, }; =20 +static struct event_constraint dmr_uncore_cbo_constraints[] =3D { + UNCORE_EVENT_CONSTRAINT(0x11, 0x1), + UNCORE_EVENT_CONSTRAINT_RANGE(0x19, 0x1a, 0x1), + UNCORE_EVENT_CONSTRAINT(0x1f, 0x1), + UNCORE_EVENT_CONSTRAINT(0x21, 0x1), + UNCORE_EVENT_CONSTRAINT(0x25, 0x1), + UNCORE_EVENT_CONSTRAINT(0x36, 0x1), + EVENT_CONSTRAINT_END +}; + static struct intel_uncore_type dmr_uncore_cbo =3D { .name =3D "cbo", .event_mask_ext =3D DMR_HAMVF_EVENT_MASK_EXT, + .constraints =3D dmr_uncore_cbo_constraints, .format_group =3D &dmr_sca_uncore_format_group, .attr_update =3D uncore_alias_groups, }; @@ -6711,9 +6731,16 @@ static struct intel_uncore_type dmr_uncore_dda =3D { .attr_update =3D uncore_alias_groups, }; =20 +static struct event_constraint dmr_uncore_sbo_constraints[] =3D { + UNCORE_EVENT_CONSTRAINT(0x1f, 0x01), + UNCORE_EVENT_CONSTRAINT(0x25, 0x01), + EVENT_CONSTRAINT_END +}; + static struct intel_uncore_type dmr_uncore_sbo =3D { .name =3D "sbo", .event_mask_ext =3D DMR_HAMVF_EVENT_MASK_EXT, + .constraints =3D dmr_uncore_sbo_constraints, .format_group =3D &dmr_sca_uncore_format_group, .attr_update =3D uncore_alias_groups, }; --=20 2.52.0 From nobody Sat Feb 7 18:20:28 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F0B0310762; Wed, 31 Dec 2025 22:49:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767221389; cv=none; b=X9paDY0Wz1fWCsojM6AIDFjbsMaupyq/saRdQmtgvmR+ztSKN8WYrcDJ5gOEyN9nBgWKeaDV11U+8bC2yY3jas9vsn5QWuBQHjGZLdOljtSMZ084zewhgskgkjTujm4VjLNhqtS027xZ+cn8JPLnRTilaP77RIjrDdJOdDGRJ7U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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d="scan'208";a="232611034" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Dec 2025 14:49:42 -0800 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Xudong Hao , Falcon Thomas Subject: [PATCH V2 11/13] perf pmu: Relax uncore wildcard matching to allow numeric suffix Date: Wed, 31 Dec 2025 14:42:28 -0800 Message-ID: <20251231224233.113839-12-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251231224233.113839-1-zide.chen@intel.com> References: <20251231224233.113839-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Diamond Rapids introduces two types of PCIe related uncore PMUs: "uncore_pcie4_*" and "uncore_pcie6_*". To ensure that generic PCIe events (e.g., UNC_PCIE_CLOCKTICKS) can match and collect events from both PMU types, slightly relax the wildcard matching logic in perf_pmu__match_wildcard(). This change allows a wildcard such as "pcie" to match PMU names that include a numeric suffix, such as "pcie4_*" and "pcie6_*". Co-developed-by: Dapeng Mi Signed-off-by: Dapeng Mi Reviewed-by: Dapeng Mi Signed-off-by: Zide Chen --- tools/perf/util/pmu.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 956ea273c2c7..01a21b6aa031 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -939,6 +939,7 @@ static bool perf_pmu__match_wildcard(const char *pmu_na= me, const char *tok) { const char *p, *suffix; bool has_hex =3D false; + bool has_underscore =3D false; size_t tok_len =3D strlen(tok); =20 /* Check start of pmu_name for equality. */ @@ -949,13 +950,14 @@ static bool perf_pmu__match_wildcard(const char *pmu_= name, const char *tok) if (*p =3D=3D 0) return true; =20 - if (*p =3D=3D '_') { - ++p; - ++suffix; - } - - /* Ensure we end in a number */ + /* Ensure we end in a number or a mix of number and "_". */ while (1) { + if (!has_underscore && (*p =3D=3D '_')) { + has_underscore =3D true; + ++p; + ++suffix; + } + if (!isxdigit(*p)) return false; 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X-CSE-ConnectionGUID: D1zXJ+PvTmekfDCR9FV8fQ== X-CSE-MsgGUID: AFjAkCx0Tr2FeuiR//1K0Q== X-IronPort-AV: E=McAfee;i="6800,10657,11658"; a="68816659" X-IronPort-AV: E=Sophos;i="6.21,193,1763452800"; d="scan'208";a="68816659" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Dec 2025 14:49:42 -0800 X-CSE-ConnectionGUID: 5ZREydr2RuaL9e4NV62B3w== X-CSE-MsgGUID: M5ZV9at3SeSPPXMav2xZGg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,193,1763452800"; d="scan'208";a="232611037" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Dec 2025 14:49:42 -0800 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Xudong Hao , Falcon Thomas Subject: [PATCH V2 12/13] perf/x86/intel/uncore: Add missing PMON units for Panther Lake Date: Wed, 31 Dec 2025 14:42:29 -0800 Message-ID: <20251231224233.113839-13-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251231224233.113839-1-zide.chen@intel.com> References: <20251231224233.113839-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Besides CBOX, Panther Lake includes several legacy uncore PMON units not enumerated via discovery tables, including cNCU, SANTA, and ia_core_bridge. The cNCU PMON is similar to Meteor Lake but has two boxes with two counters each. SANTA and IA Core Bridge PMON units follow the legacy model used on Lunar Lake, Meteor Lake, and others. Panther Lake implements the Global Control Register; the freeze_all bit must be cleared before programming counters. Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi --- V2: new patch arch/x86/events/intel/uncore.c | 1 + arch/x86/events/intel/uncore_snb.c | 45 ++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 54b3c1e3af32..07a9a2826398 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1814,6 +1814,7 @@ static const struct uncore_plat_init ptl_uncore_init = __initconst =3D { .cpu_init =3D ptl_uncore_cpu_init, .mmio_init =3D ptl_uncore_mmio_init, .domain[0].discovery_base =3D UNCORE_DISCOVERY_MSR, + .domain[0].global_init =3D uncore_mmio_global_init, }; =20 static const struct uncore_plat_init icx_uncore_init __initconst =3D { diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/unc= ore_snb.c index 807e582b8f17..c663b00b68fe 100644 --- a/arch/x86/events/intel/uncore_snb.c +++ b/arch/x86/events/intel/uncore_snb.c @@ -245,6 +245,17 @@ #define MTL_UNC_HBO_CTR 0x2048 #define MTL_UNC_HBO_CTRL 0x2042 =20 +/* PTL Low Power Bridge register */ +#define PTL_UNC_IA_CORE_BRIDGE_PER_CTR0 0x2028 +#define PTL_UNC_IA_CORE_BRIDGE_PERFEVTSEL0 0x2022 + +/* PTL Santa register */ +#define PTL_UNC_SANTA_CTR0 0x2418 +#define PTL_UNC_SANTA_CTRL0 0x2412 + +/* PTL cNCU register */ +#define PTL_UNC_CNCU_MSR_OFFSET 0x140 + DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7"); DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15"); DEFINE_UNCORE_FORMAT_ATTR(chmask, chmask, "config:8-11"); @@ -1921,8 +1932,36 @@ void ptl_uncore_mmio_init(void) ptl_uncores); } =20 +static struct intel_uncore_type ptl_uncore_ia_core_bridge =3D { + .name =3D "ia_core_bridge", + .num_counters =3D 2, + .num_boxes =3D 1, + .perf_ctr_bits =3D 48, + .perf_ctr =3D PTL_UNC_IA_CORE_BRIDGE_PER_CTR0, + .event_ctl =3D PTL_UNC_IA_CORE_BRIDGE_PERFEVTSEL0, + .event_mask =3D ADL_UNC_RAW_EVENT_MASK, + .ops =3D &icl_uncore_msr_ops, + .format_group =3D &adl_uncore_format_group, +}; + +static struct intel_uncore_type ptl_uncore_santa =3D { + .name =3D "santa", + .num_counters =3D 2, + .num_boxes =3D 2, + .perf_ctr_bits =3D 48, + .perf_ctr =3D PTL_UNC_SANTA_CTR0, + .event_ctl =3D PTL_UNC_SANTA_CTRL0, + .event_mask =3D ADL_UNC_RAW_EVENT_MASK, + .msr_offset =3D SNB_UNC_CBO_MSR_OFFSET, + .ops =3D &icl_uncore_msr_ops, + .format_group =3D &adl_uncore_format_group, +}; + static struct intel_uncore_type *ptl_msr_uncores[] =3D { &mtl_uncore_cbox, + &ptl_uncore_ia_core_bridge, + &ptl_uncore_santa, + &mtl_uncore_cncu, NULL }; =20 @@ -1930,6 +1969,12 @@ void ptl_uncore_cpu_init(void) { mtl_uncore_cbox.num_boxes =3D 6; mtl_uncore_cbox.ops =3D &lnl_uncore_msr_ops; + + mtl_uncore_cncu.num_counters =3D 2; + mtl_uncore_cncu.num_boxes =3D 2; + mtl_uncore_cncu.msr_offset =3D PTL_UNC_CNCU_MSR_OFFSET; + mtl_uncore_cncu.single_fixed =3D 0; + uncore_msr_uncores =3D ptl_msr_uncores; } =20 --=20 2.52.0 From nobody Sat Feb 7 18:20:28 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FB03311597; Wed, 31 Dec 2025 22:49:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767221391; cv=none; b=jHcZwVRD/B8tRx9oktwZvBafH2f1BhaNaKAjqRUHAMBmpe8/LlHnaQXUk3HvMb7qwPFc/FqQnt9r7Mo5PVSG1gORRK4zHy53QrCXKD7ovWB1781ZBL+8MDZPk825UYjGxWBQ4yko+vdtuZcY39XRXoyQ1NtAV04JCbBJ3+mgR4Q= ARC-Message-Signature: i=1; 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d="scan'208";a="232611040" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.43]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Dec 2025 14:49:42 -0800 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Xudong Hao , Falcon Thomas Subject: [PATCH V2 13/13] perf/x86/intel/uncore: Add Nova Lake support Date: Wed, 31 Dec 2025 14:42:30 -0800 Message-ID: <20251231224233.113839-14-zide.chen@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251231224233.113839-1-zide.chen@intel.com> References: <20251231224233.113839-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Nova Lake uncore PMON largely follows Panther Lake and supports CBOX, iMC, cNCU, SANTA, sNCU, and HBO units. As with Panther Lake, CBOX, cNCU, and SANTA are not enumerated via discovery tables. Their programming model matches Panther Lake, with differences limited to MSR addresses and the number of boxes or counters per box. The remaining units are enumerated via discovery tables using a new base MSR (0x711) and otherwise reuse the Panther Lake implementation. Nova Lake also supports iMC free-running counters. Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi --- V2: new patch arch/x86/events/intel/uncore.c | 9 ++++++ arch/x86/events/intel/uncore.h | 1 + arch/x86/events/intel/uncore_discovery.h | 2 ++ arch/x86/events/intel/uncore_snb.c | 40 ++++++++++++++++++++++++ 4 files changed, 52 insertions(+) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 07a9a2826398..2607bf178658 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1817,6 +1817,13 @@ static const struct uncore_plat_init ptl_uncore_init= __initconst =3D { .domain[0].global_init =3D uncore_mmio_global_init, }; =20 +static const struct uncore_plat_init nvl_uncore_init __initconst =3D { + .cpu_init =3D nvl_uncore_cpu_init, + .mmio_init =3D ptl_uncore_mmio_init, + .domain[0].discovery_base =3D PACKAGE_UNCORE_DISCOVERY_MSR, + .domain[0].global_init =3D uncore_mmio_global_init, +}; + static const struct uncore_plat_init icx_uncore_init __initconst =3D { .cpu_init =3D icx_uncore_cpu_init, .pci_init =3D icx_uncore_pci_init, @@ -1916,6 +1923,8 @@ static const struct x86_cpu_id intel_uncore_match[] _= _initconst =3D { X86_MATCH_VFM(INTEL_LUNARLAKE_M, &lnl_uncore_init), X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &ptl_uncore_init), X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &ptl_uncore_init), + X86_MATCH_VFM(INTEL_NOVALAKE, &nvl_uncore_init), + X86_MATCH_VFM(INTEL_NOVALAKE_L, &nvl_uncore_init), X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &spr_uncore_init), X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &spr_uncore_init), X86_MATCH_VFM(INTEL_GRANITERAPIDS_X, &gnr_uncore_init), diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index 564cb26c4468..c35918c01afa 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -636,6 +636,7 @@ void adl_uncore_cpu_init(void); void lnl_uncore_cpu_init(void); void mtl_uncore_cpu_init(void); void ptl_uncore_cpu_init(void); +void nvl_uncore_cpu_init(void); void tgl_uncore_mmio_init(void); void tgl_l_uncore_mmio_init(void); void adl_uncore_mmio_init(void); diff --git a/arch/x86/events/intel/uncore_discovery.h b/arch/x86/events/int= el/uncore_discovery.h index 63b8f7634e42..e1330342b92e 100644 --- a/arch/x86/events/intel/uncore_discovery.h +++ b/arch/x86/events/intel/uncore_discovery.h @@ -4,6 +4,8 @@ #define UNCORE_DISCOVERY_MSR 0x201e /* Base address of uncore perfmon discovery table for CBB domain */ #define CBB_UNCORE_DISCOVERY_MSR 0x710 +/* Base address of uncore perfmon discovery table for the package */ +#define PACKAGE_UNCORE_DISCOVERY_MSR 0x711 =20 /* Generic device ID of a discovery table device */ #define UNCORE_DISCOVERY_TABLE_DEVICE 0x09a7 diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/unc= ore_snb.c index c663b00b68fe..e8e44741200e 100644 --- a/arch/x86/events/intel/uncore_snb.c +++ b/arch/x86/events/intel/uncore_snb.c @@ -256,6 +256,19 @@ /* PTL cNCU register */ #define PTL_UNC_CNCU_MSR_OFFSET 0x140 =20 +/* NVL cNCU register */ +#define NVL_UNC_CNCU_BOX_CTL 0x202e +#define NVL_UNC_CNCU_FIXED_CTR 0x2028 +#define NVL_UNC_CNCU_FIXED_CTRL 0x2022 + +/* NVL SANTA register */ +#define NVL_UNC_SANTA_CTR0 0x2048 +#define NVL_UNC_SANTA_CTRL0 0x2042 + +/* NVL CBOX register */ +#define NVL_UNC_CBOX_PER_CTR0 0x2108 +#define NVL_UNC_CBOX_PERFEVTSEL0 0x2102 + DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7"); DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15"); DEFINE_UNCORE_FORMAT_ATTR(chmask, chmask, "config:8-11"); @@ -1979,3 +1992,30 @@ void ptl_uncore_cpu_init(void) } =20 /* end of Panther Lake uncore support */ + +/* Nova Lake uncore support */ + +static struct intel_uncore_type *nvl_msr_uncores[] =3D { + &mtl_uncore_cbox, + &ptl_uncore_santa, + &mtl_uncore_cncu, + NULL +}; + +void nvl_uncore_cpu_init(void) +{ + mtl_uncore_cbox.num_boxes =3D 12; + mtl_uncore_cbox.perf_ctr =3D NVL_UNC_CBOX_PER_CTR0, + mtl_uncore_cbox.event_ctl =3D NVL_UNC_CBOX_PERFEVTSEL0, + + ptl_uncore_santa.perf_ctr =3D NVL_UNC_SANTA_CTR0, + ptl_uncore_santa.event_ctl =3D NVL_UNC_SANTA_CTRL0, + + mtl_uncore_cncu.box_ctl =3D NVL_UNC_CNCU_BOX_CTL; + mtl_uncore_cncu.fixed_ctr =3D NVL_UNC_CNCU_FIXED_CTR; + mtl_uncore_cncu.fixed_ctl =3D NVL_UNC_CNCU_FIXED_CTRL; + + uncore_msr_uncores =3D nvl_msr_uncores; +} + +/* end of Nova Lake uncore support */ --=20 2.52.0