From nobody Sat Feb 7 09:59:00 2026 Received: from out-172.mta1.migadu.com (out-172.mta1.migadu.com [95.215.58.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0FB422F068C for ; Wed, 31 Dec 2025 03:45:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767152735; cv=none; b=udNELeqx31NhMNNV9daPMffhJ0vIwJAY+jIBBsboQ78nwuc+6CLX2PJb8jsxUlB6oRaqGwvS/plr+GqbQnlUvok2NBEkCzxVKKDU1ABL0n0zpdgvnM4foOgP/7wLyZuMpY5LIn/YJbku5qb07wkhKGR83Bg/zpFmUuD9Gtvuasg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767152735; c=relaxed/simple; bh=BuuxaCwSCLYg1R0ojnfESNIxbCZSrE0vV6q/iS4ppy8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oVML+qyGLghG4nxIRAABKfZOT77B3ExK1kEzoAWxprFzME8Zte2LxwIDUw4CyWs+T9y/XviJgW2ZSVYmUEGt46e0F199PBgoDKNQ0RUjicxYDEf153ebabPGHha9Bo4sqMWJzyLTvCsbQXNjT79gZbViBCYKbRi1+eRB1H/FFaI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=MDkQCOg4; arc=none smtp.client-ip=95.215.58.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="MDkQCOg4" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1767152731; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3ej0WdmIZc8uYGH7uI3cqt+SohwtHVALnfZQqf9BhrA=; b=MDkQCOg4MxnDXTsUAHz+NV+50tvBkG4ZPJVhxdvt/UI9Grm983Y95OtWBQ5VDiCXFXc/kF QdKg9Ky+I5rO8ey/SDnpt2wQ8IY79yf1F4NeyoJyNXDQBLJLjqz32198l3nj8RdHFYEhmn vPiaCmqc3uHllNTGVqI4tb3O6bLG+4I= From: George Guo To: hengqi.chen@gmail.com Cc: chenhuacai@kernel.org, dongtai.guo@linux.dev, guodongtai@kylinos.cn, kernel@xen0n.name, lianyangyang@kylinos.cn, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, r@hev.cc, xry111@xry111.site Subject: [PATCH v8 loongarch-next 1/3] LoongArch: Add SCQ support detection Date: Wed, 31 Dec 2025 11:45:21 +0800 Message-ID: <20251231034523.47014-2-dongtai.guo@linux.dev> In-Reply-To: <20251231034523.47014-1-dongtai.guo@linux.dev> References: <20251231034523.47014-1-dongtai.guo@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" From: George Guo Check CPUCFG2_SCQ bit to determine if the CPU supports SCQ instruction. Co-developed-by: Yangyang Lian Signed-off-by: Yangyang Lian Signed-off-by: George Guo Reviewed-by: Hengqi Chen Tested-by: Hengqi Chen --- arch/loongarch/include/asm/cpu-features.h | 1 + arch/loongarch/include/asm/cpu.h | 2 ++ arch/loongarch/include/asm/loongarch.h | 1 + arch/loongarch/kernel/cpu-probe.c | 2 ++ arch/loongarch/kernel/proc.c | 1 + 5 files changed, 7 insertions(+) diff --git a/arch/loongarch/include/asm/cpu-features.h b/arch/loongarch/inc= lude/asm/cpu-features.h index 3745d991a99a..39c7fe64c3ef 100644 --- a/arch/loongarch/include/asm/cpu-features.h +++ b/arch/loongarch/include/asm/cpu-features.h @@ -67,5 +67,6 @@ #define cpu_has_msgint cpu_opt(LOONGARCH_CPU_MSGINT) #define cpu_has_avecint cpu_opt(LOONGARCH_CPU_AVECINT) #define cpu_has_redirectint cpu_opt(LOONGARCH_CPU_REDIRECTINT) +#define cpu_has_scq cpu_opt(LOONGARCH_CPU_SCQ) =20 #endif /* __ASM_CPU_FEATURES_H */ diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/include/asm/= cpu.h index f3efb00b6141..5531039027ec 100644 --- a/arch/loongarch/include/asm/cpu.h +++ b/arch/loongarch/include/asm/cpu.h @@ -125,6 +125,7 @@ static inline char *id_to_core_name(unsigned int id) #define CPU_FEATURE_MSGINT 29 /* CPU has MSG interrupt */ #define CPU_FEATURE_AVECINT 30 /* CPU has AVEC interrupt */ #define CPU_FEATURE_REDIRECTINT 31 /* CPU has interrupt remapping */ +#define CPU_FEATURE_SCQ 32 /* CPU has SC.Q instruction */ =20 #define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG) #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM) @@ -158,5 +159,6 @@ static inline char *id_to_core_name(unsigned int id) #define LOONGARCH_CPU_MSGINT BIT_ULL(CPU_FEATURE_MSGINT) #define LOONGARCH_CPU_AVECINT BIT_ULL(CPU_FEATURE_AVECINT) #define LOONGARCH_CPU_REDIRECTINT BIT_ULL(CPU_FEATURE_REDIRECTINT) +#define LOONGARCH_CPU_SCQ BIT_ULL(CPU_FEATURE_SCQ) =20 #endif /* _ASM_CPU_H */ diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/includ= e/asm/loongarch.h index e6b8ff61c8cc..817cd90941d9 100644 --- a/arch/loongarch/include/asm/loongarch.h +++ b/arch/loongarch/include/asm/loongarch.h @@ -94,6 +94,7 @@ #define CPUCFG2_LSPW BIT(21) #define CPUCFG2_LAM BIT(22) #define CPUCFG2_PTW BIT(24) +#define CPUCFG2_SCQ BIT(30) =20 #define LOONGARCH_CPUCFG3 0x3 #define CPUCFG3_CCDMA BIT(0) diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-= probe.c index 08a227034042..382c472c6bfe 100644 --- a/arch/loongarch/kernel/cpu-probe.c +++ b/arch/loongarch/kernel/cpu-probe.c @@ -205,6 +205,8 @@ static void cpu_probe_common(struct cpuinfo_loongarch *= c) c->options |=3D LOONGARCH_CPU_PTW; elf_hwcap |=3D HWCAP_LOONGARCH_PTW; } + if (config & CPUCFG2_SCQ) + c->options |=3D LOONGARCH_CPU_SCQ; if (config & CPUCFG2_LSPW) { c->options |=3D LOONGARCH_CPU_LSPW; elf_hwcap |=3D HWCAP_LOONGARCH_LSPW; diff --git a/arch/loongarch/kernel/proc.c b/arch/loongarch/kernel/proc.c index a8800d20e11b..252fa1d03b85 100644 --- a/arch/loongarch/kernel/proc.c +++ b/arch/loongarch/kernel/proc.c @@ -75,6 +75,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) if (cpu_has_lbt_x86) seq_printf(m, " lbt_x86"); if (cpu_has_lbt_arm) seq_printf(m, " lbt_arm"); if (cpu_has_lbt_mips) seq_printf(m, " lbt_mips"); + if (cpu_has_scq) seq_printf(m, " scq"); seq_printf(m, "\n"); =20 seq_printf(m, "Hardware Watchpoint\t: %s", str_yes_no(cpu_has_watch)); --=20 2.49.0 From nobody Sat Feb 7 09:59:00 2026 Received: from out-182.mta1.migadu.com (out-182.mta1.migadu.com [95.215.58.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAC692F3612 for ; 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DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1767152735; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KwyqUC0qz/7HldbWplcKPTskOM2D1bC7Y9+f+VDp2yQ=; b=YlqKW2YPFXzP/NfHxUOCvdS2e+rAjnJnUuMJi4qW94ixhcmbHZ6qcjieZ2On6ev/83H4hu ODgo7lArJnU/6KCUJO+c0qgDknwj5NPtFpSJcWDkLxW7LiAyqJD1JUeFJ+xbB0t8gdpdNz CqMAeVCwjFaUWH7DUjbC6ZVFO7fudhE= From: George Guo To: hengqi.chen@gmail.com Cc: chenhuacai@kernel.org, dongtai.guo@linux.dev, guodongtai@kylinos.cn, kernel@xen0n.name, lianyangyang@kylinos.cn, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, r@hev.cc, xry111@xry111.site Subject: [PATCH v8 loongarch-next 2/3] LoongArch: Add 128-bit atomic cmpxchg support Date: Wed, 31 Dec 2025 11:45:22 +0800 Message-ID: <20251231034523.47014-3-dongtai.guo@linux.dev> In-Reply-To: <20251231034523.47014-1-dongtai.guo@linux.dev> References: <20251231034523.47014-1-dongtai.guo@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" From: George Guo Implement 128-bit atomic compare-and-exchange using LoongArch's LL.D/SC.Q instructions. For LoongArch CPUs lacking 128-bit atomic instruction(e.g., the SCQ instruction on 3A5000), use a spinlock to emulate the atomic operation. At the same time, fix BPF scheduler test failures (scx_central scx_qmap) caused by kmalloc_nolock_noprof returning NULL due to missing 128-bit atomics. The NULL returns led to -ENOMEM errors during scheduler initialization, causing test cases to fail. Verified by testing with the scx_qmap scheduler (located in tools/sched_ext/). Building with `make` and running ./tools/sched_ext/build/bin/scx_qmap. Link: https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git/commit/?i= d=3D5fb750e8a9ae Signed-off-by: George Guo Acked-by: Hengqi Chen Tested-by: Hengqi Chen --- arch/loongarch/include/asm/cmpxchg.h | 66 ++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/loongarch/include/asm/cmpxchg.h b/arch/loongarch/include/= asm/cmpxchg.h index 0494c2ab553e..ef793bcb7b25 100644 --- a/arch/loongarch/include/asm/cmpxchg.h +++ b/arch/loongarch/include/asm/cmpxchg.h @@ -8,6 +8,7 @@ #include #include #include +#include =20 #define __xchg_amo_asm(amswap_db, m, val) \ ({ \ @@ -137,6 +138,61 @@ __arch_xchg(volatile void *ptr, unsigned long x, int s= ize) __ret; \ }) =20 +union __u128_halves { + u128 full; + struct { + u64 low; + u64 high; + }; +}; + +#define __cmpxchg128_asm(ptr, old, new) \ +({ \ + union __u128_halves __old, __new, __ret; \ + volatile u64 *__ptr =3D (volatile u64 *)(ptr); \ + \ + __old.full =3D (old); \ + __new.full =3D (new); \ + \ + __asm__ __volatile__( \ + "1: ll.d %0, %3 # 128-bit cmpxchg low \n" \ + __WEAK_LLSC_MB \ + " ld.d %1, %4 # 128-bit cmpxchg high \n" \ + " bne %0, %z5, 2f \n" \ + " bne %1, %z6, 2f \n" \ + " move $t0, %z7 \n" \ + " move $t1, %z8 \n" \ + " sc.q $t0, $t1, %2 \n" \ + " beqz $t0, 1b \n" \ + "2: \n" \ + __WEAK_LLSC_MB \ + : "=3D&r" (__ret.low), "=3D&r" (__ret.high) \ + : "r" (__ptr), \ + "ZC" (__ptr[0]), "m" (__ptr[1]), \ + "Jr" (__old.low), "Jr" (__old.high), \ + "Jr" (__new.low), "Jr" (__new.high) \ + : "t0", "t1", "memory"); \ + \ + __ret.full; \ +}) + +#define __cmpxchg128_locked(ptr, old, new) \ +({ \ + u128 __ret; \ + static DEFINE_SPINLOCK(lock); \ + unsigned long flags; \ + \ + spin_lock_irqsave(&lock, flags); \ + \ + __ret =3D *(volatile u128 *)(ptr); \ + if (__ret =3D=3D (old)) \ + *(volatile u128 *)(ptr) =3D (new); \ + \ + spin_unlock_irqrestore(&lock, flags); \ + \ + __ret; \ +}) + static inline unsigned int __cmpxchg_small(volatile void *ptr, unsigned in= t old, unsigned int new, unsigned int size) { @@ -224,6 +280,16 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsig= ned long new, unsigned int __res; \ }) =20 +/* cmpxchg128 */ +#define system_has_cmpxchg128() 1 + +#define arch_cmpxchg128(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 16); \ + cpu_has_scq ? __cmpxchg128_asm(ptr, o, n) : \ + __cmpxchg128_locked(ptr, o, n); \ +}) + #ifdef CONFIG_64BIT #define arch_cmpxchg64_local(ptr, o, n) \ ({ \ --=20 2.49.0 From nobody Sat Feb 7 09:59:00 2026 Received: from out-173.mta1.migadu.com (out-173.mta1.migadu.com [95.215.58.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAB8C2F290B for ; Wed, 31 Dec 2025 03:45:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767152740; cv=none; b=bVcU5dr+EGNmj/Q/d9U7+XYVMZQ32yb9lV23AFjbk9qTpripvjB8LzlIYgxo1vBQfYYwstPm0vqR3y1REy2nR8Q93jGkcTapKNvey9C8uz6QVH27qgI2+MW54fHRItsrSu89xAnzj6S7konPu+cHPMLA8g37o3l4nUqIO5x9nE8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767152740; c=relaxed/simple; bh=sxTP2oXXUnc5NysmI2N+EZ1bqhsGfXhqVJPVELj4s9Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Rx9u3t12Jia4Csvey8l3nxChCaJV8qdStEnD0coqsgNFcIKGb7HJOkGHR6k1/CK0ad68KlLsya0qapi5mb7Q2egzzqvQPhlLZLqRwOFjxYAHRXOMkcqJyiyRqKKJa4ikjP4xZ1YFGVmecOKK4rWQ96R/0kvPA/oczSRckGaIlgc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=OV85iR8K; arc=none smtp.client-ip=95.215.58.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="OV85iR8K" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1767152737; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PqpeETFJkzNuoFoanCBY+LFS018RYhS6I82D9WQGSDc=; b=OV85iR8KBGbrdZ+m+1p7Sr7AwqQkRY1v1yrNwDddheK74m/bKJ4Nk6z0EyGMXS5zqvUnEI bmoT4p4lsCDBOz4y3oq+iKBxbSJiEIxZVt0nBW65KDii4TQE5mdooQVBINNmB57I8tqJlh D+xcX1QyUodNoB59sWStcH4t7goSt1c= From: George Guo To: hengqi.chen@gmail.com Cc: chenhuacai@kernel.org, dongtai.guo@linux.dev, guodongtai@kylinos.cn, kernel@xen0n.name, lianyangyang@kylinos.cn, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, r@hev.cc, xry111@xry111.site Subject: [PATCH v8 loongarch-next 3/3] LoongArch: Enable 128-bit atomics cmpxchg support Date: Wed, 31 Dec 2025 11:45:23 +0800 Message-ID: <20251231034523.47014-4-dongtai.guo@linux.dev> In-Reply-To: <20251231034523.47014-1-dongtai.guo@linux.dev> References: <20251231034523.47014-1-dongtai.guo@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" From: George Guo Add select HAVE_CMPXCHG_DOUBLE and select HAVE_ALIGNED_STRUCT_PAGE in Kconf= ig to enable 128-bit atomic cmpxchg support on LoongArch. Signed-off-by: George Guo Reviewed-by: Hengqi Chen Tested-by: Hengqi Chen --- arch/loongarch/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index 730f34214519..f9845ebec1a4 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -114,6 +114,7 @@ config LOONGARCH select GENERIC_TIME_VSYSCALL select GPIOLIB select HAS_IOPORT + select HAVE_ALIGNED_STRUCT_PAGE select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_BITREVERSE select HAVE_ARCH_JUMP_LABEL @@ -130,6 +131,7 @@ config LOONGARCH select HAVE_ARCH_TRANSPARENT_HUGEPAGE select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD select HAVE_ASM_MODVERSIONS + select HAVE_CMPXCHG_DOUBLE select HAVE_CONTEXT_TRACKING_USER select HAVE_C_RECORDMCOUNT select HAVE_DEBUG_KMEMLEAK --=20 2.49.0