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Wed, 31 Dec 2025 01:29:38 -0800 (PST) Received: from Black-Pearl.localdomain ([122.162.204.179]) by smtp.googlemail.com with ESMTPSA id 41be03b00d2f7-c1e7961fbb9sm29842795a12.2.2025.12.31.01.29.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Dec 2025 01:29:38 -0800 (PST) From: Charan Pedumuru Date: Wed, 31 Dec 2025 09:29:32 +0000 Subject: [PATCH v3] dt-bindings: mtd: nvidia,tegra20-nand: convert to DT schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251231-nvidia-nand-v3-1-2e67664d3674@gmail.com> X-B4-Tracking: v=1; b=H4sIAPvsVGkC/1XMSwrCMBSF4a1IxkZyb2PTOnIf4iAv2ws2lUSCU rp30yJoh+fA/00s+Ug+sdNuYtFnSjSGMqr9jtleh85zcmUzFHgEAcBDJkeaBx0cFyitVdo3Rmh Wikf0N3qt2uVadk/pOcb3imdY3q9TiY2TgQNXNUgPEhts8dwNmu4HOw5scTL+WsR222JpTd0q1 yqURpj/dp7nD1ymRAziAAAA X-Change-ID: 20251011-nvidia-nand-024cc7ae8b0a To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Stefan Agner , Lucas Stach Cc: linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Charan Pedumuru X-Mailer: b4 0.14.3 Convert NVIDIA Tegra NAND Flash Controller binding to YAML format. Changes during Conversion: - Define new properties `power-domains` and `operating-points-v2` because the existing in tree DTS uses them. Signed-off-by: Charan Pedumuru --- Changes in v3: - Removed pattern properties for partition. - Used single quotes for nand string in pattern properties. - Modified maxItems value and added minItems to reg property under nand chi= ld node. - Link to v2: https://lore.kernel.org/r/20251229-nvidia-nand-v2-1-b697d9724= b0b@gmail.com Changes in v2: - Edited the commit description to match the updated changes. - Modified the description for the YAML. - Removed all the duplicated properties, defined a proper ref for both pare= nt and child nodes. - Removed unnecessary properties from the required following the old text binding. - Link to v1: https://lore.kernel.org/r/20251030-nvidia-nand-v1-1-7614e1428= 292@gmail.com --- .../bindings/mtd/nvidia,tegra20-nand.yaml | 103 +++++++++++++++++= ++++ .../bindings/mtd/nvidia-tegra20-nand.txt | 64 ------------- 2 files changed, 103 insertions(+), 64 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml= b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml new file mode 100644 index 000000000000..632cfd7dc5e2 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/nvidia,tegra20-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra NAND Flash Controller + +maintainers: + - Jonathan Hunter + +allOf: + - $ref: nand-controller.yaml + +description: + The NVIDIA NAND controller provides an interface between NVIDIA SoCs + and raw NAND flash devices. It supports standard NAND operations, + hardware-assisted ECC, OOB data access, and DMA transfers, and + integrates with the Linux MTD NAND subsystem for reliable flash manageme= nt. + +properties: + compatible: + const: nvidia,tegra20-nand + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: nand + + resets: + maxItems: 1 + + reset-names: + items: + - const: nand + + power-domains: + maxItems: 1 + + operating-points-v2: + maxItems: 1 + +patternProperties: + '^nand@': + type: object + description: Individual NAND chip connected to the NAND controller + $ref: raw-nand-chip.yaml# + + properties: + reg: + minItems: 1 + maxItems: 5 + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + nand-controller@70008000 { + compatible =3D "nvidia,tegra20-nand"; + reg =3D <0x70008000 0x100>; + interrupts =3D ; + clocks =3D <&tegra_car TEGRA20_CLK_NDFLASH>; + clock-names =3D "nand"; + resets =3D <&tegra_car 13>; + reset-names =3D "nand"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + nand@0 { + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + nand-bus-width =3D <8>; + nand-on-flash-bbt; + nand-ecc-algo =3D "bch"; + nand-ecc-strength =3D <8>; + wp-gpios =3D <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt = b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt deleted file mode 100644 index 4a00ec2b2540..000000000000 --- a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt +++ /dev/null @@ -1,64 +0,0 @@ -NVIDIA Tegra NAND Flash controller - -Required properties: -- compatible: Must be one of: - - "nvidia,tegra20-nand" -- reg: MMIO address range -- interrupts: interrupt output of the NFC controller -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - nand -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - nand - -Optional children nodes: -Individual NAND chips are children of the NAND controller node. Currently -only one NAND chip supported. - -Required children node properties: -- reg: An integer ranging from 1 to 6 representing the CS line to use. - -Optional children node properties: -- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently on= ly - "hw" is supported. -- nand-ecc-algo: string, algorithm of NAND ECC. - Supported values with "hw" ECC mode are: "rs", "bch". -- nand-bus-width : See nand-controller.yaml -- nand-on-flash-bbt: See nand-controller.yaml -- nand-ecc-strength: integer representing the number of bits to correct - per ECC step (always 512). Supported strength using HW ECC - modes are: - - RS: 4, 6, 8 - - BCH: 4, 8, 14, 16 -- nand-ecc-maximize: See nand-controller.yaml -- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot= ROM - are chosen. -- wp-gpios: GPIO specifier for the write protect pin. - -Optional child node of NAND chip nodes: -Partitions: see mtd.yaml - - Example: - nand-controller@70008000 { - compatible =3D "nvidia,tegra20-nand"; - reg =3D <0x70008000 0x100>; - interrupts =3D ; - clocks =3D <&tegra_car TEGRA20_CLK_NDFLASH>; - clock-names =3D "nand"; - resets =3D <&tegra_car 13>; - reset-names =3D "nand"; - - nand@0 { - reg =3D <0>; - #address-cells =3D <1>; - #size-cells =3D <1>; - nand-bus-width =3D <8>; - nand-on-flash-bbt; - nand-ecc-algo =3D "bch"; - nand-ecc-strength =3D <8>; - wp-gpios =3D <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; - }; - }; --- base-commit: 43edce71d70c603d3f3f1b1c886f65cd02d80c24 change-id: 20251011-nvidia-nand-024cc7ae8b0a Best regards, --=20 Charan Pedumuru