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Tue, 30 Dec 2025 12:35:40 -0800 (PST) Received: from Lewboski.localdomain ([181.191.143.75]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1217253c23csm128074981c88.9.2025.12.30.12.35.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Dec 2025 12:35:40 -0800 (PST) From: Tomas Borquez To: Jonathan Cameron , Greg Kroah-Hartman , Lars-Peter Clausen , Michael Hennerich Cc: David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux-staging@lists.linux.dev, Tomas Borquez Subject: [PATCH v2 5/6] staging: iio: ad9832: convert to iio channels and ext_info attrs Date: Tue, 30 Dec 2025 17:34:58 -0300 Message-ID: <20251230203459.28935-6-tomasborquez13@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251230203459.28935-1-tomasborquez13@gmail.com> References: <20251230203459.28935-1-tomasborquez13@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert ad9832 from sysfs attributes to standard channel interface using a single IIO_ALTCURRENT channel with ext_info attributes, as this device is a current source DAC with one output. Signed-off-by: Tomas Borquez --- drivers/staging/iio/frequency/ad9832.c | 278 +++++++++++++++++++------ 1 file changed, 220 insertions(+), 58 deletions(-) diff --git a/drivers/staging/iio/frequency/ad9832.c b/drivers/staging/iio/f= requency/ad9832.c index aa78973c3a3c..47b41b9eb14f 100644 --- a/drivers/staging/iio/frequency/ad9832.c +++ b/drivers/staging/iio/frequency/ad9832.c @@ -20,6 +20,7 @@ #include #include #include +#include =20 #include #include @@ -64,6 +65,7 @@ #define AD9832_CLR BIT(11) #define AD9832_FREQ_BITS 32 #define AD9832_PHASE_BITS 12 +#define AD9832_2PI_URAD 6283185UL #define AD9832_CMD_MSK GENMASK(15, 12) #define AD9832_ADD_MSK GENMASK(11, 8) #define AD9832_DAT_MSK GENMASK(7, 0) @@ -75,6 +77,12 @@ * @ctrl_fp: cached frequency/phase control word * @ctrl_ss: cached sync/selsrc control word * @ctrl_src: cached sleep/reset/clr word + * @freq: cached frequencies + * @freq_sym: cached frequency symbol selection + * @phase: cached phases + * @phase_sym: cached phase symbol selection + * @output_en: cached output enable state + * @pinctrl_en: cached pinctrl enable state * @xfer: default spi transfer * @msg: default spi message * @freq_xfer: tuning word spi transfer @@ -92,6 +100,12 @@ struct ad9832_state { unsigned short ctrl_fp; unsigned short ctrl_ss; unsigned short ctrl_src; + u32 freq[2]; + bool freq_sym; + u32 phase[4]; + u32 phase_sym; + bool output_en; + bool pinctrl_en; struct spi_transfer xfer; struct spi_message msg; struct spi_transfer freq_xfer[4]; @@ -110,7 +124,7 @@ struct ad9832_state { } __aligned(IIO_DMA_MINALIGN); }; =20 -static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long= fout) +static unsigned long ad9832_calc_freqreg(unsigned long mclk, u32 fout) { unsigned long long freqreg =3D (u64)fout * (u64)((u64)1L << AD9832_FREQ_BITS); @@ -118,19 +132,33 @@ static unsigned long ad9832_calc_freqreg(unsigned lon= g mclk, unsigned long fout) return freqreg; } =20 -static int ad9832_write_frequency(struct ad9832_state *st, - unsigned int addr, unsigned long fout) +static ssize_t ad9832_write_frequency(struct iio_dev *indio_dev, + uintptr_t private, + struct iio_chan_spec const *chan, + const char *buf, size_t len) { + struct ad9832_state *st =3D iio_priv(indio_dev); unsigned long clk_freq; unsigned long regval; u8 regval_bytes[4]; u16 freq_cmd; + u32 fout, addr; + int ret; =20 - clk_freq =3D clk_get_rate(st->mclk); + if (private > 1) + return -EINVAL; + + addr =3D (private =3D=3D 0) ? AD9832_FREQ0HM : AD9832_FREQ1HM; + + ret =3D kstrtou32(buf, 10, &fout); + if (ret) + return ret; =20 + clk_freq =3D clk_get_rate(st->mclk); if (!clk_freq || fout > (clk_freq / 2)) return -EINVAL; =20 + guard(mutex)(&st->lock); regval =3D ad9832_calc_freqreg(clk_freq, fout); put_unaligned_be32(regval, regval_bytes); =20 @@ -142,32 +170,102 @@ static int ad9832_write_frequency(struct ad9832_stat= e *st, FIELD_PREP(AD9832_DAT_MSK, regval_bytes[i])); } =20 - return spi_sync(st->spi, &st->freq_msg); + ret =3D spi_sync(st->spi, &st->freq_msg); + if (ret) + return ret; + + st->freq[private] =3D fout; + + return len; +} + +static ssize_t ad9832_read_frequency(struct iio_dev *indio_dev, + uintptr_t private, + struct iio_chan_spec const *chan, + char *buf) +{ + struct ad9832_state *st =3D iio_priv(indio_dev); + u32 val; + + if (private > 1) + return -EINVAL; + + guard(mutex)(&st->lock); + val =3D st->freq[private]; + + return sysfs_emit(buf, "%u\n", val); } =20 -static int ad9832_write_phase(struct ad9832_state *st, - unsigned long addr, unsigned long phase) +static const u32 ad9832_phase_addr[] =3D { + AD9832_PHASE0H, AD9832_PHASE1H, AD9832_PHASE2H, AD9832_PHASE3H +}; + +static ssize_t ad9832_write_phase(struct iio_dev *indio_dev, + uintptr_t private, + struct iio_chan_spec const *chan, + const char *buf, size_t len) { + struct ad9832_state *st =3D iio_priv(indio_dev); u8 phase_bytes[2]; u16 phase_cmd; + u32 phase_urad, phase; + int val, val2, ret; =20 - if (phase >=3D BIT(AD9832_PHASE_BITS)) + if (private >=3D ARRAY_SIZE(ad9832_phase_addr)) return -EINVAL; =20 - put_unaligned_be16(phase, phase_bytes); + ret =3D iio_str_to_fixpoint(buf, 100000, &val, &val2); + if (ret) + return ret; + + if (val < 0 || val2 < 0) + return -EINVAL; + + phase_urad =3D val * MICRO + val2; + if (phase_urad >=3D AD9832_2PI_URAD) + return -EINVAL; =20 + /* Convert microradians to 12-bit phase register value (0 to 4095) */ + phase =3D ((u64)phase_urad << AD9832_PHASE_BITS) / AD9832_2PI_URAD; + + guard(mutex)(&st->lock); + put_unaligned_be16(phase, phase_bytes); for (int i =3D 0; i < ARRAY_SIZE(phase_bytes); i++) { phase_cmd =3D (i % 2 =3D=3D 0) ? AD9832_CMD_PHA8BITSW : AD9832_CMD_PHA16= BITSW; =20 st->phase_data[i] =3D cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, phase_cmd) | - FIELD_PREP(AD9832_ADD_MSK, addr - i) | + FIELD_PREP(AD9832_ADD_MSK, ad9832_phase_addr[private] - i) | FIELD_PREP(AD9832_DAT_MSK, phase_bytes[i])); } =20 - return spi_sync(st->spi, &st->phase_msg); + ret =3D spi_sync(st->spi, &st->phase_msg); + if (ret) + return ret; + + st->phase[private] =3D phase; + + return len; } =20 -static ssize_t ad9832_write(struct device *dev, struct device_attribute *a= ttr, +static ssize_t ad9832_read_phase(struct iio_dev *indio_dev, + uintptr_t private, + struct iio_chan_spec const *chan, + char *buf) +{ + struct ad9832_state *st =3D iio_priv(indio_dev); + u32 phase_urad; + + if (private >=3D ARRAY_SIZE(ad9832_phase_addr)) + return -EINVAL; + + guard(mutex)(&st->lock); + phase_urad =3D ((u64)st->phase[private] * AD9832_2PI_URAD) >> AD9832_PHAS= E_BITS; + + return sysfs_emit(buf, "%u.%06u\n", phase_urad / (u32)MICRO, phase_urad %= (u32)MICRO); +} + +static ssize_t ad9832_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t len) { struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); @@ -181,25 +279,7 @@ static ssize_t ad9832_write(struct device *dev, struct= device_attribute *attr, return ret; =20 guard(mutex)(&st->lock); - switch ((u32)this_attr->address) { - case AD9832_FREQ0HM: - case AD9832_FREQ1HM: - ret =3D ad9832_write_frequency(st, this_attr->address, val); - return ret ?: len; - case AD9832_PHASE0H: - case AD9832_PHASE1H: - case AD9832_PHASE2H: - case AD9832_PHASE3H: - ret =3D ad9832_write_phase(st, this_attr->address, val); - return ret ?: len; - case AD9832_PINCTRL_EN: - st->ctrl_ss &=3D ~AD9832_SELSRC; - st->ctrl_ss |=3D FIELD_PREP(AD9832_SELSRC, val ? 0 : 1); - - st->data =3D cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_SYNCSELSR= C) | - st->ctrl_ss); - ret =3D spi_sync(st->spi, &st->msg); - return ret ?: len; + switch (this_attr->address) { case AD9832_FREQ_SYM: if (val !=3D 1 && val !=3D 0) return -EINVAL; @@ -209,7 +289,11 @@ static ssize_t ad9832_write(struct device *dev, struct= device_attribute *attr, st->data =3D cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_FPSELECT)= | st->ctrl_fp); ret =3D spi_sync(st->spi, &st->msg); - return ret ?: len; + if (ret) + return ret; + + st->freq_sym =3D val; + break; case AD9832_PHASE_SYM: if (val > 3) return -EINVAL; @@ -220,8 +304,15 @@ static ssize_t ad9832_write(struct device *dev, struct= device_attribute *attr, st->data =3D cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_FPSELECT)= | st->ctrl_fp); ret =3D spi_sync(st->spi, &st->msg); - return ret ?: len; + if (ret) + return ret; + + st->phase_sym =3D val; + break; case AD9832_OUTPUT_EN: + if (val !=3D 1 && val !=3D 0) + return -EINVAL; + if (val) st->ctrl_src &=3D ~(AD9832_RESET | AD9832_SLEEP | AD9832_CLR); else @@ -230,42 +321,111 @@ static ssize_t ad9832_write(struct device *dev, stru= ct device_attribute *attr, st->data =3D cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_SLEEPRESC= LR) | st->ctrl_src); ret =3D spi_sync(st->spi, &st->msg); - return ret ?: len; + if (ret) + return ret; + + st->output_en =3D val; + break; + case AD9832_PINCTRL_EN: + if (val !=3D 1 && val !=3D 0) + return -EINVAL; + + st->ctrl_ss &=3D ~AD9832_SELSRC; + st->ctrl_ss |=3D FIELD_PREP(AD9832_SELSRC, !val); + + st->data =3D cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, AD9832_CMD_SYNCSELSR= C) | + st->ctrl_ss); + ret =3D spi_sync(st->spi, &st->msg); + if (ret) + return ret; + + st->pinctrl_en =3D val; + break; default: return -ENODEV; } + + return len; } =20 -static IIO_DEVICE_ATTR(out_altvoltage0_frequency0, 0200, NULL, ad9832_writ= e, AD9832_FREQ0HM); -static IIO_DEVICE_ATTR(out_altvoltage0_frequency1, 0200, NULL, ad9832_writ= e, AD9832_FREQ1HM); +static ssize_t ad9832_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct ad9832_state *st =3D iio_priv(indio_dev); + struct iio_dev_attr *this_attr =3D to_iio_dev_attr(attr); =20 -static IIO_DEVICE_ATTR(out_altvoltage0_frequencysymbol, 0200, NULL, ad9832= _write, AD9832_FREQ_SYM); -static IIO_CONST_ATTR(out_altvoltage0_frequency_scale, "1"); /* 1Hz */ + guard(mutex)(&st->lock); + switch (this_attr->address) { + case AD9832_FREQ_SYM: + return sysfs_emit(buf, "%u\n", st->freq_sym); + case AD9832_PHASE_SYM: + return sysfs_emit(buf, "%u\n", st->phase_sym); + case AD9832_OUTPUT_EN: + return sysfs_emit(buf, "%u\n", st->output_en); + case AD9832_PINCTRL_EN: + return sysfs_emit(buf, "%u\n", st->pinctrl_en); + default: + return -ENODEV; + } +} =20 -static IIO_DEVICE_ATTR(out_altvoltage0_phase0, 0200, NULL, ad9832_write, A= D9832_PHASE0H); -static IIO_DEVICE_ATTR(out_altvoltage0_phase1, 0200, NULL, ad9832_write, A= D9832_PHASE1H); -static IIO_DEVICE_ATTR(out_altvoltage0_phase2, 0200, NULL, ad9832_write, A= D9832_PHASE2H); -static IIO_DEVICE_ATTR(out_altvoltage0_phase3, 0200, NULL, ad9832_write, A= D9832_PHASE3H); +#define AD9832_CHAN_FREQ(_name, _select) { \ + .name =3D _name, \ + .write =3D ad9832_write_frequency, \ + .read =3D ad9832_read_frequency, \ + .private =3D _select, \ + .shared =3D IIO_SEPARATE, \ +} + +#define AD9832_CHAN_PHASE(_name, _select) { \ + .name =3D _name, \ + .write =3D ad9832_write_phase, \ + .read =3D ad9832_read_phase, \ + .private =3D _select, \ + .shared =3D IIO_SEPARATE, \ +} =20 -static IIO_DEVICE_ATTR(out_altvoltage0_phasesymbol, 0200, NULL, ad9832_wri= te, AD9832_PHASE_SYM); -static IIO_CONST_ATTR(out_altvoltage0_phase_scale, "0.0015339808"); /* 2PI= /2^12 rad */ +static const struct iio_chan_spec_ext_info ad9832_ext_info[] =3D { + AD9832_CHAN_FREQ("frequency0", 0), + AD9832_CHAN_FREQ("frequency1", 1), + AD9832_CHAN_PHASE("phase0", 0), + AD9832_CHAN_PHASE("phase1", 1), + AD9832_CHAN_PHASE("phase2", 2), + AD9832_CHAN_PHASE("phase3", 3), + { } +}; =20 -static IIO_DEVICE_ATTR(out_altvoltage0_pincontrol_en, 0200, NULL, ad9832_w= rite, AD9832_PINCTRL_EN); -static IIO_DEVICE_ATTR(out_altvoltage0_out_enable, 0200, NULL, ad9832_writ= e, AD9832_OUTPUT_EN); +static const struct iio_chan_spec ad9832_channels[] =3D { + { + .type =3D IIO_ALTCURRENT, + .output =3D 1, + .indexed =3D 1, + .channel =3D 0, + .ext_info =3D ad9832_ext_info, + }, +}; + +static IIO_DEVICE_ATTR(out_altcurrent0_frequency_symbol, 0644, + ad9832_show, ad9832_store, AD9832_FREQ_SYM); +static IIO_DEVICE_ATTR(out_altcurrent0_phase_symbol, 0644, + ad9832_show, ad9832_store, AD9832_PHASE_SYM); +static IIO_DEVICE_ATTR(out_altcurrent0_enable, 0644, + ad9832_show, ad9832_store, AD9832_OUTPUT_EN); + +/* + * TODO: Convert to DT property when graduating from staging. + * Pin control configuration depends on hardware wiring. + */ +static IIO_DEVICE_ATTR(out_altcurrent0_pincontrol_en, 0644, + ad9832_show, ad9832_store, AD9832_PINCTRL_EN); =20 static struct attribute *ad9832_attributes[] =3D { - &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr, - &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_phase2.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_phase3.dev_attr.attr, - &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr, - &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr, + &iio_dev_attr_out_altcurrent0_frequency_symbol.dev_attr.attr, + &iio_dev_attr_out_altcurrent0_phase_symbol.dev_attr.attr, + &iio_dev_attr_out_altcurrent0_enable.dev_attr.attr, + &iio_dev_attr_out_altcurrent0_pincontrol_en.dev_attr.attr, NULL, }; =20 @@ -310,6 +470,8 @@ static int ad9832_probe(struct spi_device *spi) indio_dev->name =3D spi_get_device_id(spi)->name; indio_dev->info =3D &ad9832_info; indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->channels =3D ad9832_channels; + indio_dev->num_channels =3D ARRAY_SIZE(ad9832_channels); =20 /* Setup default messages */ st->xfer.tx_buf =3D &st->data; --=20 2.43.0