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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Dec 2025 08:33:59.5881 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7969cad7-9983-48d1-10ae-08de477e2dff X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001506.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR10MB5120 Content-Type: text/plain; charset="utf-8" From: Jai Luthra Each CSI2 stream can be multiplexed into 4 independent streams, each identified by its virtual channel number and data type. The incoming data from these streams can be filtered on the basis of either the virtual channel or the data type. To capture this multiplexed stream, the application needs to tell the driver how it wants to route the data. It needs to specify which context should process which stream. This is done via the new routing APIs. Add ioctls to accept routing information from the application and save that in the driver. This can be used when starting streaming on a context to determine which route and consequently which virtual channel it should process. De-assert the pixel interface reset on first start_streaming() and assert it on the last stop_streaming(). Reviewed-by: Yemike Abhilash Chandra Co-developed-by: Pratyush Yadav Signed-off-by: Pratyush Yadav Signed-off-by: Jai Luthra Co-developed-by: Rishikesh Donadkar Signed-off-by: Rishikesh Donadkar --- .../platform/ti/j721e-csi2rx/j721e-csi2rx.c | 259 +++++++++++++----- 1 file changed, 189 insertions(+), 70 deletions(-) diff --git a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c b/driver= s/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c index 6f9f34aa26f1b..4a063364f893e 100644 --- a/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c +++ b/drivers/media/platform/ti/j721e-csi2rx/j721e-csi2rx.c @@ -137,6 +137,7 @@ struct ti_csi2rx_dev { dma_addr_t paddr; size_t len; } drain; + bool vc_cached; }; =20 static inline struct ti_csi2rx_dev *to_csi2rx_dev(struct v4l2_subdev *sd) @@ -144,17 +145,6 @@ static inline struct ti_csi2rx_dev *to_csi2rx_dev(stru= ct v4l2_subdev *sd) return container_of(sd, struct ti_csi2rx_dev, subdev); } =20 -static const struct v4l2_mbus_framefmt ti_csi2rx_default_fmt =3D { - .width =3D 640, - .height =3D 480, - .code =3D MEDIA_BUS_FMT_UYVY8_1X16, - .field =3D V4L2_FIELD_NONE, - .colorspace =3D V4L2_COLORSPACE_SRGB, - .ycbcr_enc =3D V4L2_YCBCR_ENC_601, - .quantization =3D V4L2_QUANTIZATION_LIM_RANGE, - .xfer_func =3D V4L2_XFER_FUNC_SRGB, -}; - static const struct ti_csi2rx_fmt ti_csi2rx_formats[] =3D { { .fourcc =3D V4L2_PIX_FMT_YUYV, @@ -567,8 +557,10 @@ static void ti_csi2rx_setup_shim(struct ti_csi2rx_ctx = *ctx) fmt =3D find_format_by_fourcc(ctx->v_fmt.fmt.pix.pixelformat); =20 /* De-assert the pixel interface reset. */ - reg =3D SHIM_CNTL_PIX_RST; - writel(reg, csi->shim + SHIM_CNTL); + if (!csi->enable_count) { + reg =3D SHIM_CNTL_PIX_RST; + writel(reg, csi->shim + SHIM_CNTL); + } =20 /* Negotiate pixel count from the source */ ti_csi2rx_request_max_ppc(csi); @@ -889,29 +881,69 @@ static void ti_csi2rx_buffer_queue(struct vb2_buffer = *vb) } } =20 +static int ti_csi2rx_get_stream(struct ti_csi2rx_ctx *ctx) +{ + struct ti_csi2rx_dev *csi =3D ctx->csi; + struct media_pad *pad; + struct v4l2_subdev_state *state; + struct v4l2_subdev_route *r; + + /* Get the source pad connected to this ctx */ + pad =3D media_entity_remote_source_pad_unique(ctx->pad.entity); + if (!pad) { + dev_err(csi->dev, "No pad connected to ctx %d\n", ctx->idx); + return -ENODEV; + } + + state =3D v4l2_subdev_get_locked_active_state(&csi->subdev); + + for_each_active_route(&state->routing, r) { + if (r->source_pad =3D=3D pad->index) { + ctx->stream =3D r->sink_stream; + return 0; + } + } + + /* No route found for this ctx */ + return -ENODEV; +} + static int ti_csi2rx_get_vc_and_dt(struct ti_csi2rx_ctx *ctx) { struct ti_csi2rx_dev *csi =3D ctx->csi; + struct ti_csi2rx_ctx *curr_ctx; struct v4l2_mbus_frame_desc fd; - struct media_pad *pad; - int ret, i; + struct media_pad *source_pad; + int ret; + unsigned int i, j; =20 - pad =3D media_entity_remote_pad_unique(&csi->subdev.entity, MEDIA_PAD_FL_= SOURCE); - if (!pad) + /* Get the frame desc form source */ + source_pad =3D media_entity_remote_pad_unique(&csi->subdev.entity, MEDIA_= PAD_FL_SOURCE); + if (!source_pad) return -ENODEV; =20 - ret =3D v4l2_subdev_call(csi->source, pad, get_frame_desc, pad->index, &f= d); + ret =3D v4l2_subdev_call(csi->source, pad, get_frame_desc, source_pad->in= dex, &fd); if (ret) return ret; =20 if (fd.type !=3D V4L2_MBUS_FRAME_DESC_TYPE_CSI2) return -EINVAL; =20 - for (i =3D 0; i < fd.num_entries; i++) { - if (ctx->stream =3D=3D fd.entry[i].stream) { - ctx->vc =3D fd.entry[i].bus.csi2.vc; - ctx->dt =3D fd.entry[i].bus.csi2.dt; - } + for (i =3D 0; i < csi->num_ctx; i++) { + curr_ctx =3D &csi->ctx[i]; + + /* Capture VC 0 by default */ + curr_ctx->vc =3D 0; + + ret =3D ti_csi2rx_get_stream(curr_ctx); + if (ret) + continue; + + for (j =3D 0; j < fd.num_entries; j++) + if (curr_ctx->stream =3D=3D fd.entry[j].stream) { + curr_ctx->vc =3D fd.entry[j].bus.csi2.vc; + curr_ctx->dt =3D fd.entry[j].bus.csi2.dt; + } } =20 return 0; @@ -922,8 +954,6 @@ static int ti_csi2rx_start_streaming(struct vb2_queue *= vq, unsigned int count) struct ti_csi2rx_ctx *ctx =3D vb2_get_drv_priv(vq); struct ti_csi2rx_dev *csi =3D ctx->csi; struct ti_csi2rx_dma *dma =3D &ctx->dma; - struct ti_csi2rx_buffer *buf; - const struct ti_csi2rx_fmt *fmt; unsigned long flags; int ret =3D 0; =20 @@ -938,35 +968,9 @@ static int ti_csi2rx_start_streaming(struct vb2_queue = *vq, unsigned int count) if (ret) goto err; =20 - ret =3D ti_csi2rx_get_vc_and_dt(ctx); - if (ret =3D=3D -ENOIOCTLCMD) { - ctx->vc =3D 0; - fmt =3D find_format_by_fourcc(ctx->v_fmt.fmt.pix.pixelformat); - ctx->dt =3D fmt->csi_dt; - } else if (ret < 0) { - goto err; - } - - ti_csi2rx_setup_shim(ctx); - - ctx->sequence =3D 0; - - spin_lock_irqsave(&dma->lock, flags); - buf =3D list_entry(dma->queue.next, struct ti_csi2rx_buffer, list); - - ret =3D ti_csi2rx_start_dma(ctx, buf); - if (ret) { - dev_err(csi->dev, "Failed to start DMA: %d\n", ret); - spin_unlock_irqrestore(&dma->lock, flags); - goto err_pipeline; - } - - list_move_tail(&buf->list, &dma->submitted); - dma->state =3D TI_CSI2RX_DMA_ACTIVE; - spin_unlock_irqrestore(&dma->lock, flags); - + /* Start stream 0, we don't allow multiple streams on the source pad */ ret =3D v4l2_subdev_enable_streams(&csi->subdev, - TI_CSI2RX_PAD_FIRST_SOURCE, + TI_CSI2RX_PAD_FIRST_SOURCE + ctx->idx, BIT_U64(0)); if (ret) goto err_dma; @@ -975,7 +979,6 @@ static int ti_csi2rx_start_streaming(struct vb2_queue *= vq, unsigned int count) =20 err_dma: ti_csi2rx_stop_dma(ctx); -err_pipeline: video_device_pipeline_stop(&ctx->vdev); writel(0, csi->shim + SHIM_CNTL); writel(0, csi->shim + SHIM_DMACNTX(ctx->idx)); @@ -990,17 +993,26 @@ static void ti_csi2rx_stop_streaming(struct vb2_queue= *vq) struct ti_csi2rx_dev *csi =3D ctx->csi; int ret; =20 - video_device_pipeline_stop(&ctx->vdev); + mutex_lock(&csi->mutex); =20 - writel(0, csi->shim + SHIM_CNTL); writel(0, csi->shim + SHIM_DMACNTX(ctx->idx)); =20 + /* assert pixel reset to prevent stale data */ + if (csi->enable_count =3D=3D 1) { + writel(0, csi->shim + SHIM_CNTL); + csi->vc_cached =3D false; + } + + video_device_pipeline_stop(&ctx->vdev); + ret =3D v4l2_subdev_disable_streams(&csi->subdev, - TI_CSI2RX_PAD_FIRST_SOURCE, + TI_CSI2RX_PAD_FIRST_SOURCE + ctx->idx, BIT_U64(0)); if (ret) dev_err(csi->dev, "Failed to stop subdev stream\n"); =20 + mutex_unlock(&csi->mutex); + ti_csi2rx_stop_dma(ctx); ti_csi2rx_cleanup_buffers(ctx, VB2_BUF_STATE_ERROR); } @@ -1043,25 +1055,84 @@ static int ti_csi2rx_sd_set_fmt(struct v4l2_subdev = *sd, fmt =3D v4l2_subdev_state_get_format(state, format->pad, format->stream); *fmt =3D format->format; =20 - fmt =3D v4l2_subdev_state_get_format(state, TI_CSI2RX_PAD_FIRST_SOURCE, - format->stream); + fmt =3D v4l2_subdev_state_get_opposite_stream_format(state, format->pad, + format->stream); + if (!fmt) + return -EINVAL; + *fmt =3D format->format; =20 return 0; } =20 -static int ti_csi2rx_sd_init_state(struct v4l2_subdev *sd, - struct v4l2_subdev_state *state) +static int _ti_csi2rx_sd_set_routing(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + struct v4l2_subdev_krouting *routing) { - struct v4l2_mbus_framefmt *fmt; + int ret; + + static const struct v4l2_mbus_framefmt format =3D { + .width =3D 640, + .height =3D 480, + .code =3D MEDIA_BUS_FMT_UYVY8_1X16, + .field =3D V4L2_FIELD_NONE, + .colorspace =3D V4L2_COLORSPACE_SRGB, + .ycbcr_enc =3D V4L2_YCBCR_ENC_601, + .quantization =3D V4L2_QUANTIZATION_LIM_RANGE, + .xfer_func =3D V4L2_XFER_FUNC_SRGB, + }; =20 - fmt =3D v4l2_subdev_state_get_format(state, TI_CSI2RX_PAD_SINK); - *fmt =3D ti_csi2rx_default_fmt; + ret =3D v4l2_subdev_routing_validate(sd, routing, + V4L2_SUBDEV_ROUTING_ONLY_1_TO_1 | + V4L2_SUBDEV_ROUTING_NO_SOURCE_MULTIPLEXING); =20 - fmt =3D v4l2_subdev_state_get_format(state, TI_CSI2RX_PAD_FIRST_SOURCE); - *fmt =3D ti_csi2rx_default_fmt; + if (ret) + return ret; =20 - return 0; + /* Only stream ID 0 allowed on source pads */ + for (unsigned int i =3D 0; i < routing->num_routes; ++i) { + const struct v4l2_subdev_route *route =3D &routing->routes[i]; + + if (route->source_stream !=3D 0) + return -EINVAL; + } + + ret =3D v4l2_subdev_set_routing_with_fmt(sd, state, routing, &format); + + return ret; +} + +static int ti_csi2rx_sd_set_routing(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + enum v4l2_subdev_format_whence which, + struct v4l2_subdev_krouting *routing) +{ + struct ti_csi2rx_dev *csi =3D to_csi2rx_dev(sd); + + if (csi->enable_count > 0) + return -EBUSY; + + return _ti_csi2rx_sd_set_routing(sd, state, routing); +} + +static int ti_csi2rx_sd_init_state(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state) +{ + struct v4l2_subdev_route routes[] =3D { { + .sink_pad =3D 0, + .sink_stream =3D 0, + .source_pad =3D TI_CSI2RX_PAD_FIRST_SOURCE, + .source_stream =3D 0, + .flags =3D V4L2_SUBDEV_ROUTE_FL_ACTIVE, + } }; + + struct v4l2_subdev_krouting routing =3D { + .num_routes =3D 1, + .routes =3D routes, + }; + + /* Initialize routing to single route to the fist source pad */ + return _ti_csi2rx_sd_set_routing(sd, state, &routing); } =20 static int ti_csi2rx_sd_enable_streams(struct v4l2_subdev *sd, @@ -1069,15 +1140,58 @@ static int ti_csi2rx_sd_enable_streams(struct v4l2_= subdev *sd, u32 pad, u64 streams_mask) { struct ti_csi2rx_dev *csi =3D to_csi2rx_dev(sd); + struct ti_csi2rx_ctx *ctx =3D &csi->ctx[pad - TI_CSI2RX_PAD_FIRST_SOURCE]; + struct ti_csi2rx_dma *dma =3D &ctx->dma; struct media_pad *remote_pad; + struct ti_csi2rx_buffer *buf; + const struct ti_csi2rx_fmt *fmt; + unsigned long flags; + u64 sink_streams; int ret =3D 0; =20 + ret =3D ti_csi2rx_get_stream(ctx); + if (ret) + return ret; + + /* Get the VC and DT for all enabled ctx on first stream start */ + if (!csi->vc_cached) { + ret =3D ti_csi2rx_get_vc_and_dt(ctx); + if (ret =3D=3D -ENOIOCTLCMD) { + ctx->vc =3D 0; + fmt =3D find_format_by_fourcc(ctx->v_fmt.fmt.pix.pixelformat); + ctx->dt =3D fmt->csi_dt; + } else if (ret < 0) { + return ret; + } + csi->vc_cached =3D true; + } + + ti_csi2rx_setup_shim(ctx); + ctx->sequence =3D 0; + + spin_lock_irqsave(&dma->lock, flags); + buf =3D list_entry(dma->queue.next, struct ti_csi2rx_buffer, list); + + ret =3D ti_csi2rx_start_dma(ctx, buf); + if (ret) { + dev_err(csi->dev, "Failed to start DMA: %d\n", ret); + spin_unlock_irqrestore(&dma->lock, flags); + return ret; + } + + list_move_tail(&buf->list, &dma->submitted); + dma->state =3D TI_CSI2RX_DMA_ACTIVE; + spin_unlock_irqrestore(&dma->lock, flags); + remote_pad =3D media_entity_remote_source_pad_unique(&csi->subdev.entity); if (!remote_pad) return -ENODEV; + sink_streams =3D v4l2_subdev_state_xlate_streams(state, pad, + TI_CSI2RX_PAD_SINK, + &streams_mask); =20 ret =3D v4l2_subdev_enable_streams(csi->source, remote_pad->index, - BIT_U64(0)); + sink_streams); if (ret) return ret; =20 @@ -1092,17 +1206,21 @@ static int ti_csi2rx_sd_disable_streams(struct v4l2= _subdev *sd, { struct ti_csi2rx_dev *csi =3D to_csi2rx_dev(sd); struct media_pad *remote_pad; + u64 sink_streams; int ret =3D 0; =20 remote_pad =3D media_entity_remote_source_pad_unique(&csi->subdev.entity); if (!remote_pad) return -ENODEV; + sink_streams =3D v4l2_subdev_state_xlate_streams(state, pad, + TI_CSI2RX_PAD_SINK, + &streams_mask); =20 if (csi->enable_count =3D=3D 0) return -EINVAL; =20 ret =3D v4l2_subdev_disable_streams(csi->source, remote_pad->index, - BIT_U64(0)); + sink_streams); if (!ret) --csi->enable_count; =20 @@ -1111,6 +1229,7 @@ static int ti_csi2rx_sd_disable_streams(struct v4l2_s= ubdev *sd, =20 static const struct v4l2_subdev_pad_ops ti_csi2rx_subdev_pad_ops =3D { .enum_mbus_code =3D ti_csi2rx_enum_mbus_code, + .set_routing =3D ti_csi2rx_sd_set_routing, .get_fmt =3D v4l2_subdev_get_fmt, .set_fmt =3D ti_csi2rx_sd_set_fmt, .enable_streams =3D ti_csi2rx_sd_enable_streams, @@ -1289,7 +1408,7 @@ static int ti_csi2rx_v4l2_init(struct ti_csi2rx_dev *= csi) v4l2_subdev_init(sd, &ti_csi2rx_subdev_ops); sd->internal_ops =3D &ti_csi2rx_internal_ops; sd->entity.function =3D MEDIA_ENT_F_VID_IF_BRIDGE; - sd->flags =3D V4L2_SUBDEV_FL_HAS_DEVNODE; + sd->flags =3D V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_STREAMS; strscpy(sd->name, dev_name(csi->dev), sizeof(sd->name)); sd->dev =3D csi->dev; sd->entity.ops =3D &ti_csi2rx_subdev_entity_ops; --=20 2.34.1