From nobody Mon Feb 9 13:02:53 2026 Received: from out-180.mta0.migadu.com (out-180.mta0.migadu.com [91.218.175.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A72A2BE7AA for ; Tue, 30 Dec 2025 01:34:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767058470; cv=none; b=YBgmGZNnFLO86koG1wfa3YUC7JRKCHTeZLubZkfyqGk/l3TeILJfDjfdc9a78n7+RrqQavLSa1eW735/KpvNYGjJROwr8qbvqKWpr3M8j6vhog2H+Nv8MUI6CiwB6KkebZwbb8T7Py94ZCFM55c1BpSdKP90EnAA0GRPzpU/A3E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767058470; c=relaxed/simple; bh=P+qofRHgKI9mEvf/M2+uRxs0vPJHcW9djs3JSnJOuKU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jo6UvRkeEzQu/S4eifuEBx4FNuaQedVOduu6DEr0/wo5ejlcAJdp8vK6WHEQXD4WCkM9lFhHHLtGJYWRPUfCQWiD2ObAYbwSHb/3/PhLTUEHfNHxG4SeA8cbXvPWBNwOrcyGqBR/HEaMcGtkxyysn1uV4UNFwC4fxKUXqOT5X0g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=gphrDY/F; arc=none smtp.client-ip=91.218.175.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="gphrDY/F" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1767058467; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9e1GeNzrkliZLlZL213Exbk9DDZDpepWNXJsRZoIj9M=; b=gphrDY/FcUrE58B9c45vTjqkJs7oG9bE7AphEUINY43mcv/MYDf+VRTSSAbQS/4Msq5m+y xGhexPMAhU52AGrBXiNOnq8nQDU2wA2ZOcqANi6MQqLCOTk01Q3LHqUquvMG8PahIE6Wmb itYiC6Zhz/ibDnuvtlLjrg9/LwmlBYA= From: George Guo To: hengqi.chen@gmail.com Cc: chenhuacai@kernel.org, dongtai.guo@linux.dev, guodongtai@kylinos.cn, kernel@xen0n.name, lianyangyang@kylinos.cn, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, r@hev.cc, xry111@xry111.site Subject: [PATCH v7 loongarch-next 2/4] LoongArch: Add 128-bit atomic cmpxchg support Date: Tue, 30 Dec 2025 09:34:15 +0800 Message-ID: <20251230013417.37393-3-dongtai.guo@linux.dev> In-Reply-To: <20251230013417.37393-1-dongtai.guo@linux.dev> References: <20251230013417.37393-1-dongtai.guo@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" From: George Guo Implement 128-bit atomic compare-and-exchange using LoongArch's LL.D/SC.Q instructions. At the same time, fix BPF scheduler test failures (scx_central scx_qmap) caused by kmalloc_nolock_noprof returning NULL due to missing 128-bit atomics. The NULL returns led to -ENOMEM errors during scheduler initialization, causing test cases to fail. Verified by testing with the scx_qmap scheduler (located in tools/sched_ext/). Building with `make` and running ./tools/sched_ext/build/bin/scx_qmap. Signed-off-by: George Guo --- arch/loongarch/include/asm/cmpxchg.h | 47 ++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/loongarch/include/asm/cmpxchg.h b/arch/loongarch/include/= asm/cmpxchg.h index 0494c2ab553e..61ce6a0889f0 100644 --- a/arch/loongarch/include/asm/cmpxchg.h +++ b/arch/loongarch/include/asm/cmpxchg.h @@ -137,6 +137,44 @@ __arch_xchg(volatile void *ptr, unsigned long x, int s= ize) __ret; \ }) =20 +union __u128_halves { + u128 full; + struct { + u64 low; + u64 high; + }; +}; + +#define __cmpxchg128_asm(ptr, old, new) \ +({ \ + union __u128_halves __old, __new, __ret; \ + volatile u64 *__ptr =3D (volatile u64 *)(ptr); \ + \ + __old.full =3D (old); \ + __new.full =3D (new); \ + \ + __asm__ __volatile__( \ + "1: ll.d %0, %3 # 128-bit cmpxchg low \n" \ + __WEAK_LLSC_MB \ + " ld.d %1, %4 # 128-bit cmpxchg high \n" \ + " bne %0, %z5, 2f \n" \ + " bne %1, %z6, 2f \n" \ + " move $t0, %z7 \n" \ + " move $t1, %z8 \n" \ + " sc.q $t0, $t1, %2 \n" \ + " beqz $t0, 1b \n" \ + "2: \n" \ + __WEAK_LLSC_MB \ + : "=3D&r" (__ret.low), "=3D&r" (__ret.high) \ + : "r" (__ptr), \ + "ZC" (__ptr[0]), "m" (__ptr[1]), \ + "Jr" (__old.low), "Jr" (__old.high), \ + "Jr" (__new.low), "Jr" (__new.high) \ + : "t0", "t1", "memory"); \ + \ + __ret.full; \ +}) + static inline unsigned int __cmpxchg_small(volatile void *ptr, unsigned in= t old, unsigned int new, unsigned int size) { @@ -224,6 +262,15 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsig= ned long new, unsigned int __res; \ }) =20 +/* cmpxchg128 */ +#define system_has_cmpxchg128() 1 + +#define arch_cmpxchg128(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 16); \ + __cmpxchg128_asm(ptr, o, n); \ +}) + #ifdef CONFIG_64BIT #define arch_cmpxchg64_local(ptr, o, n) \ ({ \ --=20 2.49.0