From nobody Sun Feb 8 20:28:24 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A8242E88BD; Tue, 30 Dec 2025 05:58:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767074292; cv=none; b=V+e8UpPSXBxaYxPzNLzYH7rd87Inxvo/sNQIKX72jeMMlmzwllyZQEkE9GdPxr+W4W4v57uZlwPwjr+7tcEo5ODk2nRxzclTyRj9K6xj3tAx6U/VSb4lVnx4XLpKELpjINJwqLWCZZIzFS5RtQagfQDEow5Ji3snVlyn70lH308= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767074292; c=relaxed/simple; bh=nSo81XDH3g+0IhsQkmlg4apJPpZay88RgQZ5h1VpL2k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Ph3Bjs3jXweQSpGo1MYLjX0pZmTKr2xBpMMlZxAFdY8jj+MoS2QuyH2Os/ZRGEwk4loQeMTx7YyP8UazMA0OzYzXUqiPQphKztwN/8qzeWL5uCGziyiViurEsIdcD5fu+TziQsfbAcvZHPtPKhYFKe2D8AdAQxvZetOAQaW1MxU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 30 Dec 2025 13:57:59 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 30 Dec 2025 13:57:59 +0800 From: Jacky Chou Date: Tue, 30 Dec 2025 13:57:58 +0800 Subject: [PATCH v8 1/4] dt-bindings: phy: aspeed: Add ASPEED PCIe PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20251230-upstream_pcie_rc-v8-1-03598cdd80cd@aspeedtech.com> References: <20251230-upstream_pcie_rc-v8-0-03598cdd80cd@aspeedtech.com> In-Reply-To: <20251230-upstream_pcie_rc-v8-0-03598cdd80cd@aspeedtech.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" CC: , , , , , Jacky Chou X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767074279; l=1554; i=jacky_chou@aspeedtech.com; s=20251031; h=from:subject:message-id; bh=nSo81XDH3g+0IhsQkmlg4apJPpZay88RgQZ5h1VpL2k=; b=f38D1olY/5adTxUTnUpE5ehquyCwz8v7FP9anlrRZZy+eV4sRP0S7wgboM54eqe9QiPWpZsmm R3V1VE+LI3aAQunRZiLgk7MgA5lYeYwkZqoPc2UWW+WSo0Zryxj45Bx X-Developer-Key: i=jacky_chou@aspeedtech.com; a=ed25519; pk=8XBx7KFM1drEsfCXTH9QC2lbMlGU4XwJTA6Jt9Mabdo= Introduce device-binding for ASPEED AST2600/2700 PCIe PHY. The PCIe PHY is used for PCIe RC to configure as RC mode. Signed-off-by: Jacky Chou Reviewed-by: Rob Herring (Arm) --- .../bindings/phy/aspeed,ast2600-pcie-phy.yaml | 42 ++++++++++++++++++= ++++ 1 file changed, 42 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.= yaml b/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml new file mode 100644 index 000000000000..71a5cd91fb3f --- /dev/null +++ b/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/aspeed,ast2600-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED PCIe PHY + +maintainers: + - Jacky Chou + +description: + The ASPEED PCIe PHY provides the physical layer functionality for PCIe + controllers in the SoC. + +properties: + compatible: + items: + - enum: + - aspeed,ast2600-pcie-phy + - aspeed,ast2700-pcie-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@1e6ed200 { + compatible =3D "aspeed,ast2600-pcie-phy"; + reg =3D <0x1e6ed200 0x100>; + #phy-cells =3D <0>; + }; --=20 2.34.1 From nobody Sun Feb 8 20:28:24 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66C8B2F1FE7; Tue, 30 Dec 2025 05:58:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767074294; cv=none; b=qofCJyldj7wZ2Gnz46Uad8mBFBURamVl/ymWcXV2xxPxpyqWM/vqDR5awd40FJzeJjRv0EaaOJwGJpzFK8xsyyah+75L8EHyMVvlnik2+Okhq54SdlgPpMbGN4Dk3FxJ9/Bcl0T0GIkrp2Vd8VLfxJK9AI7W6Sm+Tkqjidv5Bi4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767074294; c=relaxed/simple; bh=WucACgBEVr41rzAvQJGKyFXe0ozjjV/dKi/l/xqeoAY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=vFNFjHBkiFj584a85peJt9MmgE2aOzpQeIwldFdT8V6Y+EcCPvlDb2OPWv153LH4VRVe9tN5DHy5aJZckXTBVoXEa6DCfw0mhA2b8Y7Nq9OWF10ektbsOPFIC/3kvx8udrRptxK02KO+ii+t0BsnNhREG/2rLtPZvnadiZ/iACU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 30 Dec 2025 13:57:59 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 30 Dec 2025 13:57:59 +0800 From: Jacky Chou Date: Tue, 30 Dec 2025 13:57:59 +0800 Subject: [PATCH v8 2/4] ARM: dts: aspeed-g6: Add PCIe RC and PCIe PHY node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20251230-upstream_pcie_rc-v8-2-03598cdd80cd@aspeedtech.com> References: <20251230-upstream_pcie_rc-v8-0-03598cdd80cd@aspeedtech.com> In-Reply-To: <20251230-upstream_pcie_rc-v8-0-03598cdd80cd@aspeedtech.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" CC: , , , , , Jacky Chou X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767074279; l=2703; i=jacky_chou@aspeedtech.com; s=20251031; h=from:subject:message-id; bh=WucACgBEVr41rzAvQJGKyFXe0ozjjV/dKi/l/xqeoAY=; b=kMjFtp+Py35zDp/DX+PpOXplj8HWq9l1/yvPv0El7FhbP40YOMNnVlm6AOBjZ5NvFv5xxR/uu d191xsJz2QIBSerQUXnCo6ylSCWgMgxAhJ451I6vNVOSCfWAvQyC16s X-Developer-Key: i=jacky_chou@aspeedtech.com; a=ed25519; pk=8XBx7KFM1drEsfCXTH9QC2lbMlGU4XwJTA6Jt9Mabdo= The AST2600 has one PCIe RC and add the PCIe PHY for RC. And add pinctrl support for PCIe RC PERST#. Signed-off-by: Jacky Chou --- arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi | 5 +++ arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 53 +++++++++++++++++++++= ++++ 2 files changed, 58 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi b/arch/arm/boo= t/dts/aspeed/aspeed-g6-pinctrl.dtsi index e87c4b58994a..d46f2047135c 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi @@ -2,6 +2,11 @@ // Copyright 2019 IBM Corp. =20 &pinctrl { + pinctrl_pcierc1_default: pcierc1-default { + function =3D "PCIERC1"; + groups =3D "PCIERC1"; + }; + pinctrl_adc0_default: adc0_default { function =3D "ADC0"; groups =3D "ADC0"; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/as= peed/aspeed-g6.dtsi index f8662c8ac089..dde8f87db2e3 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -379,6 +379,59 @@ rng: hwrng@1e6e2524 { quality =3D <100>; }; =20 + pcie_phy1: phy@1e6ed200 { + compatible =3D "aspeed,ast2600-pcie-phy"; + reg =3D <0x1e6ed200 0x100>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + pcie0: pcie@1e770000 { + compatible =3D "aspeed,ast2600-pcie"; + device_type =3D "pci"; + reg =3D <0x1e770000 0x100>; + #address-cells =3D <3>; + #size-cells =3D <2>; + interrupts =3D ; + bus-range =3D <0x00 0xff>; + + ranges =3D <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000 + 0x02000000 0x0 0x60000000 0x60000000 0x0 0x20000000>; + + status =3D "disabled"; + + resets =3D <&syscon ASPEED_RESET_H2X>; + reset-names =3D "h2x"; + + #interrupt-cells =3D <1>; + msi-controller; + + aspeed,ahbc =3D <&ahbc>; + + interrupt-controller; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie0 0>, + <0 0 0 2 &pcie0 1>, + <0 0 0 3 &pcie0 2>, + <0 0 0 4 &pcie0 3>; + + pcie@8,0 { + compatible =3D "pciclass,0604"; + reg =3D <0x00004000 0 0 0 0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + device_type =3D "pci"; + resets =3D <&syscon ASPEED_RESET_PCIE_RC_O>; + reset-names =3D "perst"; + clocks =3D <&syscon ASPEED_CLK_GATE_BCLK>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pcierc1_default>; + phys =3D <&pcie_phy1>; + ranges; + }; + }; + gfx: display@1e6e6000 { compatible =3D "aspeed,ast2600-gfx", "syscon"; reg =3D <0x1e6e6000 0x1000>; --=20 2.34.1 From nobody Sun Feb 8 20:28:24 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DA722E6CC7; Tue, 30 Dec 2025 05:58:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767074298; cv=none; b=lnCQY1Sjdh5wcGjzP0HeFvpUV0UKZ9qGoop5/WqnKgP3D73aKMw37g5iBkZ7/bkCfzouPVpnliFHVSOyOU/3OmEESPCrskJeWaLWHVbq7FxwMysiWpAXE3Hro13iAiXWkeLynedQqgtV2ERjn2t3bG6bCqlDSnuxDZxP7uZGa+8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767074298; 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Tue, 30 Dec 2025 13:57:59 +0800 From: Jacky Chou Date: Tue, 30 Dec 2025 13:58:00 +0800 Subject: [PATCH v8 3/4] phy: aspeed: Add ASPEED PCIe PHY driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20251230-upstream_pcie_rc-v8-3-03598cdd80cd@aspeedtech.com> References: <20251230-upstream_pcie_rc-v8-0-03598cdd80cd@aspeedtech.com> In-Reply-To: <20251230-upstream_pcie_rc-v8-0-03598cdd80cd@aspeedtech.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" CC: , , , , , Jacky Chou X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767074279; l=7886; i=jacky_chou@aspeedtech.com; s=20251031; h=from:subject:message-id; bh=iuA+GjJ84VtsIS3gDieMnU9uSG5jEHnAHxGjEw3iUOE=; b=o5sKUQF6StNa1Y/EZ3wjlXgfAydS8Nbjq1hm1Q/WPKrPB1HAXu6V/x4tqkzykbXJVOcWMqx9z boWx/EyECBxCCpoV+u8gWA1OdbEK0jkhsJlH5bKcYmdTzDt1JdohA+t X-Developer-Key: i=jacky_chou@aspeedtech.com; a=ed25519; pk=8XBx7KFM1drEsfCXTH9QC2lbMlGU4XwJTA6Jt9Mabdo= Introduce support for Aspeed PCIe PHY controller available in AST2600/2700. Signed-off-by: Jacky Chou --- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/aspeed/Kconfig | 14 +++ drivers/phy/aspeed/Makefile | 2 + drivers/phy/aspeed/phy-aspeed-pcie.c | 194 +++++++++++++++++++++++++++++++= ++++ 5 files changed, 212 insertions(+) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 678dd0452f0a..f6a8f06fd244 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -103,6 +103,7 @@ config PHY_NXP_PTN3222 =20 source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" +source "drivers/phy/aspeed/Kconfig" source "drivers/phy/broadcom/Kconfig" source "drivers/phy/cadence/Kconfig" source "drivers/phy/freescale/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index bfb27fb5a494..18990c87dfb0 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PHY_AIROHA_PCIE) +=3D phy-airoha-pcie.o obj-$(CONFIG_PHY_NXP_PTN3222) +=3D phy-nxp-ptn3222.o obj-y +=3D allwinner/ \ amlogic/ \ + aspeed/ \ broadcom/ \ cadence/ \ freescale/ \ diff --git a/drivers/phy/aspeed/Kconfig b/drivers/phy/aspeed/Kconfig new file mode 100644 index 000000000000..f7aad553f3fd --- /dev/null +++ b/drivers/phy/aspeed/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Phy drivers for Aspeed platforms +# +config PHY_ASPEED_PCIE + tristate "ASPEED PCIe PHY driver" + select GENERIC_PHY + depends on ARCH_ASPEED + help + This option enables support for the ASPEED PCIe PHY driver. + The driver provides the necessary interface to control and + configure the PCIe PHY hardware found on ASPEED SoCs. + It is required for proper operation of PCIe devices on + platforms using ASPEED chips. diff --git a/drivers/phy/aspeed/Makefile b/drivers/phy/aspeed/Makefile new file mode 100644 index 000000000000..3edce7f522e1 --- /dev/null +++ b/drivers/phy/aspeed/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PHY_ASPEED_PCIE) +=3D phy-aspeed-pcie.o diff --git a/drivers/phy/aspeed/phy-aspeed-pcie.c b/drivers/phy/aspeed/phy-= aspeed-pcie.c new file mode 100644 index 000000000000..a3a696df459e --- /dev/null +++ b/drivers/phy/aspeed/phy-aspeed-pcie.c @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 Aspeed Technology Inc. + */ + +#include +#include +#include + +/* AST2600 PCIe Host Controller Registers */ +#define PEHR_GLOBAL 0x30 +#define AST2600_PORT_TYPE_MASK GENMASK(5, 4) +#define AST2600_PORT_TYPE(x) FIELD_PREP(AST2600_PORT_TYPE_MASK, x) +#define PEHR_LOCK 0x7c +#define PCIE_UNLOCK 0xa8 + +/* AST2700 PEHR */ +#define PEHR_MISC_58 0x58 +#define LOCAL_SCALE_SUP BIT(0) +#define PEHR_MISC_5C 0x5c +#define CONFIG_RC_DEVICE BIT(30) +#define PEHR_MISC_60 0x60 +#define AST2700_PORT_TYPE_MASK GENMASK(7, 4) +#define PORT_TYPE_ROOT BIT(6) +#define PEHR_MISC_70 0x70 +#define POSTED_DATA_CREDITS(x) FIELD_PREP(GENMASK(15, 0), x) +#define POSTED_HEADER_CREDITS(x) FIELD_PREP(GENMASK(27, 16), x) +#define PEHR_MISC_78 0x78 +#define COMPLETION_DATA_CREDITS(x) FIELD_PREP(GENMASK(15, 0), x) +#define COMPLETION_HEADER_CREDITS(x) FIELD_PREP(GENMASK(27, 16), x) + +/** + * struct aspeed_pcie_phy - PCIe PHY information + * @dev: pointer to device structure + * @reg: PCIe host register base address + * @phy: pointer to PHY structure + * @platform: platform specific information + */ +struct aspeed_pcie_phy { + struct device *dev; + void __iomem *reg; + struct phy *phy; + const struct aspeed_pcie_phy_platform *platform; +}; + +/** + * struct aspeed_pcie_phy_platform - Platform information + * @phy_ops: phy operations + */ +struct aspeed_pcie_phy_platform { + const struct phy_ops *phy_ops; +}; + +static int ast2600_phy_init(struct phy *phy) +{ + struct aspeed_pcie_phy *pcie_phy =3D phy_get_drvdata(phy); + + writel(PCIE_UNLOCK, pcie_phy->reg + PEHR_LOCK); + + return 0; +} + +static int ast2600_phy_set_mode(struct phy *phy, enum phy_mode mode, + int submode) +{ + struct aspeed_pcie_phy *pcie_phy =3D phy_get_drvdata(phy); + + switch (submode) { + case PHY_MODE_PCIE_RC: + writel(AST2600_PORT_TYPE(0x3), pcie_phy->reg + PEHR_GLOBAL); + break; + default: + dev_err(&phy->dev, "Unsupported submode %d\n", submode); + return -EINVAL; + } + + return 0; +} + +static const struct phy_ops ast2600_phy_ops =3D { + .init =3D ast2600_phy_init, + .set_mode =3D ast2600_phy_set_mode, + .owner =3D THIS_MODULE, +}; + +static int ast2700_phy_init(struct phy *phy) +{ + struct aspeed_pcie_phy *pcie_phy =3D phy_get_drvdata(phy); + + writel(POSTED_DATA_CREDITS(0xc0) | POSTED_HEADER_CREDITS(0xa), + pcie_phy->reg + PEHR_MISC_70); + writel(COMPLETION_DATA_CREDITS(0x30) | COMPLETION_HEADER_CREDITS(0x8), + pcie_phy->reg + PEHR_MISC_78); + writel(LOCAL_SCALE_SUP, pcie_phy->reg + PEHR_MISC_58); + + return 0; +} + +static int ast2700_phy_set_mode(struct phy *phy, enum phy_mode mode, + int submode) +{ + struct aspeed_pcie_phy *pcie_phy =3D phy_get_drvdata(phy); + u32 cfg_val; + + switch (submode) { + case PHY_MODE_PCIE_RC: + writel(CONFIG_RC_DEVICE, pcie_phy->reg + PEHR_MISC_5C); + cfg_val =3D readl(pcie_phy->reg + PEHR_MISC_60); + cfg_val &=3D ~AST2700_PORT_TYPE_MASK; + cfg_val |=3D PORT_TYPE_ROOT; + writel(cfg_val, pcie_phy->reg + PEHR_MISC_60); + break; + default: + dev_err(&phy->dev, "Unsupported submode %d\n", submode); + return -EINVAL; + } + + return 0; +} + +static const struct phy_ops ast2700_phy_ops =3D { + .init =3D ast2700_phy_init, + .set_mode =3D ast2700_phy_set_mode, + .owner =3D THIS_MODULE, +}; + +const struct aspeed_pcie_phy_platform pcie_phy_ast2600 =3D { + .phy_ops =3D &ast2600_phy_ops, +}; + +const struct aspeed_pcie_phy_platform pcie_phy_ast2700 =3D { + .phy_ops =3D &ast2700_phy_ops, +}; + +static int aspeed_pcie_phy_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct phy_provider *phy_provider; + struct aspeed_pcie_phy *pcie_phy; + const struct aspeed_pcie_phy_platform *md; + + md =3D of_device_get_match_data(dev); + if (!md) + return -ENODEV; + + pcie_phy =3D devm_kzalloc(dev, sizeof(*pcie_phy), GFP_KERNEL); + if (!pcie_phy) + return -ENOMEM; + + pcie_phy->reg =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pcie_phy->reg)) + return PTR_ERR(pcie_phy->reg); + + pcie_phy->dev =3D dev; + pcie_phy->platform =3D md; + + pcie_phy->phy =3D devm_phy_create(dev, dev->of_node, + pcie_phy->platform->phy_ops); + if (IS_ERR(pcie_phy->phy)) + return dev_err_probe(dev, PTR_ERR(pcie_phy->phy), + "failed to create PHY\n"); + + phy_set_drvdata(pcie_phy->phy, pcie_phy); + phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id aspeed_pcie_phy_of_match_table[] =3D { + { + .compatible =3D "aspeed,ast2600-pcie-phy", + .data =3D &pcie_phy_ast2600, + }, + { + .compatible =3D "aspeed,ast2700-pcie-phy", + .data =3D &pcie_phy_ast2700, + }, + { }, +}; +MODULE_DEVICE_TABLE(of, aspeed_pcie_phy_of_match_table); + +static struct platform_driver aspeed_pcie_driver =3D { + .probe =3D aspeed_pcie_phy_probe, + .driver =3D { + .name =3D "aspeed-pcie-phy", + .of_match_table =3D aspeed_pcie_phy_of_match_table, + }, +}; + +module_platform_driver(aspeed_pcie_driver); + +MODULE_AUTHOR("Jacky Chou "); +MODULE_DESCRIPTION("ASPEED PCIe PHY"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Sun Feb 8 20:28:24 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A4642F28EB; Tue, 30 Dec 2025 05:58:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 30 Dec 2025 13:57:59 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 30 Dec 2025 13:57:59 +0800 From: Jacky Chou Date: Tue, 30 Dec 2025 13:58:01 +0800 Subject: [PATCH v8 4/4] MAINTAINERS: Add ASPEED PCIe PHY driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20251230-upstream_pcie_rc-v8-4-03598cdd80cd@aspeedtech.com> References: <20251230-upstream_pcie_rc-v8-0-03598cdd80cd@aspeedtech.com> In-Reply-To: <20251230-upstream_pcie_rc-v8-0-03598cdd80cd@aspeedtech.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" CC: , , , , , Jacky Chou X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1767074279; l=878; i=jacky_chou@aspeedtech.com; s=20251031; h=from:subject:message-id; bh=7BsJ9XPv5rGKvSJQ3KjVN6WF7d6K48ePDihYrmnFgLA=; b=zPygAO6pzHv1s2zc0IMazDFA4SlSDHTnUhapiyVpEktNPNa3UuJUPEpY1BhpwaVuxycM2bQMA Ro7Eo1n0hwXAXNSO2swWrfxQTYPhZYu5o4uD+k6/1a0oN78LrEJ5qd8 X-Developer-Key: i=jacky_chou@aspeedtech.com; a=ed25519; pk=8XBx7KFM1drEsfCXTH9QC2lbMlGU4XwJTA6Jt9Mabdo= Add maintainer entry for ASPEED PCIe PHY driver. Signed-off-by: Jacky Chou --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 765ad2daa218..bcb94fe3faa6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3843,6 +3843,14 @@ S: Maintained F: Documentation/devicetree/bindings/crypto/aspeed,* F: drivers/crypto/aspeed/ =20 +ASPEED PCIE PHY DRIVER +M: Jacky Chou +L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers) +L: linux-phy@lists.infradead.org +S: Maintained +F: Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml +F: drivers/phy/aspeed/pcie-phy-aspeed.c + ASPEED PECI CONTROLLER M: Iwona Winiarska L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers) --=20 2.34.1