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Tue, 30 Dec 2025 09:38:53 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7ff7af35f37sm32865208b3a.18.2025.12.30.09.38.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Dec 2025 09:38:52 -0800 (PST) From: Taniya Das Date: Tue, 30 Dec 2025 23:08:35 +0530 Subject: [PATCH 2/3] clk: qcom: gcc-x1e80100: Add missing UFS symbol mux clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251230-ufs_symbol_clk-v1-2-47d46b24c087@oss.qualcomm.com> References: <20251230-ufs_symbol_clk-v1-0-47d46b24c087@oss.qualcomm.com> In-Reply-To: <20251230-ufs_symbol_clk-v1-0-47d46b24c087@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rajendra Nayak , Abel Vesa , Konrad Dybcio , Bryan O'Donoghue Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sibi Sankar , Pradeep P V K , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjMwMDE1OCBTYWx0ZWRfX2VzKVE094qnL 17vzbL6tku1oT2gxHB1tcgT3o+uQqNtv5fShP8ctUr9+2qh1TWWYcD+Kp9gWLsRACC29s+CH7U9 7Uoah/EwyMLeV11VXkabGk0vzc/MwERsMGfRkaebkunTMpQTngEGHVK4YMeNNyiq4u4KtEd5oL4 8fv3kF5sOMyks3xL2oYiAKWhiuBKmaXOdMjPL5CUpxghbQ2p6r7V2nkfMsT4/swYrQiThLBy+J9 eKq5ZsCB/Jh7scH1KUXEMyDSw484ErRM2bsclvmsjX56RT5I5Sao8NCNRnKO0zXPD/7ivCb9PL5 XY5OLkzdL+ERfcNCV30SqklapTxXwuWDJHUTYiQ+PyzUy4/iotLdB/t+LIO+Qva3giuHDLpGHAU BuX7DyJAqdFse0VpWorLBYeCxkmShv92gfHh2frGx4Ly9wAfKzoKSGH7jZe4vKTx89Smu8nQwyf aMdhIfQYz4ntVxHKtGA== X-Proofpoint-ORIG-GUID: u9obpHkDJT4ANUPreSJRF_5oArLXkX9r X-Authority-Analysis: v=2.4 cv=KvNAGGWN c=1 sm=1 tr=0 ts=69540e2e cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=zK1IZneI0yAGVV4HvJ0A:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-GUID: u9obpHkDJT4ANUPreSJRF_5oArLXkX9r X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-30_02,2025-12-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 adultscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512300158 The UFS symbol RX/TX mux clocks were not defined previously. Add these mux clocks so that clock rate propagation reaches the muxes correctly. Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver f= or X1E80100") Signed-off-by: Taniya Das Reviewed-by: Abel Vesa --- drivers/clk/qcom/gcc-x1e80100.c | 102 ++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 99 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e8010= 0.c index e46e65e631513e315de2f663f3dab73e1eb70604..c8fc9e6b1ac97b13f84753ac7f7= 6e23df071c2e0 100644 --- a/drivers/clk/qcom/gcc-x1e80100.c +++ b/drivers/clk/qcom/gcc-x1e80100.c @@ -59,6 +59,9 @@ enum { DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, + DT_UFS_PHY_RX_SYMBOL_0_CLK, + DT_UFS_PHY_RX_SYMBOL_1_CLK, + DT_UFS_PHY_TX_SYMBOL_0_CLK, }; =20 enum { @@ -103,6 +106,9 @@ enum { P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK, P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, + P_UFS_PHY_RX_SYMBOL_0_CLK, + P_UFS_PHY_RX_SYMBOL_1_CLK, + P_UFS_PHY_TX_SYMBOL_0_CLK, }; =20 static struct clk_alpha_pll gcc_gpll0 =3D { @@ -482,6 +488,78 @@ static const struct clk_parent_data gcc_parent_data_33= [] =3D { { .index =3D DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK }, }; =20 +static const struct parent_map gcc_parent_map_37[] =3D { + { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_37[] =3D { + { .index =3D DT_UFS_PHY_RX_SYMBOL_0_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_38[] =3D { + { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_38[] =3D { + { .index =3D DT_UFS_PHY_RX_SYMBOL_1_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map gcc_parent_map_39[] =3D { + { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 }, + { P_BI_TCXO, 2 }, +}; + +static const struct clk_parent_data gcc_parent_data_39[] =3D { + { .index =3D DT_UFS_PHY_TX_SYMBOL_0_CLK }, + { .index =3D DT_BI_TCXO }, +}; + +static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_0_clk_src =3D { + .reg =3D 0x77064, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_rx_symbol_0_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_UFS_PHY_RX_SYMBOL_0_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_1_clk_src =3D { + .reg =3D 0x770e0, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_rx_symbol_1_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_UFS_PHY_RX_SYMBOL_1_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + +static struct clk_regmap_phy_mux gcc_ufs_phy_tx_symbol_0_clk_src =3D { + .reg =3D 0x77054, + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "gcc_ufs_phy_tx_symbol_0_clk_src", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_UFS_PHY_TX_SYMBOL_0_CLK, + }, + .num_parents =3D 1, + .ops =3D &clk_regmap_phy_mux_ops, + }, + }, +}; + static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp0_clk_src =3D { .reg =3D 0x9f06c, .clkr =3D { @@ -5148,12 +5226,17 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = =3D { =20 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk =3D { .halt_reg =3D 0x7702c, - .halt_check =3D BRANCH_HALT, + .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { .enable_reg =3D 0x7702c, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_ufs_phy_rx_symbol_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5161,12 +5244,17 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_cl= k =3D { =20 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk =3D { .halt_reg =3D 0x770cc, - .halt_check =3D BRANCH_HALT, + .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { .enable_reg =3D 0x770cc, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_ufs_phy_rx_symbol_1_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -5174,12 +5262,17 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_1_cl= k =3D { =20 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk =3D { .halt_reg =3D 0x77028, - .halt_check =3D BRANCH_HALT, + .halt_check =3D BRANCH_HALT_DELAY, .clkr =3D { .enable_reg =3D 0x77028, .enable_mask =3D BIT(0), .hw.init =3D &(const struct clk_init_data) { .name =3D "gcc_ufs_phy_tx_symbol_0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, .ops =3D &clk_branch2_ops, }, }, @@ -7180,6 +7273,9 @@ static struct clk_regmap *gcc_x1e80100_clocks[] =3D { [GCC_USB4_2_TMU_CLK_SRC] =3D &gcc_usb4_2_tmu_clk_src.clkr, [GCC_VIDEO_AXI0_CLK] =3D &gcc_video_axi0_clk.clkr, [GCC_VIDEO_AXI1_CLK] =3D &gcc_video_axi1_clk.clkr, + [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] =3D &gcc_ufs_phy_rx_symbol_0_clk_src.cl= kr, + [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] =3D &gcc_ufs_phy_rx_symbol_1_clk_src.cl= kr, + [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] =3D &gcc_ufs_phy_tx_symbol_0_clk_src.cl= kr, }; =20 static struct gdsc *gcc_x1e80100_gdscs[] =3D { --=20 2.34.1