From nobody Mon Feb 9 16:02:35 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BECDE1E832A for ; Tue, 30 Dec 2025 14:03:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767103425; cv=none; b=qqk2Ahe6hBXUyIdLnzV8ESCMOzQNSVQe091234HniFJnwsXZy+I1teRzMCOPyBu4iaZtieb0PkYX9+e4SVrndAH4FReBz2Yw2BjNKz17JKXKbu81TB5mGCM9X1PZpWQEYT7bR+t7q6pOkODPm9ePUkaMireyT0LQf6uPyiyDRUE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767103425; c=relaxed/simple; bh=rJV17EF05/w3f78uj2ASdMF8eiM0a/h7oQKf1vfMmHo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qjtaXQPyU/TgbZGdCGL6X/+XB3EC8z+GaJSpufauFu2acFDTe75Q2fIY6/Tk5PeQA8mmNDsjCcpnp9GMkCiYIIxj+8dmQNzs6KL0R8omR3tm2XhBdvA2Q3xAC+JZPjSP04VIQZhAp61cf9VsVMJ+0ahveokd7mVus6TT/7Zz+RQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=PDhygWG0; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="PDhygWG0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1767103422; bh=rJV17EF05/w3f78uj2ASdMF8eiM0a/h7oQKf1vfMmHo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=PDhygWG0x/U4wclIg9h8oZo+gQ//UlYeRFApaehOF9ikP+860UiSJUFwFG/D6F0gt sfg23E/sYyslf10PCqtHV15hGDCse7vVpKRbzpxXbTiNQ4PQ7eg3eJymG26ph25CRt Pf9Praf4I6S6MqQkHBZGXoiCJgcKwacssm5lRzXp4O58EoM4rUd7JMbAsvTS3n8tlt 05uoGNPKSurr+uCbeWxq5LCAsgbokXhLtQVXed9YSuQ/Ai5u7QcFlT4ZREf5A8/5Au AYzpzqWOAdtPzVq8lPXj2Pje18qV3X3Ip6u/gLG0pCO7w13lRZsXkpOqwiaIR4gynH zxTzx1VXuIR4g== Received: from [127.0.1.1] (unknown [IPv6:2804:1b1:f803:a1ec:e46f:3b67:baf0:3d70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id 7776817E1408; Tue, 30 Dec 2025 15:03:36 +0100 (CET) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Tue, 30 Dec 2025 11:03:02 -0300 Subject: [PATCH RFC 2/6] drm/mediatek: plane: Correct AFBC alignment definition to 128 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251230-mtk-afbc-fixes-v1-2-6c0247b66e32@collabora.com> References: <20251230-mtk-afbc-fixes-v1-0-6c0247b66e32@collabora.com> In-Reply-To: <20251230-mtk-afbc-fixes-v1-0-6c0247b66e32@collabora.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Justin Green Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ariel.dalessandro@collabora.com, daniels@collabora.com, kernel@collabora.com, Nancy.Lin@mediatek.com, Jason-JH.Lin@mediatek.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.3 The minimum alignment for both the header and data buffers in the AFBC format for Mali GPUs with archicture version 6 and higher (which includes MT8195's G57 (v9)) is 128, not 1024 as the MediaTek DRM driver currently defines. Since Mesa defines it as the correct value of 128 [1], when displaying AFBC buffers, some resolutions will cause the OVL component to be configured by the driver with a data address that is different from the address that actually contains the data as set by Mesa, resulting in corrupted output on display. Fix the AFBC alignment definition for the MediaTek DRM driver. [1] https://gitlab.freedesktop.org/mesa/mesa/-/blob/3848a080534a17ca075e9e9= 5dd3a14abb80139aa/src/panfrost/lib/pan_afbc.h#L364 Fixes: c410fa9b07c3 ("drm/mediatek: Add AFBC support to Mediatek DRM driver= ") Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_plane.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_plane.h b/drivers/gpu/drm/mediate= k/mtk_plane.h index 95c5fa5295d8..46be4454bc92 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.h +++ b/drivers/gpu/drm/mediatek/mtk_plane.h @@ -13,7 +13,7 @@ #define AFBC_DATA_BLOCK_WIDTH 32 #define AFBC_DATA_BLOCK_HEIGHT 8 #define AFBC_HEADER_BLOCK_SIZE 16 -#define AFBC_HEADER_ALIGNMENT 1024 +#define AFBC_HEADER_ALIGNMENT 128 =20 struct mtk_plane_pending_state { bool config; --=20 2.51.0