From nobody Sun Feb 8 23:42:23 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E21513A258 for ; Tue, 30 Dec 2025 14:03:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767103419; cv=none; b=Oy0xw8Q8mUQktoAmLoFjtZPlWlzLTAVBq8WqhmmcEmJ2ZzFHtcwWFUd8sJCgY1tvTtCJgV09BTZREZ+xvhwbxmVVuXD3yOqVE4vNTw3c0QDyX+ywyFfDabxyiJbrF9BPK5a75SfzMKlNIsJCk9KPMHv0dW9VP6hsd6b/IEtOWBY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767103419; c=relaxed/simple; bh=+9dZdnFTOLQEU43l4IQfP9P4NbPSetsJuzCQ32SzXns=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aXiuvLEUHtZWf3tUgqC440beXCYeI0Y8jHoHRui8W6vp1FrE7QhJ6v+KvaSVaKO6OEp9qDpGRy5n76OS65NfxpTTKzI/HJfottOrStG+0tYRpQ6gM69qbUi/VpJZ1lT4ipu7PvmP2/QhZAoV/N8Q7AsGxQfe2tmlPCd/SAM8tJE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=jIsErsen; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="jIsErsen" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1767103415; bh=+9dZdnFTOLQEU43l4IQfP9P4NbPSetsJuzCQ32SzXns=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=jIsErsenY6TL6SJSyJkoGGLS1NOKlhLcd6p7YPvROtay4CGMpi7TbCqFFTLQE7hOE 3QroSgNQieFaOh8EAMdh3NmrpZS8liS2pVoE0Ba5FMuVEpisJJeG2NByc4CBYfrCGZ I2RQInSZ+2x83QKzlxa7i/4Pc4QjAF6xpL3E7q8k0LPC6OxQy8Zr0qPF+VwJ7DTYah KI0LqFjVUHgwjNDQufzRBzyPRzERTmtH+T+iClywQ+y1BiyttuVq1lPNyH2CYQ6apV aNN/CMIPDoP6lEir/rogTD3zZ8pvA4V9NTRo2H3A7rayEdiJiYSSCdKUS+XhTkhzE6 zL0PfNET9SaLw== Received: from [127.0.1.1] (unknown [IPv6:2804:1b1:f803:a1ec:e46f:3b67:baf0:3d70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id 8CEE917E127C; Tue, 30 Dec 2025 15:03:30 +0100 (CET) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Tue, 30 Dec 2025 11:03:01 -0300 Subject: [PATCH RFC 1/6] drm/mediatek: plane: Remove extra block from AFBC data payload offset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251230-mtk-afbc-fixes-v1-1-6c0247b66e32@collabora.com> References: <20251230-mtk-afbc-fixes-v1-0-6c0247b66e32@collabora.com> In-Reply-To: <20251230-mtk-afbc-fixes-v1-0-6c0247b66e32@collabora.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Justin Green Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ariel.dalessandro@collabora.com, daniels@collabora.com, kernel@collabora.com, Nancy.Lin@mediatek.com, Jason-JH.Lin@mediatek.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.3 The AFBC data payload is in fact not offset by 1 additional block as the code and comment suggest, and this causes the buffer to be rendered offset by one block. Remove this extraneous offset to get the buffer correctly displayed. Fixes: c410fa9b07c3 ("drm/mediatek: Add AFBC support to Mediatek DRM driver= ") Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_plane.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediate= k/mtk_plane.c index 5043e0377270..1214f623859e 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_plane.c @@ -164,10 +164,9 @@ static void mtk_plane_update_new_state(struct drm_plan= e_state *new_state, */ hdr_addr =3D addr + hdr_offset; =20 - /* The data plane is offset by 1 additional block. */ offset =3D pitch * y_offset_in_blocks + AFBC_DATA_BLOCK_WIDTH * AFBC_DATA_BLOCK_HEIGHT * - fb->format->cpp[0] * (x_offset_in_blocks + 1); + fb->format->cpp[0] * x_offset_in_blocks; =20 /* * Using dma_addr_t variable to calculate with multiplier of different t= ypes, --=20 2.51.0 From nobody Sun Feb 8 23:42:23 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BECDE1E832A for ; Tue, 30 Dec 2025 14:03:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767103425; cv=none; b=qqk2Ahe6hBXUyIdLnzV8ESCMOzQNSVQe091234HniFJnwsXZy+I1teRzMCOPyBu4iaZtieb0PkYX9+e4SVrndAH4FReBz2Yw2BjNKz17JKXKbu81TB5mGCM9X1PZpWQEYT7bR+t7q6pOkODPm9ePUkaMireyT0LQf6uPyiyDRUE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767103425; c=relaxed/simple; bh=rJV17EF05/w3f78uj2ASdMF8eiM0a/h7oQKf1vfMmHo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qjtaXQPyU/TgbZGdCGL6X/+XB3EC8z+GaJSpufauFu2acFDTe75Q2fIY6/Tk5PeQA8mmNDsjCcpnp9GMkCiYIIxj+8dmQNzs6KL0R8omR3tm2XhBdvA2Q3xAC+JZPjSP04VIQZhAp61cf9VsVMJ+0ahveokd7mVus6TT/7Zz+RQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=PDhygWG0; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="PDhygWG0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1767103422; bh=rJV17EF05/w3f78uj2ASdMF8eiM0a/h7oQKf1vfMmHo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=PDhygWG0x/U4wclIg9h8oZo+gQ//UlYeRFApaehOF9ikP+860UiSJUFwFG/D6F0gt sfg23E/sYyslf10PCqtHV15hGDCse7vVpKRbzpxXbTiNQ4PQ7eg3eJymG26ph25CRt Pf9Praf4I6S6MqQkHBZGXoiCJgcKwacssm5lRzXp4O58EoM4rUd7JMbAsvTS3n8tlt 05uoGNPKSurr+uCbeWxq5LCAsgbokXhLtQVXed9YSuQ/Ai5u7QcFlT4ZREf5A8/5Au AYzpzqWOAdtPzVq8lPXj2Pje18qV3X3Ip6u/gLG0pCO7w13lRZsXkpOqwiaIR4gynH zxTzx1VXuIR4g== Received: from [127.0.1.1] (unknown [IPv6:2804:1b1:f803:a1ec:e46f:3b67:baf0:3d70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id 7776817E1408; Tue, 30 Dec 2025 15:03:36 +0100 (CET) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Tue, 30 Dec 2025 11:03:02 -0300 Subject: [PATCH RFC 2/6] drm/mediatek: plane: Correct AFBC alignment definition to 128 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251230-mtk-afbc-fixes-v1-2-6c0247b66e32@collabora.com> References: <20251230-mtk-afbc-fixes-v1-0-6c0247b66e32@collabora.com> In-Reply-To: <20251230-mtk-afbc-fixes-v1-0-6c0247b66e32@collabora.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Justin Green Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ariel.dalessandro@collabora.com, daniels@collabora.com, kernel@collabora.com, Nancy.Lin@mediatek.com, Jason-JH.Lin@mediatek.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.3 The minimum alignment for both the header and data buffers in the AFBC format for Mali GPUs with archicture version 6 and higher (which includes MT8195's G57 (v9)) is 128, not 1024 as the MediaTek DRM driver currently defines. Since Mesa defines it as the correct value of 128 [1], when displaying AFBC buffers, some resolutions will cause the OVL component to be configured by the driver with a data address that is different from the address that actually contains the data as set by Mesa, resulting in corrupted output on display. Fix the AFBC alignment definition for the MediaTek DRM driver. [1] https://gitlab.freedesktop.org/mesa/mesa/-/blob/3848a080534a17ca075e9e9= 5dd3a14abb80139aa/src/panfrost/lib/pan_afbc.h#L364 Fixes: c410fa9b07c3 ("drm/mediatek: Add AFBC support to Mediatek DRM driver= ") Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_plane.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_plane.h b/drivers/gpu/drm/mediate= k/mtk_plane.h index 95c5fa5295d8..46be4454bc92 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.h +++ b/drivers/gpu/drm/mediatek/mtk_plane.h @@ -13,7 +13,7 @@ #define AFBC_DATA_BLOCK_WIDTH 32 #define AFBC_DATA_BLOCK_HEIGHT 8 #define AFBC_HEADER_BLOCK_SIZE 16 -#define AFBC_HEADER_ALIGNMENT 1024 +#define AFBC_HEADER_ALIGNMENT 128 =20 struct mtk_plane_pending_state { bool config; --=20 2.51.0 From nobody Sun Feb 8 23:42:23 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9140124678F for ; Tue, 30 Dec 2025 14:03:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767103431; cv=none; b=MA7adbUlvVuJcqw/NKd0ze3QGayrTZB6enVs5sZAg6yJQ+4wHj0M7myRKoCtn45q0I9tmcVDHp5iaE3MJd2SmILEsuH9eSlWpbTGtK/rb7kX5r2RI14Iy+kEl6GWsVwf/4xzY+Q2Rp91xuSyR8zCJcx0FJAZIlBG6DqchpPyUrs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767103431; c=relaxed/simple; bh=niec/Lk0+W0q+vswWH4K+LQLh/B8K5auYvmJIMiA2Qo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pKp3IMlIX8rAff8cTF/aftekcD/L8+6jQ20mLbsghVlVc+K35A2tft2IwqivnO9KaPltTywIwLuViAs36AG7tsd7IBPnnz705/5hlup18IGkkpIugdwfqGhJ9fzGCMjOBlHRkbbpWwtT8cIq9s1C+Llq/gcCkr/ledz2GUCWUNs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=If0SQNrI; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="If0SQNrI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1767103427; bh=niec/Lk0+W0q+vswWH4K+LQLh/B8K5auYvmJIMiA2Qo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=If0SQNrIOjiaD0iHAz0A0Ia9cL3spRbHO4hD6+q9pPMSFzSpjAApqjY2ix1vqqHsD dwR+kxQB+CpdEVdfhFUBtzFvYEj15nF28ZsbO7esU9XBf5GL9tkJnvUvmSI5JsZl+X KtzDQ7JJc1W1k511P/stpKvERME0fuBl1UKzobuQ+ehIZ7NPyZ6PsAEmrCqRT4tpsg +sKcLELdN8B7BWWviW/xglYvrUIxvWueei0XwAKuiQgJHVMhX8Jr/9TyuLThII++cS t5dcaM+8cfYMAmUHn2zabRaxYLxJUhq+qCkbeR1OwjbXXa+In0qDjtDmdba2Dw4Sn1 ExXDjftY30wFQ== Received: from [127.0.1.1] (unknown [IPv6:2804:1b1:f803:a1ec:e46f:3b67:baf0:3d70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id 8867F17E0ED3; Tue, 30 Dec 2025 15:03:42 +0100 (CET) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Tue, 30 Dec 2025 11:03:03 -0300 Subject: [PATCH RFC 3/6] drm/mediatek: ovl: Fix misaligned layer source size on AFBC mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251230-mtk-afbc-fixes-v1-3-6c0247b66e32@collabora.com> References: <20251230-mtk-afbc-fixes-v1-0-6c0247b66e32@collabora.com> In-Reply-To: <20251230-mtk-afbc-fixes-v1-0-6c0247b66e32@collabora.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Justin Green Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ariel.dalessandro@collabora.com, daniels@collabora.com, kernel@collabora.com, Nancy.Lin@mediatek.com, Jason-JH.Lin@mediatek.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.3 From: Ariel D'Alessandro In AFBC mode, OVL_SRC_SIZE must be block aligned. Due to this limitation of the AFBC format, OVL_CLIP needs to be used to achieve the desired output size of the layer while still meeting the alignment constraints. Failure to do this will result in vblank timeouts and no rendered output when the AFBC data source isn't aligned to the AFBC block (32x8). Configure OVL_CLIP so unaligned AFBC layers can be displayed. The following illustrates how the alignment is achieved through the clip settings for the horizontal coordinates, the vertical coordinates are analogous: /------------------------------------------------\ | | | ........................ | | ........................ | | ........................ | | ........................ | | | \------------------------------------------------/ | | | | | src.x1 src.x2 | | | | | | |<-------------------->| | | src_width | | | N * AFBC_DATA_BLOCK_WIDTH M * AFBC_DATA_BLOCK_WIDTH | | |<----->| |<----->| clip_left clip_right Signed-off-by: Ariel D'Alessandro Co-developed-by: N=C3=ADcolas F. R. A. Prado Signed-off-by: N=C3=ADcolas F. R. A. Prado --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 35 ++++++++++++++++++++++++++++-= ---- drivers/gpu/drm/mediatek/mtk_plane.c | 21 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_plane.h | 4 ++++ 3 files changed, 55 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 8e20b45411fc..c6a00c2256dd 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -39,6 +39,11 @@ #define OVL_PITCH_MSB_2ND_SUBBUF BIT(16) #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n)) #define OVL_CONST_BLEND BIT(28) +#define DISP_REG_OVL_CLIP(n) (0x004C + 0x20 * (n)) +#define OVL_CLIP_LEFT GENMASK(7, 0) +#define OVL_CLIP_RIGHT GENMASK(15, 8) +#define OVL_CLIP_TOP GENMASK(23, 16) +#define OVL_CLIP_BOTTOM GENMASK(31, 24) #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) #define DISP_REG_OVL_ADDR_MT2701 0x0040 @@ -499,13 +504,14 @@ void mtk_ovl_layer_config(struct device *dev, unsigne= d int idx, struct mtk_plane_pending_state *pending =3D &state->pending; unsigned int addr =3D pending->addr; unsigned int pitch_lsb =3D pending->pitch & GENMASK(15, 0); + unsigned long long modifier =3D pending->modifier; unsigned int fmt =3D pending->format; unsigned int rotation =3D pending->rotation; unsigned int offset =3D (pending->y << 16) | pending->x; - unsigned int src_size =3D (pending->height << 16) | pending->width; unsigned int blend_mode =3D state->base.pixel_blend_mode; unsigned int ignore_pixel_alpha =3D 0; - unsigned int con; + unsigned int src_size, con, src_width, src_height; + unsigned int clip =3D 0; =20 if (!pending->enable) { mtk_ovl_layer_off(dev, idx, cmdq_pkt); @@ -550,9 +556,26 @@ void mtk_ovl_layer_config(struct device *dev, unsigned= int idx, addr +=3D pending->pitch - 1; } =20 - if (ovl->data->supports_afbc) - mtk_ovl_set_afbc(ovl, cmdq_pkt, idx, - pending->modifier !=3D DRM_FORMAT_MOD_LINEAR); + if (ovl->data->supports_afbc && (modifier !=3D DRM_FORMAT_MOD_LINEAR)) { + /* + * In AFBC mode, OVL_SRC_SIZE must be block aligned. Due to this + * limitation of the AFBC format, OVL_CLIP is used to adjust the + * output size of the layer. + */ + clip =3D FIELD_PREP(OVL_CLIP_BOTTOM, pending->clip_bottom) | + FIELD_PREP(OVL_CLIP_TOP, pending->clip_top) | + FIELD_PREP(OVL_CLIP_RIGHT, pending->clip_right) | + FIELD_PREP(OVL_CLIP_LEFT, pending->clip_left); + src_height =3D pending->height + pending->clip_top + pending->clip_botto= m; + src_width =3D pending->width + pending->clip_left + pending->clip_right; + mtk_ovl_set_afbc(ovl, cmdq_pkt, idx, true); + } else { + src_height =3D pending->height; + src_width =3D pending->width; + mtk_ovl_set_afbc(ovl, cmdq_pkt, idx, false); + } + + src_size =3D (src_height << 16) | src_width; =20 mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CON(idx)); @@ -560,6 +583,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx)); mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_SRC_SIZE(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, clip, &ovl->cmdq_reg, ovl->regs, + DISP_REG_OVL_CLIP(idx)); mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_OFFSET(idx)); mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs, diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediate= k/mtk_plane.c index 1214f623859e..8fb08768e8ce 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_plane.c @@ -114,6 +114,7 @@ static void mtk_plane_update_new_state(struct drm_plane= _state *new_state, struct mtk_plane_state *mtk_plane_state) { struct drm_framebuffer *fb =3D new_state->fb; + unsigned int clip_left =3D 0, clip_top =3D 0, clip_right =3D 0, clip_bott= om =3D 0; struct drm_gem_object *gem; struct mtk_gem_obj *mtk_gem; unsigned int pitch, format; @@ -148,6 +149,22 @@ static void mtk_plane_update_new_state(struct drm_plan= e_state *new_state, int x_offset_in_blocks =3D (new_state->src.x1 >> 16) / AFBC_DATA_BLOCK_W= IDTH; int y_offset_in_blocks =3D (new_state->src.y1 >> 16) / AFBC_DATA_BLOCK_H= EIGHT; int hdr_size, hdr_offset; + int src_width =3D drm_rect_width(&new_state->src) >> 16; + int src_height =3D drm_rect_height(&new_state->src) >> 16; + unsigned int remainder_right, remainder_bottom; + + /* + * In AFBC mode, the source size configured needs to be a + * multiple of the AFBC data block size. Compute and save the + * necessary clips so the indeded x, y, width and height are + * obtained in the output despite this constraint. + */ + clip_left =3D (new_state->src.x1 >> 16) % AFBC_DATA_BLOCK_WIDTH; + clip_top =3D (new_state->src.y1 >> 16) % AFBC_DATA_BLOCK_HEIGHT; + remainder_right =3D (src_width + clip_left) % AFBC_DATA_BLOCK_WIDTH; + clip_right =3D remainder_right ? AFBC_DATA_BLOCK_WIDTH - remainder_right= : 0; + remainder_bottom =3D (src_height + clip_top) % AFBC_DATA_BLOCK_HEIGHT; + clip_bottom =3D remainder_bottom ? AFBC_DATA_BLOCK_HEIGHT - remainder_bo= ttom : 0; =20 hdr_pitch =3D width_in_blocks * AFBC_HEADER_BLOCK_SIZE; pitch =3D width_in_blocks * AFBC_DATA_BLOCK_WIDTH * @@ -187,6 +204,10 @@ static void mtk_plane_update_new_state(struct drm_plan= e_state *new_state, mtk_plane_state->pending.y =3D new_state->dst.y1; mtk_plane_state->pending.width =3D drm_rect_width(&new_state->dst); mtk_plane_state->pending.height =3D drm_rect_height(&new_state->dst); + mtk_plane_state->pending.clip_left =3D clip_left; + mtk_plane_state->pending.clip_top =3D clip_top; + mtk_plane_state->pending.clip_right =3D clip_right; + mtk_plane_state->pending.clip_bottom =3D clip_bottom; mtk_plane_state->pending.rotation =3D new_state->rotation; mtk_plane_state->pending.color_encoding =3D new_state->color_encoding; } diff --git a/drivers/gpu/drm/mediatek/mtk_plane.h b/drivers/gpu/drm/mediate= k/mtk_plane.h index 46be4454bc92..a9cfb2ee5859 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.h +++ b/drivers/gpu/drm/mediatek/mtk_plane.h @@ -28,6 +28,10 @@ struct mtk_plane_pending_state { unsigned int y; unsigned int width; unsigned int height; + unsigned int clip_left; + unsigned int clip_top; + unsigned int clip_right; + unsigned int clip_bottom; unsigned int rotation; bool dirty; bool async_dirty; --=20 2.51.0 From nobody Sun Feb 8 23:42:23 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72396267731 for ; Tue, 30 Dec 2025 14:03:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767103437; cv=none; b=KZ2HhvGhqeuNkExtEggap2Bbn73SzRVyJTGUa5rq0A6L6dEfZwH/azeQe6dOEYNqBBgqGlWrnjAvM8OTTH/B3EMduavXisNcSdDaljhV7n9eyVJl/U5wrWoDLpLJiwTsF7+53Ai6oxCMX1HeSY9IkIdw/IrvlNaZdtbiTSWcNLM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767103437; c=relaxed/simple; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251230-mtk-afbc-fixes-v1-4-6c0247b66e32@collabora.com> References: <20251230-mtk-afbc-fixes-v1-0-6c0247b66e32@collabora.com> In-Reply-To: <20251230-mtk-afbc-fixes-v1-0-6c0247b66e32@collabora.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Justin Green Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ariel.dalessandro@collabora.com, daniels@collabora.com, kernel@collabora.com, Nancy.Lin@mediatek.com, Jason-JH.Lin@mediatek.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.3 AFBC buffers with width over 1920 are not supported by OVL. If attempted, the image displayed contains many artifacts. Add this restriction to the layer check callback so such configurations are not allowed. NOTE: This doesn't seem to be a good way to handle this restriction, as when tested with Weston, it simply fails to render, rather than fallback to not using the modifier: [19:09:03.857] atomic: couldn't commit new state: Invalid argument [19:09:03.857] repaint-flush failed: Invalid argument Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index c6a00c2256dd..196b874057ba 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -368,6 +368,13 @@ int mtk_ovl_layer_check(struct device *dev, unsigned i= nt idx, if (state->fb->format->is_yuv && (state->rotation & ~DRM_MODE_ROTATE_0)) return -EINVAL; =20 + /* + * AFBC buffers with width > 1920 are not supported and produce + * artifacts, so should be disabled. + */ + if (state->fb->modifier !=3D DRM_FORMAT_MOD_LINEAR && state->fb->width > = 1920) + return -EINVAL; + return 0; } =20 --=20 2.51.0 From nobody Sun Feb 8 23:42:23 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7354D2459D1 for ; Tue, 30 Dec 2025 14:04:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767103443; cv=none; b=rT/Ar/Qd8vTi3qz6KATG/hZLBVihGPB6cEaeJ1i6rlrIxEuU56cGpxZ8C1A/bGydUAxOCYUbTwt0nhSFowq4/dQIpoDPRomylqa/MafbXSH1NcpcUenngKdILHZwdmwLJuDDVNoK5xcj+fvA8yhxYBlGEhTOBA3E7jp72sYs1Bk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767103443; c=relaxed/simple; bh=7ItMKgsVy2ANsMynoBcCjpMv8Wqb8/BHa+zFioLqrpU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=syiJt72BgLMxzRo+IWm0rwc5FnXooUNOcmOcgl1VfONcgLdgLP/gCKf0GKQPzdRoU3XV0Sjdbb+mGvob5lkHHYaoN0AlU9eCbTZjeMU6kUJ1Ei3OX5v1/yjFjAdgWnM/f0Q5y79HhA9cuAiZlL1uNryK0f/LZ5tn6v25vqsfuHc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=Y7JDCR3K; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="Y7JDCR3K" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1767103439; bh=7ItMKgsVy2ANsMynoBcCjpMv8Wqb8/BHa+zFioLqrpU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Y7JDCR3KjF5xO3Cb9p8u4LJAanA1E+R1SJFxaZgjU/Etndc0lo1hPKtGny9QXsImT lBOmOs0SkuSiz4Ptv3Nlt/0iBvRxGd4xf206J+9utGm6abmLEq/euGzWZRdOvdZSZ1 LjKb5xEi7xZWwiHyG6O6vYa6Hi4o0+lMMiGrrBERqjuUXbW8YDzN4nW5QCX4WZAXQk WMYNC0Pwo8ipF7j9E9QzlcEcBMx+MgvtU2EXyFMuEBrw4cx9qa2wuDoDkPPks4G1gs ZYjBKH76CLrhKOfkj4lXTi3YcflkSsO+IU2IClTszAln7TeoN8veD38tjUJYeExS5f aIV0UPdepajzg== Received: from [127.0.1.1] (unknown [IPv6:2804:1b1:f803:a1ec:e46f:3b67:baf0:3d70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id 8242317E0ED3; Tue, 30 Dec 2025 15:03:54 +0100 (CET) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Tue, 30 Dec 2025 11:03:05 -0300 Subject: [PATCH RFC 5/6] drm/mediatek: ovl: Disable AFBC on MT8188 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251230-mtk-afbc-fixes-v1-5-6c0247b66e32@collabora.com> References: <20251230-mtk-afbc-fixes-v1-0-6c0247b66e32@collabora.com> In-Reply-To: <20251230-mtk-afbc-fixes-v1-0-6c0247b66e32@collabora.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Justin Green Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ariel.dalessandro@collabora.com, daniels@collabora.com, kernel@collabora.com, Nancy.Lin@mediatek.com, Jason-JH.Lin@mediatek.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.3 Despite MT8188's OVL being mostly the same IP as the OVL on MT8195, it does not support AFBC, even when the same register configurations are applied. Introduce a separate compatible for it with AFBC support disabled. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 196b874057ba..97f6694772d4 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -762,6 +762,21 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_dr= iver_data =3D { .num_formats =3D ARRAY_SIZE(mt8173_formats), }; =20 +static const struct mtk_disp_ovl_data mt8188_ovl_driver_data =3D { + .addr =3D DISP_REG_OVL_ADDR_MT8173, + .gmc_bits =3D 10, + .layer_nr =3D 4, + .fmt_rgb565_is_0 =3D true, + .smi_id_en =3D true, + .supports_afbc =3D false, + .blend_modes =3D BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE) | + BIT(DRM_MODE_BLEND_PIXEL_NONE), + .formats =3D mt8195_formats, + .num_formats =3D ARRAY_SIZE(mt8195_formats), + .supports_clrfmt_ext =3D true, +}; + static const struct mtk_disp_ovl_data mt8195_ovl_driver_data =3D { .addr =3D DISP_REG_OVL_ADDR_MT8173, .gmc_bits =3D 10, @@ -790,6 +805,8 @@ static const struct of_device_id mtk_disp_ovl_driver_dt= _match[] =3D { .data =3D &mt8192_ovl_driver_data}, { .compatible =3D "mediatek,mt8192-disp-ovl-2l", .data =3D &mt8192_ovl_2l_driver_data}, + { .compatible =3D "mediatek,mt8188-disp-ovl", + .data =3D &mt8188_ovl_driver_data}, { .compatible =3D "mediatek,mt8195-disp-ovl", .data =3D &mt8195_ovl_driver_data}, {}, --=20 2.51.0 From nobody Sun Feb 8 23:42:23 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3895824BD for ; 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Tue, 30 Dec 2025 15:03:59 +0100 (CET) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Tue, 30 Dec 2025 11:03:06 -0300 Subject: [PATCH RFC 6/6] drm/mediatek: Re-enable AFBC support on MediaTek DRM driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251230-mtk-afbc-fixes-v1-6-6c0247b66e32@collabora.com> References: <20251230-mtk-afbc-fixes-v1-0-6c0247b66e32@collabora.com> In-Reply-To: <20251230-mtk-afbc-fixes-v1-0-6c0247b66e32@collabora.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Simona Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Justin Green Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ariel.dalessandro@collabora.com, daniels@collabora.com, kernel@collabora.com, Nancy.Lin@mediatek.com, Jason-JH.Lin@mediatek.com, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= X-Mailer: b4 0.14.3 Commit 9882a4064003 ("drm/mediatek: Disable AFBC support on Mediatek DRM driver") disabled AFBC support on the MediaTek DRM driver since it was broken. With the bugs in the AFBC support now fixed, re-enable the support. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_plane.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediate= k/mtk_plane.c index 8fb08768e8ce..38dd94cdd665 100644 --- a/drivers/gpu/drm/mediatek/mtk_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_plane.c @@ -22,6 +22,9 @@ =20 static const u64 modifiers[] =3D { DRM_FORMAT_MOD_LINEAR, + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | + AFBC_FORMAT_MOD_SPLIT | + AFBC_FORMAT_MOD_SPARSE), DRM_FORMAT_MOD_INVALID, }; =20 @@ -69,7 +72,26 @@ static bool mtk_plane_format_mod_supported(struct drm_pl= ane *plane, uint32_t format, uint64_t modifier) { - return modifier =3D=3D DRM_FORMAT_MOD_LINEAR; + if (modifier =3D=3D DRM_FORMAT_MOD_LINEAR) + return true; + + if (modifier !=3D DRM_FORMAT_MOD_ARM_AFBC( + AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | + AFBC_FORMAT_MOD_SPLIT | + AFBC_FORMAT_MOD_SPARSE)) + return false; + + if (format !=3D DRM_FORMAT_XRGB8888 && + format !=3D DRM_FORMAT_ARGB8888 && + format !=3D DRM_FORMAT_BGRX8888 && + format !=3D DRM_FORMAT_BGRA8888 && + format !=3D DRM_FORMAT_ABGR8888 && + format !=3D DRM_FORMAT_XBGR8888 && + format !=3D DRM_FORMAT_RGB888 && + format !=3D DRM_FORMAT_BGR888) + return false; + + return true; } =20 static void mtk_plane_destroy_state(struct drm_plane *plane, --=20 2.51.0