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Support programming the timer in the INTF block. Fixes tag points to the commit which removed register access to those registers on DPU 8.x+ (and which also should have added proper support for WD timer on those devices). Fixes: 43e3293fc614 ("drm/msm/dpu: add support for MDP_TOP blackhole") Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 49 +++++++++++++++++++++++++= ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 7 ----- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 7 +++++ 5 files changed, 57 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 3921c15aee98..058a7c8727f7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -775,13 +775,13 @@ static void _dpu_encoder_update_vsync_source(struct d= pu_encoder_virt *dpu_enc, } =20 vsync_cfg.vsync_source =3D disp_info->vsync_source; + vsync_cfg.frame_rate =3D drm_mode_vrefresh(&dpu_enc->base.crtc->state->ad= justed_mode); =20 if (hw_mdptop->ops.setup_vsync_source) { for (i =3D 0; i < dpu_enc->num_phys_encs; i++) vsync_cfg.ppnumber[i] =3D dpu_enc->hw_pp[i]->idx; =20 vsync_cfg.pp_count =3D dpu_enc->num_phys_encs; - vsync_cfg.frame_rate =3D drm_mode_vrefresh(&dpu_enc->base.crtc->state->a= djusted_mode); =20 hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg); } @@ -791,7 +791,7 @@ static void _dpu_encoder_update_vsync_source(struct dpu= _encoder_virt *dpu_enc, =20 if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel) phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf, - vsync_cfg.vsync_source); + &vsync_cfg); } } =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_intf.c index a80ac82a9625..7e620f590984 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -67,6 +67,10 @@ #define INTF_MISR_CTRL 0x180 #define INTF_MISR_SIGNATURE 0x184 =20 +#define INTF_WD_TIMER_0_CTL 0x230 +#define INTF_WD_TIMER_0_CTL2 0x234 +#define INTF_WD_TIMER_0_LOAD_VALUE 0x238 + #define INTF_MUX 0x25C #define INTF_STATUS 0x26C #define INTF_AVR_CONTROL 0x270 @@ -475,7 +479,20 @@ static int dpu_hw_intf_get_vsync_info(struct dpu_hw_in= tf *intf, } =20 static void dpu_hw_intf_vsync_sel(struct dpu_hw_intf *intf, - enum dpu_vsync_source vsync_source) + struct dpu_vsync_source_cfg *cfg) +{ + struct dpu_hw_blk_reg_map *c; + + if (!intf) + return; + + c =3D &intf->hw; + + DPU_REG_WRITE(c, INTF_TEAR_MDP_VSYNC_SEL, (cfg->vsync_source & 0xf)); +} + +static void dpu_hw_intf_vsync_sel_v8(struct dpu_hw_intf *intf, + struct dpu_vsync_source_cfg *cfg) { struct dpu_hw_blk_reg_map *c; =20 @@ -484,7 +501,30 @@ static void dpu_hw_intf_vsync_sel(struct dpu_hw_intf *= intf, =20 c =3D &intf->hw; =20 - DPU_REG_WRITE(c, INTF_TEAR_MDP_VSYNC_SEL, (vsync_source & 0xf)); + if (cfg->vsync_source >=3D DPU_VSYNC_SOURCE_WD_TIMER_4 && + cfg->vsync_source <=3D DPU_VSYNC_SOURCE_WD_TIMER_1) { + pr_warn_once("DPU 8.x supports only GPIOs and timer0 as TE sources\n"); + return; + } + + if (cfg->vsync_source =3D=3D DPU_VSYNC_SOURCE_WD_TIMER_0) { + u32 reg; + + DPU_REG_WRITE(c, INTF_WD_TIMER_0_LOAD_VALUE, + CALCULATE_WD_LOAD_VALUE(cfg->frame_rate)); + + DPU_REG_WRITE(c, INTF_WD_TIMER_0_CTL, BIT(0)); /* clear timer */ + + reg =3D BIT(8); /* enable heartbeat timer */ + reg |=3D BIT(0); /* enable WD timer */ + reg |=3D BIT(1); /* select default 16 clock ticks */ + DPU_REG_WRITE(c, INTF_WD_TIMER_0_CTL2, reg); + + /* make sure that timers are enabled/disabled for vsync state */ + wmb(); + } + + dpu_hw_intf_vsync_sel(intf, cfg); } =20 static void dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf, @@ -598,7 +638,10 @@ struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device= *dev, c->ops.enable_tearcheck =3D dpu_hw_intf_enable_te; c->ops.disable_tearcheck =3D dpu_hw_intf_disable_te; c->ops.connect_external_te =3D dpu_hw_intf_connect_external_te; - c->ops.vsync_sel =3D dpu_hw_intf_vsync_sel; + if (mdss_rev->core_major_ver >=3D 8) + c->ops.vsync_sel =3D dpu_hw_intf_vsync_sel_v8; + else + c->ops.vsync_sel =3D dpu_hw_intf_vsync_sel; c->ops.disable_autorefresh =3D dpu_hw_intf_disable_autorefresh; } =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_intf.h index f31067a9aaf1..e84ab849d71a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -12,6 +12,7 @@ #include "dpu_hw_util.h" =20 struct dpu_hw_intf; +struct dpu_vsync_source_cfg; =20 /* intf timing settings */ struct dpu_hw_intf_timing_params { @@ -107,7 +108,7 @@ struct dpu_hw_intf_ops { =20 int (*connect_external_te)(struct dpu_hw_intf *intf, bool enable_external= _te); =20 - void (*vsync_sel)(struct dpu_hw_intf *intf, enum dpu_vsync_source vsync_s= ource); + void (*vsync_sel)(struct dpu_hw_intf *intf, struct dpu_vsync_source_cfg *= cfg); =20 /** * Disable autorefresh if enabled diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_top.c index 96dc10589bee..1ebd75d4f9be 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -22,13 +22,6 @@ #define TRAFFIC_SHAPER_WR_CLIENT(num) (0x060 + (num * 4)) #define TRAFFIC_SHAPER_FIXPOINT_FACTOR 4 =20 -#define MDP_TICK_COUNT 16 -#define XO_CLK_RATE 19200 -#define MS_TICKS_IN_SEC 1000 - -#define CALCULATE_WD_LOAD_VALUE(fps) \ - ((uint32_t)((MS_TICKS_IN_SEC * XO_CLK_RATE)/(MDP_TICK_COUNT * fps))) - static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp, struct split_pipe_cfg *cfg) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_util.h index 67b08e99335d..6fe65bc3bff4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h @@ -21,6 +21,13 @@ =20 #define TO_S15D16(_x_)((_x_) << 7) =20 +#define MDP_TICK_COUNT 16 +#define XO_CLK_RATE 19200 +#define MS_TICKS_IN_SEC 1000 + +#define CALCULATE_WD_LOAD_VALUE(fps) \ + ((uint32_t)((MS_TICKS_IN_SEC * XO_CLK_RATE)/(MDP_TICK_COUNT * fps))) + extern const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L; extern const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L; extern const struct dpu_csc_cfg dpu_csc10_rgb2yuv_601l; --=20 2.47.3