From nobody Mon Feb 9 22:38:37 2026 Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1CD4275114; Tue, 30 Dec 2025 16:49:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767113369; cv=none; b=uezxKWDRrQj02S9r8pTG9+fXzFzdYtAE2sNdf6KrfGnJQgWvKRyDtEtzCpQpWUWNt9HoBWhGKTC5TxYyazZAyV22/chwjlRnpAu/YVE9tq55HPJ17q7Fk5SWZGtfMBqiBd/hljrYBR1NEo1RqMoTkeSyuAoooorHMp148wVVmwY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767113369; c=relaxed/simple; bh=RhC6l1PbQbreA7q0UtfZqJIjoV0EZp1hIhdytC+A7v8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AiYsmy7n5WhBvvtK3MQwUkWMFKUdPPTmqExmWjtwi8fmvvFvl5pKWrjWEIE43P4Ip5gw6zpKd0W7f2yu3KYtNiEouNqroHjcMpqsZ7Cewa+z7dfWxQz/HON29DR8OCKQjKxwS0YFApTgrQI/bBu+19JlY8K2jNYXhhaSwROl0nI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn; spf=pass smtp.mailfrom=isrc.iscas.ac.cn; arc=none smtp.client-ip=159.226.251.84 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=isrc.iscas.ac.cn Received: from minun.felixc.at (unknown [65.108.105.71]) by APP-05 (Coremail) with SMTP id zQCowAA3yQw8AlRpUjKQAg--.63740S6; Wed, 31 Dec 2025 00:48:51 +0800 (CST) From: Asuna Yang Date: Tue, 30 Dec 2025 17:47:57 +0100 Subject: [PATCH v6 4/4] RISC-V: handle extension configs for bindgen, re-enable gcc + rust builds Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20251230-gcc-rust-v5-v6-4-2ac86ba728c8@isrc.iscas.ac.cn> References: <20251230-gcc-rust-v5-v6-0-2ac86ba728c8@isrc.iscas.ac.cn> In-Reply-To: <20251230-gcc-rust-v5-v6-0-2ac86ba728c8@isrc.iscas.ac.cn> To: Nathan Chancellor , Nicolas Schier , Miguel Ojeda , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Nick Desaulniers , Bill Wendling , Justin Stitt , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet , Conor Dooley , Mingcong Bai , Han Gao , Vivian Wang , Jason Montleon Cc: linux-kbuild@vger.kernel.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, llvm@lists.linux.dev, linux-riscv@lists.infradead.org, linux-doc@vger.kernel.org, Asuna Yang X-Mailer: b4 0.14.3 X-CM-TRANSID: zQCowAA3yQw8AlRpUjKQAg--.63740S6 X-Coremail-Antispam: 1UD129KBjvJXoW3Jw1kWr1Uur4UKF1xZFW7XFb_yoWfJFWUpw n2yr97tr4DJFyDKr12yry8W3WYk3Z5JFs3WFy8Kw18ArZayryvvrWqya13Z34UCan2vr9I qw47uF4UXr4UCFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHab7Iv0xC_Kw4lb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6r1S6rWUM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI 8067AKxVWUAVCq3wA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28C jxkF64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVWUJVWUCwA2z4x0Y4vE2Ix0cI 8IcVCY1x0267AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Jr0_Gr1l84ACjcxK6I8E 87Iv6xkF7I0E14v26r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2 IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4U McvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I64 8v4I1lFIxGxcIEc7CjxVA2Y2ka0xkIwI1lc7CjxVAaw2AFwI0_GFv_Wrylc2xSY4AK6IIF 6r1l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxV WUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI 7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r 4UJVWxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4U MIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjxUxbyuUU UUU X-CM-SenderInfo: x0lq233loux21fy6x21ufox2xfdvhtffof0/ Commit 33549fcf37ec ("RISC-V: disallow gcc + rust builds") disabled GCC + Rust builds for RISC-V due to differences in extension handling compared to LLVM. This commit enables GCC + Rust builds again. Add `bindgen-option` conditions for the availability of libclang to the RISC-V extension Kconfig symbols that depend on the `cc-option` function. For Zicsr/Zifencei special handling, since LLVM/Clang always enables these two extensions, either don't pass them to `-march`, or pass them explicitly and Rust bindgen libclang must recognize them. Clang does not support `-mno-riscv-attribute` flag, filter it out to resolve error: unknown argument: '-mno-riscv-attribute'. Define `BINDGEN_TARGET_riscv` to pass the target triplet to Rust bindgen libclang for RISC-V to resolve error: unsupported argument 'medany' to option '-mcmodel=3D' for target 'unknown'. Update the documentation, GCC + Rust builds for RISC-V are now maintained. Acked-by: Miguel Ojeda Signed-off-by: Asuna Yang --- Documentation/rust/arch-support.rst | 2 +- arch/riscv/Kconfig | 35 +++++++++++++++++++++++++++++++++= +- rust/Makefile | 3 ++- scripts/Makefile.rust | 1 + 4 files changed, 38 insertions(+), 3 deletions(-) diff --git a/Documentation/rust/arch-support.rst b/Documentation/rust/arch-= support.rst index 6e6a515d0899..5282e0e174e8 100644 --- a/Documentation/rust/arch-support.rst +++ b/Documentation/rust/arch-support.rst @@ -18,7 +18,7 @@ Architecture Level of support Constraints ``arm`` Maintained ARMv7 Little Endian only. ``arm64`` Maintained Little Endian only. ``loongarch`` Maintained \- -``riscv`` Maintained ``riscv64`` and LLVM/Clang only. +``riscv`` Maintained ``riscv64`` only. ``um`` Maintained \- ``x86`` Maintained ``x86_64`` only. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6b39f37f769a..c869ee07117e 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -195,7 +195,7 @@ config RISCV select HAVE_REGS_AND_STACK_ACCESS_API select HAVE_RETHOOK if !XIP_KERNEL select HAVE_RSEQ - select HAVE_RUST if RUSTC_SUPPORTS_RISCV && CC_IS_CLANG + select HAVE_RUST if RUSTC_SUPPORTS_RISCV && TOOLCHAIN_MATCHES_ZICSR_ZIFEN= CEI select HAVE_SAMPLE_FTRACE_DIRECT select HAVE_SAMPLE_FTRACE_DIRECT_MULTI select HAVE_STACKPROTECTOR @@ -619,6 +619,8 @@ config TOOLCHAIN_HAS_V depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32imv) depends on LD_IS_LLD || LD_VERSION >=3D 23800 depends on AS_HAS_OPTION_ARCH + depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=3Dlp64 -marc= h=3Drv64imv) + depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=3Dilp32 -mar= ch=3Drv32imv) =20 config RISCV_ISA_V bool "Vector extension support" @@ -683,6 +685,8 @@ config TOOLCHAIN_HAS_ZABHA depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv64ima_zabha) depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32ima_zabha) depends on AS_HAS_OPTION_ARCH + depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=3Dlp64 -marc= h=3Drv64ima_zabha) + depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=3Dilp32 -mar= ch=3Drv32ima_zabha) =20 config RISCV_ISA_ZABHA bool "Zabha extension support for atomic byte/halfword operations" @@ -701,6 +705,8 @@ config TOOLCHAIN_HAS_ZACAS depends on !64BIT || $(cc-option,-mabi=3Dlp64 -march=3Drv64ima_zacas) depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32ima_zacas) depends on AS_HAS_OPTION_ARCH + depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=3Dlp64 -marc= h=3Drv64ima_zacas) + depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=3Dilp32 -mar= ch=3Drv32ima_zacas) =20 config RISCV_ISA_ZACAS bool "Zacas extension support for atomic CAS" @@ -719,6 +725,8 @@ config TOOLCHAIN_HAS_ZBB depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32ima_zbb) depends on LD_IS_LLD || LD_VERSION >=3D 23900 depends on AS_HAS_OPTION_ARCH + depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=3Dlp64 -marc= h=3Drv64ima_zbb) + depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=3Dilp32 -mar= ch=3Drv32ima_zbb) =20 # This symbol indicates that the toolchain supports all v1.0 vector crypto # extensions, including Zvk*, Zvbb, and Zvbc. LLVM added all of these at = once. @@ -734,6 +742,8 @@ config TOOLCHAIN_HAS_ZBA depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32ima_zba) depends on LD_IS_LLD || LD_VERSION >=3D 23900 depends on AS_HAS_OPTION_ARCH + depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=3Dlp64 -marc= h=3Drv64ima_zba) + depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=3Dilp32 -mar= ch=3Drv32ima_zba) =20 config RISCV_ISA_ZBA bool "Zba extension support for bit manipulation instructions" @@ -769,6 +779,8 @@ config TOOLCHAIN_HAS_ZBC depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32ima_zbc) depends on LD_IS_LLD || LD_VERSION >=3D 23900 depends on AS_HAS_OPTION_ARCH + depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=3Dlp64 -marc= h=3Drv64ima_zbc) + depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=3Dilp32 -mar= ch=3Drv32ima_zbc) =20 config RISCV_ISA_ZBC bool "Zbc extension support for carry-less multiplication instructions" @@ -792,6 +804,8 @@ config TOOLCHAIN_HAS_ZBKB depends on !32BIT || $(cc-option,-mabi=3Dilp32 -march=3Drv32ima_zbkb) depends on LD_IS_LLD || LD_VERSION >=3D 23900 depends on AS_HAS_OPTION_ARCH + depends on !RUST || !64BIT || $(bindgen-backend-option,-mabi=3Dlp64 -marc= h=3Drv64ima_zbkb) + depends on !RUST || !32BIT || $(bindgen-backend-option,-mabi=3Dilp32 -mar= ch=3Drv32ima_zbkb) =20 config RISCV_ISA_ZBKB bool "Zbkb extension support for bit manipulation instructions" @@ -893,6 +907,25 @@ config TOOLCHAIN_NEEDS_OLD_ISA_SPEC versions of clang and GCC to be passed to GAS, which has the same result as passing zicsr and zifencei to -march. =20 +config RUST_BINDGEN_HAS_ZICSR_ZIFENCEI + def_bool y + depends on !64BIT || $(bindgen-backend-option,-mabi=3Dlp64 -march=3Drv64i= ma_zicsr_zifencei) + depends on !32BIT || $(bindgen-backend-option,-mabi=3Dilp32 -march=3Drv32= ima_zicsr_zifencei) + +config TOOLCHAIN_MATCHES_ZICSR_ZIFENCEI + def_bool y + # https://github.com/llvm/llvm-project/commit/22e199e6afb1263c943c0c0d449= 8694e15bf8a16 + depends on TOOLCHAIN_NEEDS_OLD_ISA_SPEC || !TOOLCHAIN_NEEDS_EXPLICIT_ZICS= R_ZIFENCEI || RUST_BINDGEN_HAS_ZICSR_ZIFENCEI + help + LLVM/Clang >=3D 17.0.0 starts recognizing Zicsr/Zifencei in -march, pas= sing + them to -march doesn't generate an error anymore, and passing them or n= ot + doesn't have any real difference, it still follows ISA before version + 20190608 - Zicsr/Zifencei are included in base ISA. + + The current latest version of LLVM/Clang still does not require explicit + Zicsr/Zifencei to enable these two extensions, Clang just accepts them = in + -march and then silently ignores them. + config FPU bool "FPU support" default y diff --git a/rust/Makefile b/rust/Makefile index 37b4205afb70..d8b6a570cb84 100644 --- a/rust/Makefile +++ b/rust/Makefile @@ -383,7 +383,8 @@ bindgen_skip_c_flags :=3D -mno-fp-ret-in-387 -mpreferre= d-stack-boundary=3D% \ -fno-inline-functions-called-once -fsanitize=3Dbounds-strict \ -fstrict-flex-arrays=3D% -fmin-function-alignment=3D% \ -fzero-init-padding-bits=3D% -mno-fdpic \ - --param=3D% --param asan-% -fno-isolate-erroneous-paths-dereference + --param=3D% --param asan-% -fno-isolate-erroneous-paths-dereference \ + -mno-riscv-attribute =20 # Because scripts/Makefile.rust is included regardless of whether Rust is = enabled, # we perform this check here to avoid breaking targets that do not yet sup= port Rust builds. diff --git a/scripts/Makefile.rust b/scripts/Makefile.rust index 5c12b4b8c8b6..bfdad4a0a3ce 100644 --- a/scripts/Makefile.rust +++ b/scripts/Makefile.rust @@ -3,6 +3,7 @@ BINDGEN_TARGET_x86 :=3D x86_64-linux-gnu BINDGEN_TARGET_arm64 :=3D aarch64-linux-gnu BINDGEN_TARGET_arm :=3D arm-linux-gnueabi BINDGEN_TARGET_loongarch :=3D loongarch64-linux-gnusf +BINDGEN_TARGET_riscv :=3D riscv64-linux-gnu BINDGEN_TARGET_um :=3D $(BINDGEN_TARGET_$(SUBARCH)) BINDGEN_TARGET :=3D $(BINDGEN_TARGET_$(SRCARCH)) =20 --=20 2.51.1