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These devices are part of the AOSS, CDSP, QDSS, PCIe5, TraceNoc and some small subsystems, such as GCC, IPCC, PMU and so on. Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/glymur.dtsi | 1529 +++++++++++++++++++++++++++++-= ---- 1 file changed, 1335 insertions(+), 194 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index eb042541cfe1..9ef1fd66168c 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -358,6 +358,18 @@ domain_ss3: domain-sleep-0 { }; }; =20 + dummy-sink { + compatible =3D "arm,coresight-dummy-sink"; + + in-ports { + port { + eud_in: endpoint { + remote-endpoint =3D <&swao_rep_out1>; + }; + }; + }; + }; + firmware { scm: scm { compatible =3D "qcom,scm-glymur", "qcom,scm"; @@ -4076,251 +4088,1354 @@ rx-pins { }; }; =20 - apps_smmu: iommu@15000000 { - compatible =3D "qcom,glymur-smmu-500", - "qcom,smmu-500", - "arm,mmu-500"; - reg =3D <0x0 0x15000000 0x0 0x100000>; - - #iommu-cells =3D <2>; - #global-interrupts =3D <1>; + stm: stm@10002000 { + compatible =3D "arm,coresight-stm", "arm,primecell"; + reg =3D <0x0 0x10002000 0x0 0x1000>, + <0x0 0x16280000 0x0 0x180000>; + reg-names =3D "stm-base", + "stm-stimulus-base"; =20 - interrupts =3D , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; =20 - dma-coherent; + out-ports { + port { + stm_out: endpoint { + remote-endpoint =3D <&funnel0_in7>; + }; + }; + }; }; =20 - intc: interrupt-controller@17000000 { - compatible =3D "arm,gic-v3"; - reg =3D <0x0 0x17000000 0x0 0x10000>, - <0x0 0x17080000 0x0 0x480000>; + tpda@10004000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x0 0x10004000 0x0 0x1000>; =20 - interrupts =3D ; + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; =20 - #interrupt-cells =3D <3>; - interrupt-controller; + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; =20 - #address-cells =3D <2>; - #size-cells =3D <2>; - ranges; + port@1 { + reg =3D <1>; =20 - gic_its: gic-its@17040000 { - compatible =3D "arm,gic-v3-its"; - reg =3D <0x0 0x17040000 0x0 0x40000>; + qdss_tpda_in1: endpoint { + remote-endpoint =3D <&spdm_tpdm_out>; + }; + }; + }; =20 - msi-controller; - #msi-cells =3D <1>; + out-ports { + port { + qdss_tpda_out: endpoint { + remote-endpoint =3D <&funnel0_in6>; + }; + }; }; }; =20 - watchdog@17600000 { - compatible =3D "qcom,kpss-wdt"; - reg =3D <0x0 0x17600000 0x0 0x1000>; - clocks =3D <&sleep_clk>; - interrupts =3D ; - }; + tpdm@1000f000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1000f000 0x0 0x1000>; =20 - pdp0_mbox: mailbox@17610000 { - compatible =3D "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; - reg =3D <0x0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>; - interrupts =3D ; - #mbox-cells =3D <1>; + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <32>; + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + spdm_tpdm_out: endpoint { + remote-endpoint =3D <&qdss_tpda_in1>; + }; + }; + }; }; =20 - timer@17810000 { - compatible =3D "arm,armv7-timer-mem"; - reg =3D <0x0 0x17810000 0x0 0x1000>; - #address-cells =3D <2>; - #size-cells =3D <2>; - ranges; + funnel@10041000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x10041000 0x0 0x1000>; =20 - frame@17811000 { - reg =3D <0x0 0x17811000 0x0 0x1000>, - <0x0 0x17812000 0x0 0x1000>; + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; =20 - interrupts =3D , - ; + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; =20 - frame-number =3D <0>; + port@0 { + reg =3D <0>; + + funnel0_in0: endpoint { + remote-endpoint =3D <&tn_ag_out>; + }; + }; + + port@6 { + reg =3D <6>; + + funnel0_in6: endpoint { + remote-endpoint =3D <&qdss_tpda_out>; + }; + }; + + port@7 { + reg =3D <7>; + + funnel0_in7: endpoint { + remote-endpoint =3D <&stm_out>; + }; + }; }; =20 - frame@17813000 { - reg =3D <0x0 0x17813000 0x0 0x1000>; + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint =3D <&aoss_funnel_in6>; + }; + }; + }; + }; =20 - interrupts =3D ; + tpdm@1102c000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1102c000 0x0 0x1000>; =20 - frame-number =3D <1>; + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; =20 - status =3D "disabled"; + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + gcc_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in36>; + }; + }; }; + }; =20 - frame@17815000 { - reg =3D <0x0 0x17815000 0x0 0x1000>; + cti@11161000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x11161000 0x0 0x1000>; =20 - interrupts =3D ; + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + }; =20 - frame-number =3D <2>; + cti@11162000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x11162000 0x0 0x1000>; =20 - status =3D "disabled"; + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + }; + + tpdm@11180000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11180000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-element-bits =3D <32>; + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + cdsp_tpdm_out: endpoint { + remote-endpoint =3D <&cdsp_tpda_in0>; + }; + }; }; + }; =20 - frame@17817000 { - reg =3D <0x0 0x17817000 0x0 0x1000>; + tpdm@11183000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11183000 0x0 0x1000>; =20 - interrupts =3D ; + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; =20 - frame-number =3D <3>; + qcom,cmb-element-bits =3D <32>; + qcom,cmb-msrs-num =3D <32>; + qcom,dsb-element-bits =3D <32>; + qcom,dsb-msrs-num =3D <32>; =20 - status =3D "disabled"; + out-ports { + port { + cdsp_cmsr_tpdm_out: endpoint { + remote-endpoint =3D <&cdsp_tpda_in3>; + }; + }; }; + }; =20 - frame@17819000 { - reg =3D <0x0 0x17819000 0x0 0x1000>; + tpdm@11184000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11184000 0x0 0x1000>; =20 - interrupts =3D ; + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; =20 - frame-number =3D <4>; + qcom,cmb-element-bits =3D <32>; + qcom,cmb-msrs-num =3D <32>; + qcom,dsb-element-bits =3D <32>; + qcom,dsb-msrs-num =3D <32>; =20 - status =3D "disabled"; + out-ports { + port { + cdsp_cmsr2_tpdm_out: endpoint { + remote-endpoint =3D <&cdsp_tpda_in4>; + }; + }; }; + }; =20 - frame@1781b000 { - reg =3D <0x0 0x1781b000 0x0 0x1000>; + tpdm@11185000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11185000 0x0 0x1000>; =20 - interrupts =3D ; + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; =20 - frame-number =3D <5>; + qcom,cmb-element-bits =3D <64>; + qcom,cmb-msrs-num =3D <32>; =20 - status =3D "disabled"; + out-ports { + port { + cdsp_dpm1_tpdm_out: endpoint { + remote-endpoint =3D <&cdsp_tpda_in5>; + }; + }; }; + }; =20 - frame@1781d000 { - reg =3D <0x0 0x1781d000 0x0 0x1000>; + tpdm@11186000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11186000 0x0 0x1000>; =20 - interrupts =3D ; + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; =20 - frame-number =3D <6>; + qcom,cmb-element-bits =3D <64>; + qcom,cmb-msrs-num =3D <32>; =20 - status =3D "disabled"; + out-ports { + port { + cdsp_dpm2_tpdm_out: endpoint { + remote-endpoint =3D <&cdsp_tpda_in6>; + }; + }; }; }; =20 - apps_rsc: rsc@18900000 { - compatible =3D "qcom,rpmh-rsc"; - label =3D "apps_rsc"; - reg =3D <0x0 0x18900000 0x0 0x10000>, + tpda@11188000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x0 0x11188000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + cdsp_tpda_in0: endpoint { + remote-endpoint =3D <&cdsp_tpdm_out>; + }; + }; + + port@1 { + reg =3D <1>; + + cdsp_tpda_in1: endpoint { + remote-endpoint =3D <&cdsp_llm_tpdm_out>; + }; + }; + + port@2 { + reg =3D <2>; + + cdsp_tpda_in2: endpoint { + remote-endpoint =3D <&cdsp_llm2_tpdm_out>; + }; + }; + + port@3 { + reg =3D <3>; + + cdsp_tpda_in3: endpoint { + remote-endpoint =3D <&cdsp_cmsr_tpdm_out>; + }; + }; + + port@4 { + reg =3D <4>; + + cdsp_tpda_in4: endpoint { + remote-endpoint =3D <&cdsp_cmsr2_tpdm_out>; + }; + }; + + port@5 { + reg =3D <5>; + + cdsp_tpda_in5: endpoint { + remote-endpoint =3D <&cdsp_dpm1_tpdm_out>; + }; + }; + + port@6 { + reg =3D <6>; + + cdsp_tpda_in6: endpoint { + remote-endpoint =3D <&cdsp_dpm2_tpdm_out>; + }; + }; + }; + + out-ports { + port { + cdsp_tpda_out: endpoint { + remote-endpoint =3D <&cdsp_funnel_in0>; + }; + }; + }; + }; + + funnel@11189000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x11189000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + cdsp_funnel_in0: endpoint { + remote-endpoint =3D <&cdsp_tpda_out>; + }; + }; + }; + + out-ports { + port { + cdsp_funnel_out: endpoint { + remote-endpoint =3D <&tn_ag_in53>; + }; + }; + }; + }; + + cti@11193000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x11193000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + }; + + cti@111ab000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x111ab000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + }; + + tpdm@111d0000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x111d0000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + qm_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in35>; + }; + }; + }; + }; + + tn@11200000 { + compatible =3D "qcom,coresight-tnoc", "arm,primecell"; + reg =3D <0x0 0x11200000 0x0 0x4200>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@6 { + reg =3D <6>; + + tn_ag_in6: endpoint { + remote-endpoint =3D <&mm_dsb_tpdm_out>; + }; + }; + + port@10 { + reg =3D <0x10>; + + tn_ag_in16: endpoint { + remote-endpoint =3D <&east_dsb_tpdm_out>; + }; + }; + + port@21 { + reg =3D <0x21>; + + tn_ag_in33: endpoint { + remote-endpoint =3D <&west_dsb_tpdm_out>; + }; + }; + + port@23 { + reg =3D <0x23>; + + tn_ag_in35: endpoint { + remote-endpoint =3D <&qm_tpdm_out>; + }; + }; + + port@24 { + reg =3D <0x24>; + + tn_ag_in36: endpoint { + remote-endpoint =3D <&gcc_tpdm_out>; + }; + }; + + port@32 { + reg =3D <0x32>; + + tn_ag_in50: endpoint { + remote-endpoint =3D <&pcie_rscc_tpda_out>; + }; + }; + + port@35 { + reg =3D <0x35>; + + tn_ag_in53: endpoint { + remote-endpoint =3D <&cdsp_funnel_out>; + }; + }; + + port@3f { + reg =3D <0x3f>; + + tn_ag_in63: endpoint { + remote-endpoint =3D <¢er_dsb_tpdm_out>; + }; + }; + + port@40 { + reg =3D <0x40>; + + tn_ag_in64: endpoint { + remote-endpoint =3D <&ipcc_cmb_tpdm_out>; + }; + }; + + port@41 { + reg =3D <0x41>; + + tn_ag_in65: endpoint { + remote-endpoint =3D <&qrng_tpdm_out>; + }; + }; + + port@42 { + reg =3D <0x42>; + + tn_ag_in66: endpoint { + remote-endpoint =3D <&pmu_tpdm_out>; + }; + }; + + port@43 { + reg =3D <0x43>; + + tn_ag_in67: endpoint { + remote-endpoint =3D <&rdpm_west_cmb0_tpdm_out>; + }; + }; + + port@44 { + reg =3D <0x44>; + + tn_ag_in68: endpoint { + remote-endpoint =3D <&rdpm_west_cmb1_tpdm_out>; + }; + }; + + port@45 { + reg =3D <0x45>; + + tn_ag_in69: endpoint { + remote-endpoint =3D <&rdpm_west_cmb2_tpdm_out>; + }; + }; + + port@4b { + reg =3D <0x4b>; + + tn_ag_in75: endpoint { + remote-endpoint =3D <&south_dsb2_tpdm_out>; + }; + }; + + port@52 { + reg =3D <0x52>; + + tn_ag_in82: endpoint { + remote-endpoint =3D <&south_dsb_tpdm_out>; + }; + }; + + port@53 { + reg =3D <0x53>; + + tn_ag_in83: endpoint { + remote-endpoint =3D <¢er_dsb1_tpdm_out>; + }; + }; + }; + + out-ports { + port { + tn_ag_out: endpoint { + remote-endpoint =3D <&funnel0_in0>; + }; + }; + }; + }; + + tpdm@11207000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11207000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + mm_dsb_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in6>; + }; + }; + }; + }; + + tpdm@1120b000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1120b000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + east_dsb_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in16>; + }; + }; + }; + }; + + tpdm@11213000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11213000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + west_dsb_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in33>; + }; + }; + }; + }; + + tpdm@11219000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11219000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + center_dsb_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in63>; + }; + }; + }; + }; + + tpdm@1121a000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1121a000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + ipcc_cmb_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in64>; + }; + }; + }; + }; + + tpdm@1121b000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1121b000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + qrng_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in65>; + }; + }; + }; + }; + + tpdm@1121c000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1121c000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + pmu_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in66>; + }; + }; + }; + }; + + tpdm@1121d000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1121d000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + rdpm_west_cmb0_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in67>; + }; + }; + }; + }; + + tpdm@1121e000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1121e000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + rdpm_west_cmb1_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in68>; + }; + }; + }; + }; + + tpdm@1121f000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x1121f000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + rdpm_west_cmb2_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in69>; + }; + }; + }; + }; + + tpdm@11220000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11220000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + center_dsb1_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in83>; + }; + }; + }; + }; + + tpdm@11224000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11224000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + south_dsb2_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in75>; + }; + }; + }; + }; + + tpdm@11228000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11228000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + south_dsb_tpdm_out: endpoint { + remote-endpoint =3D <&tn_ag_in82>; + }; + }; + }; + }; + + tpdm@11470000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11470000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <32>; + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + pcie_rscc_tpdm_out: endpoint { + remote-endpoint =3D <&pcie_rscc_tpda_in0>; + }; + }; + }; + }; + + tpda@11471000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x0 0x11471000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + pcie_rscc_tpda_in0: endpoint { + remote-endpoint =3D <&pcie_rscc_tpdm_out>; + }; + }; + }; + + out-ports { + port { + pcie_rscc_tpda_out: endpoint { + remote-endpoint =3D <&tn_ag_in50>; + }; + }; + }; + }; + + tpdm@11c03000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11c03000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + swao_prio4_tpdm_out: endpoint { + remote-endpoint =3D <&aoss_tpda_in4>; + }; + }; + }; + }; + + funnel@11c04000 { + compatible =3D "arm,coresight-dynamic-funnel", "arm,primecell"; + reg =3D <0x0 0x11c04000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@5 { + reg =3D <5>; + + aoss_funnel_in5: endpoint { + remote-endpoint =3D <&aoss_tpda_out>; + }; + }; + + port@6 { + reg =3D <6>; + + aoss_funnel_in6: endpoint { + remote-endpoint =3D <&funnel0_out>; + }; + }; + }; + + out-ports { + port { + aoss_funnel_out: endpoint { + remote-endpoint =3D <&etf0_in>; + }; + }; + }; + }; + + tmc_etf: tmc@11c05000 { + compatible =3D "arm,coresight-tmc", "arm,primecell"; + reg =3D <0x0 0x11c05000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + etf0_in: endpoint { + remote-endpoint =3D <&aoss_funnel_out>; + }; + }; + }; + + out-ports { + port { + etf0_out: endpoint { + remote-endpoint =3D <&swao_rep_in>; + }; + }; + }; + }; + + replicator@11c06000 { + compatible =3D "arm,coresight-dynamic-replicator", "arm,primecell"; + reg =3D <0x0 0x11c06000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + port { + swao_rep_in: endpoint { + remote-endpoint =3D <&etf0_out>; + }; + }; + }; + + out-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + + swao_rep_out1: endpoint { + remote-endpoint =3D <&eud_in>; + }; + }; + }; + }; + + tpda@11c08000 { + compatible =3D "qcom,coresight-tpda", "arm,primecell"; + reg =3D <0x0 0x11c08000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + aoss_tpda_in0: endpoint { + remote-endpoint =3D <&swao_prio0_tpdm_out>; + }; + }; + + port@1 { + reg =3D <1>; + + aoss_tpda_in1: endpoint { + remote-endpoint =3D <&swao_prio1_tpdm_out>; + }; + }; + + port@2 { + reg =3D <2>; + + aoss_tpda_in2: endpoint { + remote-endpoint =3D <&swao_prio2_tpdm_out>; + }; + }; + + port@3 { + reg =3D <3>; + + aoss_tpda_in3: endpoint { + remote-endpoint =3D <&swao_prio3_tpdm_out>; + }; + }; + + port@4 { + reg =3D <4>; + + aoss_tpda_in4: endpoint { + remote-endpoint =3D <&swao_prio4_tpdm_out>; + }; + }; + + port@5 { + reg =3D <5>; + + aoss_tpda_in5: endpoint { + remote-endpoint =3D <&swao_tpdm_out>; + }; + }; + }; + + out-ports { + port { + aoss_tpda_out: endpoint { + remote-endpoint =3D <&aoss_funnel_in5>; + }; + }; + }; + }; + + tpdm@11c09000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11c09000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + swao_prio0_tpdm_out: endpoint { + remote-endpoint =3D <&aoss_tpda_in0>; + }; + }; + }; + }; + + tpdm@11c0a000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11c0a000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + swao_prio1_tpdm_out: endpoint { + remote-endpoint =3D <&aoss_tpda_in1>; + }; + }; + }; + }; + + tpdm@11c0b000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11c0b000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + swao_prio2_tpdm_out: endpoint { + remote-endpoint =3D <&aoss_tpda_in2>; + }; + }; + }; + }; + + tpdm@11c0c000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11c0c000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,cmb-element-bits =3D <64>; + qcom,cmb-msrs-num =3D <32>; + + out-ports { + port { + swao_prio3_tpdm_out: endpoint { + remote-endpoint =3D <&aoss_tpda_in3>; + }; + }; + }; + }; + + tpdm@11c0d000 { + compatible =3D "qcom,coresight-tpdm", "arm,primecell"; + reg =3D <0x0 0x11c0d000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + + qcom,dsb-element-bits =3D <32>; + qcom,dsb-msrs-num =3D <32>; + + out-ports { + port { + swao_tpdm_out: endpoint { + remote-endpoint =3D <&aoss_tpda_in5>; + }; + }; + }; + }; + + cti@11c42000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x11c42000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + }; + + cti@11c4b000 { + compatible =3D "arm,coresight-cti", "arm,primecell"; + reg =3D <0x0 0x11c4b000 0x0 0x1000>; + + clocks =3D <&aoss_qmp>; + clock-names =3D "apb_pclk"; + }; + + apps_smmu: iommu@15000000 { + compatible =3D "qcom,glymur-smmu-500", + "qcom,smmu-500", + "arm,mmu-500"; + reg =3D <0x0 0x15000000 0x0 0x100000>; + + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + dma-coherent; + }; + + intc: interrupt-controller@17000000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17000000 0x0 0x10000>, + <0x0 0x17080000 0x0 0x480000>; + + interrupts =3D ; + + #interrupt-cells =3D <3>; + interrupt-controller; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gic_its: gic-its@17040000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x17040000 0x0 0x40000>; + + msi-controller; + #msi-cells =3D <1>; + }; + }; + + watchdog@17600000 { + compatible =3D "qcom,kpss-wdt"; + reg =3D <0x0 0x17600000 0x0 0x1000>; + clocks =3D <&sleep_clk>; + interrupts =3D ; + }; + + pdp0_mbox: mailbox@17610000 { + compatible =3D "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; + reg =3D <0x0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>; + interrupts =3D ; + #mbox-cells =3D <1>; + }; + + timer@17810000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x17810000 0x0 0x1000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + frame@17811000 { + reg =3D <0x0 0x17811000 0x0 0x1000>, + <0x0 0x17812000 0x0 0x1000>; + + interrupts =3D , + ; + + frame-number =3D <0>; + }; + + frame@17813000 { + reg =3D <0x0 0x17813000 0x0 0x1000>; + + interrupts =3D ; + + frame-number =3D <1>; + + status =3D "disabled"; + }; + + frame@17815000 { + reg =3D <0x0 0x17815000 0x0 0x1000>; + + interrupts =3D ; + + frame-number =3D <2>; + + status =3D "disabled"; + }; + + frame@17817000 { + reg =3D <0x0 0x17817000 0x0 0x1000>; + + interrupts =3D ; + + frame-number =3D <3>; + + status =3D "disabled"; + }; + + frame@17819000 { + reg =3D <0x0 0x17819000 0x0 0x1000>; + + interrupts =3D ; + + frame-number =3D <4>; + + status =3D "disabled"; + }; + + frame@1781b000 { + reg =3D <0x0 0x1781b000 0x0 0x1000>; + + interrupts =3D ; + + frame-number =3D <5>; + + status =3D "disabled"; + }; + + frame@1781d000 { + reg =3D <0x0 0x1781d000 0x0 0x1000>; + + interrupts =3D ; + + frame-number =3D <6>; + + status =3D "disabled"; + }; + }; + + apps_rsc: rsc@18900000 { + compatible =3D "qcom,rpmh-rsc"; + label =3D "apps_rsc"; + reg =3D <0x0 0x18900000 0x0 0x10000>, <0x0 0x18910000 0x0 0x10000>, <0x0 0x18920000 0x0 0x10000>; reg-names =3D "drv-0", @@ -5697,4 +6812,30 @@ gpuss-1-critical { }; }; }; + + tpdm-cdsp-llm { + compatible =3D "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + cdsp_llm_tpdm_out: endpoint { + remote-endpoint =3D <&cdsp_tpda_in1>; + }; + }; + }; + }; + + tpdm-cdsp-llm2 { + compatible =3D "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits =3D <32>; + + out-ports { + port { + cdsp_llm2_tpdm_out: endpoint { + remote-endpoint =3D <&cdsp_tpda_in2>; + }; + }; + }; + }; }; --- base-commit: 008d3547aae5bc86fac3eda317489169c3fda112 change-id: 20251229-add-coresight-nodes-for-glymur-955fb985756a prerequisite-change-id: 20251007-upstream_v3_glymur_introduction-5a105b5449= 3d:v3 prerequisite-patch-id: 2d0427a6e5a9310d8dd547eb3e2d9667ade54083 prerequisite-patch-id: adc6c3714b1636b0758d479b647389519e5199cb prerequisite-patch-id: a60d247607692a62f8f1ad53697101f1845337d9 prerequisite-patch-id: 178e4c849a063a1e945155b6e5765150137a718c Best regards, --=20 Jie Gan