From nobody Mon Feb 9 13:57:56 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EB3D26B760; Mon, 29 Dec 2025 07:53:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766994825; cv=none; b=FSCiUDwD4esGmC20g5YrmtXdYNWxhj4kt8ZNzz3kR5CSgR2HnGrS8Thc5iAMScXkwurZdfIAGPc4W1mOmy/+ZDXvCdmAVHcMggYjDutBQMxyuJaw83EJzxOFmZLQDlI9H2+FiN5q4/s0A1YY5WOdkiQFDjRlB+49sK4ysUJ9/5g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766994825; c=relaxed/simple; bh=ZNkfEevuyVwV5+M4jtEy0S7S+wFLmCUQeeKVHGakuW0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=j6aIFMpdlzP/6CuKQdjcvbB1qS3JVLi+TtEcKJpRejWV0P8WLiIb90g5SG1EUewt1vZFlC1YYc4nOZV1T8FZ2ajgd3YvAKdW/N+3iwmrvgoOL794lRnQ6DJw2jG8RG+DhmqSV18OENoJ7Fi2TP9QXxsZXXT8Cxpf7FKndD4NZB0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=Sfy8iO29; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="Sfy8iO29" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 5BT7rFuF5703580, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1766994796; bh=JSY3kPc9BxMPO94pp/MTCGXiyTXYh59MOs6zrpmI3Hw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=Sfy8iO29oSU8fXatE+qbSPENX3vs/dkYwnEmY2ZbYdE4Zih59ADhSxc/t1yNDymlk j3PGkrNGTU33w9XAzbyFZ9sar+/lUyZlmm+VN6268JuHZuNB1emFdqT7mBrBWBMSKZ op/bDeiInfwqIBvWagiablX1pyX3UpyhtBGY4J0xdtnLiC9yA4JH74rAyuLTUsaqTD x6/p0bdNxCT5RDM4Id1I5Q9D8D51GdNSfiXevbpmiTUQ8PWl1Khtw5ty5Y+UBvEpo0 GWq+gVcRmYX7F4pk/0AJ3KhILz/kmRoBJrBub2WGZ8Xi4JBsJtAhpttRj6zXG886O8 ysKC9SSL+r/Ng== Received: from mail.realtek.com (rtkexhmbs03.realtek.com.tw[10.21.1.53]) by rtits2.realtek.com.tw (8.15.2/3.21/5.94) with ESMTPS id 5BT7rFuF5703580 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 29 Dec 2025 15:53:15 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS03.realtek.com.tw (10.21.1.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 29 Dec 2025 15:53:16 +0800 Received: from RTKEXHMBS04.realtek.com.tw (10.21.1.54) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 29 Dec 2025 15:53:15 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 29 Dec 2025 15:53:15 +0800 From: Yu-Chun Lin To: , , , , , , , CC: , , , , , , Subject: [PATCH 7/9] clk: realtek: Add support for MMC-tuned PLL clocks Date: Mon, 29 Dec 2025 15:53:11 +0800 Message-ID: <20251229075313.27254-8-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251229075313.27254-1-eleanor.lin@realtek.com> References: <20251229075313.27254-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add clk_pll_mmc_ops for enable/disable, prepare, rate control, and status operations on MMC PLL clocks. Also add clk_pll_mmc_phase_ops to support phase get/set operations. Signed-off-by: Cheng-Yu Lee Signed-off-by: Jyan Chou Signed-off-by: Yu-Chun Lin --- MAINTAINERS | 8 + drivers/clk/realtek/Kconfig | 4 + drivers/clk/realtek/Makefile | 2 + drivers/clk/realtek/clk-pll-mmc.c | 410 ++++++++++++++++++++++++++++++ drivers/clk/realtek/clk-pll.h | 21 ++ 5 files changed, 445 insertions(+) create mode 100644 drivers/clk/realtek/clk-pll-mmc.c diff --git a/MAINTAINERS b/MAINTAINERS index 9cc78e867a4e..bc919a42c205 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21977,6 +21977,14 @@ S: Supported F: Documentation/devicetree/bindings/clock/realtek* F: include/dt-bindings/clock/realtek* =20 +REALTEK SOC PLL CLOCK FOR MMC SUPPORT +M: Cheng-Yu Lee +M: Jyan Chou +M: Yu-Chun Lin +L: linux-clk@vger.kernel.org +S: Supported +F: drivers/clk/realtek/clk-pll-mmc.c + REALTEK SPI-NAND M: Chris Packham S: Maintained diff --git a/drivers/clk/realtek/Kconfig b/drivers/clk/realtek/Kconfig index 8577dce93ba6..de462c2bb892 100644 --- a/drivers/clk/realtek/Kconfig +++ b/drivers/clk/realtek/Kconfig @@ -24,4 +24,8 @@ config RTK_CLK_COMMON This provides utility functions and data structures used by multiple Realtek clock implementations, and include integration with reset controllers where required. + +config RTK_CLK_PLL_MMC + bool + endif diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index b40dd5a26653..3d5c93e79dbd 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -8,3 +8,5 @@ clk-rtk-y +=3D clk-regmap-gate.o clk-rtk-y +=3D clk-regmap-mux.o clk-rtk-y +=3D freq_table.o clk-rtk-y +=3D reset.o + +clk-rtk-$(CONFIG_RTK_CLK_PLL_MMC) +=3D clk-pll-mmc.o diff --git a/drivers/clk/realtek/clk-pll-mmc.c b/drivers/clk/realtek/clk-pl= l-mmc.c new file mode 100644 index 000000000000..7beebf52b5bb --- /dev/null +++ b/drivers/clk/realtek/clk-pll-mmc.c @@ -0,0 +1,410 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#include "clk-pll.h" + +#define PLL_EMMC1_OFFSET 0x0 +#define PLL_EMMC2_OFFSET 0x4 +#define PLL_EMMC3_OFFSET 0x8 +#define PLL_EMMC4_OFFSET 0xc +#define PLL_SSC_DIG_EMMC1_OFFSET 0x0 +#define PLL_SSC_DIG_EMMC3_OFFSET 0xc +#define PLL_SSC_DIG_EMMC4_OFFSET 0x10 + +#define PLL_PHRT0_MASK BIT(1) +#define PLL_PHSEL_MASK GENMASK(4, 0) +#define PLL_SSCPLL_RS_MASK GENMASK(12, 10) +#define PLL_SSCPLL_ICP_MASK GENMASK(9, 5) +#define PLL_SSC_DIV_EXT_F_MASK GENMASK(25, 13) +#define PLL_PI_IBSELH_MASK GENMASK(28, 27) +#define PLL_SSC_DIV_N_MASK GENMASK(23, 16) +#define PLL_NCODE_SSC_EMMC_MASK GENMASK(20, 13) +#define PLL_FCODE_SSC_EMMC_MASK GENMASK(12, 0) +#define PLL_GRAN_EST_EM_MC_MASK GENMASK(20, 0) +#define PLL_EN_SSC_EMMC_MASK BIT(0) +#define PLL_FLAG_INITAL_EMMC_MASK BIT(1) + +#define PLL_PHRT0_SHIFT 1 +#define PLL_SSCPLL_RS_SHIFT 10 +#define PLL_SSCPLL_ICP_SHIFT 5 +#define PLL_SSC_DIV_EXT_F_SHIFT 13 +#define PLL_PI_IBSELH_SHIFT 27 +#define PLL_SSC_DIV_N_SHIFT 16 +#define PLL_NCODE_SSC_EMMC_SHIFT 13 +#define PLL_FLAG_INITAL_EMMC_SHIFT 8 + +#define CYCLE_DEGREES 360 +#define PHASE_STEPS 32 +#define PHASE_SCALE_FACTOR 1125 + +static inline int get_phrt0(struct clk_pll_mmc *clkm, u32 *val) +{ + u32 reg; + int ret; + + ret =3D regmap_read(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC1_OFFSET, = ®); + if (ret) + return ret; + + *val =3D (reg >> PLL_PHRT0_SHIFT) & PLL_PHRT0_MASK; + return 0; +} + +static inline int set_phrt0(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC1_OF= FSET, + PLL_PHRT0_MASK, val << PLL_PHRT0_SHIFT); +} + +static inline int get_phsel(struct clk_pll_mmc *clkm, int id, u32 *val) +{ + int ret; + u32 raw_val; + u32 sft =3D id ? 8 : 3; + + ret =3D regmap_read(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC1_OFFSET, = &raw_val); + if (ret) + return ret; + + *val =3D (raw_val >> sft) & PLL_PHSEL_MASK; + return 0; +} + +static inline int set_phsel(struct clk_pll_mmc *clkm, int id, u32 val) +{ + u32 sft =3D id ? 8 : 3; + + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC1_OF= FSET, + PLL_PHSEL_MASK << sft, val << sft); +} + +static inline int set_sscpll_rs(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC2_OF= FSET, + PLL_SSCPLL_RS_MASK, val << PLL_SSCPLL_RS_SHIFT); +} + +static inline int set_sscpll_icp(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC2_OF= FSET, + PLL_SSCPLL_ICP_MASK, val << PLL_SSCPLL_ICP_SHIFT); +} + +static inline int get_ssc_div_ext_f(struct clk_pll_mmc *clkm, u32 *val) +{ + u32 raw_val; + int ret; + + ret =3D regmap_read(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC2_OFFSET, = &raw_val); + if (ret) + return ret; + + *val =3D (raw_val & PLL_SSC_DIV_EXT_F_MASK) >> PLL_SSC_DIV_EXT_F_SHIFT; + return 0; +} + +static inline int set_ssc_div_ext_f(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC2_OF= FSET, + PLL_SSC_DIV_EXT_F_MASK, + val << PLL_SSC_DIV_EXT_F_SHIFT); +} + +static inline int set_pi_ibselh(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC2_OF= FSET, + PLL_PI_IBSELH_MASK, val << PLL_PI_IBSELH_SHIFT); +} + +static inline int set_ssc_div_n(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_update_bits(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC3_OF= FSET, + PLL_SSC_DIV_N_MASK, val << PLL_SSC_DIV_N_SHIFT); +} + +static inline int get_ssc_div_n(struct clk_pll_mmc *clkm, u32 *val) +{ + int ret; + u32 raw_val; + + ret =3D regmap_read(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC3_OFFSET, = &raw_val); + if (ret) + return ret; + + *val =3D (raw_val & PLL_SSC_DIV_N_MASK) >> PLL_SSC_DIV_N_SHIFT; + return 0; +} + +static inline int set_pow_ctl(struct clk_pll_mmc *clkm, u32 val) +{ + return regmap_write(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC4_OFFSET, = val); +} + +static inline int get_pow_ctl(struct clk_pll_mmc *clkm, u32 *val) +{ + int ret; + u32 raw_val; + + ret =3D regmap_read(clkm->clkr.regmap, clkm->pll_ofs + PLL_EMMC4_OFFSET, = &raw_val); + + *val =3D raw_val; + + return ret; +} + +static int clk_pll_mmc_phase_set_phase(struct clk_hw *hw, int degrees) +{ + struct clk_hw *hwp =3D clk_hw_get_parent(hw); + struct clk_pll_mmc *clkm; + int phase_id; + u32 val; + int ret; + + if (!hwp) + return -ENOENT; + + clkm =3D to_clk_pll_mmc(hwp); + phase_id =3D (hw - &clkm->phase0_hw) ? 1 : 0; + val =3D DIV_ROUND_CLOSEST(degrees * 100, PHASE_SCALE_FACTOR); + ret =3D set_phsel(clkm, phase_id, val); + if (ret) + return ret; + + usleep_range(10, 20); + return 0; +} + +static int clk_pll_mmc_phase_get_phase(struct clk_hw *hw) +{ + struct clk_hw *hwp; + struct clk_pll_mmc *clkm; + int phase_id; + int ret; + u32 val; + + hwp =3D clk_hw_get_parent(hw); + if (!hwp) + return -ENOENT; + + clkm =3D to_clk_pll_mmc(hwp); + phase_id =3D (hw - &clkm->phase0_hw) ? 1 : 0; + ret =3D get_phsel(clkm, phase_id, &val); + if (ret) + return ret; + + val =3D DIV_ROUND_CLOSEST(val * CYCLE_DEGREES, PHASE_STEPS); + + return val; +} + +const struct clk_ops clk_pll_mmc_phase_ops =3D { + .set_phase =3D clk_pll_mmc_phase_set_phase, + .get_phase =3D clk_pll_mmc_phase_get_phase, +}; +EXPORT_SYMBOL_GPL(clk_pll_mmc_phase_ops); + +static int clk_pll_mmc_prepare(struct clk_hw *hw) +{ + struct clk_pll_mmc *clkm =3D to_clk_pll_mmc(hw); + + return set_pow_ctl(clkm, 7); +} + +static void clk_pll_mmc_unprepare(struct clk_hw *hw) +{ + struct clk_pll_mmc *clkm =3D to_clk_pll_mmc(hw); + + set_pow_ctl(clkm, 0); +} + +static int clk_pll_mmc_is_prepared(struct clk_hw *hw) +{ + struct clk_pll_mmc *clkm =3D to_clk_pll_mmc(hw); + u32 val; + int ret; + + ret =3D get_pow_ctl(clkm, &val); + if (ret) + return 1; + + return val !=3D 0x0; +} + +static void clk_pll_mmc_unprepare_unused(struct clk_hw *hw) +{ + /* This PLL has no unprepare_unused action */ +} + +static int clk_pll_mmc_enable(struct clk_hw *hw) +{ + struct clk_pll_mmc *clkm =3D to_clk_pll_mmc(hw); + int ret; + + ret =3D set_phrt0(clkm, 1); + if (ret) + return ret; + + udelay(10); + return 0; +} + +static void clk_pll_mmc_disable(struct clk_hw *hw) +{ + struct clk_pll_mmc *clkm =3D to_clk_pll_mmc(hw); + + set_phrt0(clkm, 0); + udelay(10); +} + +static int clk_pll_mmc_is_enabled(struct clk_hw *hw) +{ + struct clk_pll_mmc *clkm =3D to_clk_pll_mmc(hw); + u32 val; + int ret; + + ret =3D get_phrt0(clkm, &val); + if (ret) + return 1; + + return val =3D=3D 0x1; +} + +static void clk_pll_mmc_disable_unused(struct clk_hw *hw) +{ + /* This PLL has no disable_unused action */ +} + +static unsigned long clk_pll_mmc_recalc_rate(struct clk_hw *hw, unsigned l= ong parent_rate) +{ + struct clk_pll_mmc *clkm =3D to_clk_pll_mmc(hw); + u32 val, ext_f; + int ret; + + ret =3D get_ssc_div_n(clkm, &val); + if (ret) + return ret; + + ret =3D get_ssc_div_ext_f(clkm, &ext_f); + if (ret) + return ret; + + return parent_rate / 4 * (val + 2) + (parent_rate / 4 * ext_f) / 8192; +} + +static int clk_pll_mmc_determine_rate(struct clk_hw *hw, struct clk_rate_r= equest *req) +{ + u32 val =3D DIV_ROUND_CLOSEST(req->rate * 4, req->best_parent_rate); + + return req->best_parent_rate * val / 4; +} + +static u32 eval_ssc_div_n(struct clk_pll_mmc *clkm, unsigned long rate) +{ + return 0x1b; +} + +static int clk_pll_mmc_set_rate(struct clk_hw *hw, unsigned long rate, uns= igned long parent_rate) +{ + struct clk_pll_mmc *clkm =3D to_clk_pll_mmc(hw); + u32 val =3D eval_ssc_div_n(clkm, rate); + int ret; + + ret =3D regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC1_OFFSET, + PLL_FLAG_INITAL_EMMC_MASK, 0x0 << PLL_FLAG_INITAL_EMMC_SHIFT); + if (ret) + return ret; + + ret =3D set_ssc_div_n(clkm, val); + if (ret) + return ret; + + ret =3D set_ssc_div_ext_f(clkm, 1517); + if (ret) + return ret; + + switch (val) { + case 31 ... 46: + ret |=3D set_pi_ibselh(clkm, 3); + ret |=3D set_sscpll_rs(clkm, 3); + ret |=3D set_sscpll_icp(clkm, 2); + break; + case 20 ... 30: + ret |=3D set_pi_ibselh(clkm, 2); + ret |=3D set_sscpll_rs(clkm, 3); + ret |=3D set_sscpll_icp(clkm, 1); + break; + case 10 ... 19: + ret |=3D set_pi_ibselh(clkm, 1); + ret |=3D set_sscpll_rs(clkm, 2); + ret |=3D set_sscpll_icp(clkm, 1); + break; + case 5 ... 9: + ret |=3D set_pi_ibselh(clkm, 0); + ret |=3D set_sscpll_rs(clkm, 2); + ret |=3D set_sscpll_icp(clkm, 0); + break; + } + if (ret) + return ret; + + ret =3D regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC3_OFFSET, + PLL_NCODE_SSC_EMMC_MASK, + 27 << PLL_NCODE_SSC_EMMC_SHIFT); + if (ret) + return ret; + + ret =3D regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC3_OFFSET, + PLL_FCODE_SSC_EMMC_MASK, 321); + if (ret) + return ret; + + ret =3D regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC4_OFFSET, + PLL_GRAN_EST_EM_MC_MASK, 5985); + if (ret) + return ret; + + ret =3D regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC1_OFFSET, + PLL_EN_SSC_EMMC_MASK, 0x1); + if (ret) + return ret; + + ret =3D regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC1_OFFSET, + PLL_EN_SSC_EMMC_MASK, 0x0); + if (ret) + return ret; + + ret =3D regmap_update_bits(clkm->clkr.regmap, + clkm->ssc_dig_ofs + PLL_SSC_DIG_EMMC1_OFFSET, + PLL_FLAG_INITAL_EMMC_MASK, + 0x1 << PLL_FLAG_INITAL_EMMC_SHIFT); + if (ret) + return ret; + + usleep_range(10, 20); + return 0; +} + +const struct clk_ops clk_pll_mmc_ops =3D { + .prepare =3D clk_pll_mmc_prepare, + .unprepare =3D clk_pll_mmc_unprepare, + .is_prepared =3D clk_pll_mmc_is_prepared, + .unprepare_unused =3D clk_pll_mmc_unprepare_unused, + .enable =3D clk_pll_mmc_enable, + .disable =3D clk_pll_mmc_disable, + .is_enabled =3D clk_pll_mmc_is_enabled, + .disable_unused =3D clk_pll_mmc_disable_unused, + .recalc_rate =3D clk_pll_mmc_recalc_rate, + .determine_rate =3D clk_pll_mmc_determine_rate, + .set_rate =3D clk_pll_mmc_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_pll_mmc_ops); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/realtek/clk-pll.h b/drivers/clk/realtek/clk-pll.h index c3e2e5ca641f..90c47279410b 100644 --- a/drivers/clk/realtek/clk-pll.h +++ b/drivers/clk/realtek/clk-pll.h @@ -44,4 +44,25 @@ static inline struct clk_pll *to_clk_pll(struct clk_hw *= hw) extern const struct clk_ops clk_pll_ops; extern const struct clk_ops clk_pll_ro_ops; =20 +struct clk_pll_mmc { + struct clk_regmap clkr; + int pll_ofs; + int ssc_dig_ofs; + struct clk_hw phase0_hw; + struct clk_hw phase1_hw; + u32 set_rate_val_53_97_set_ipc: 1; +}; + +#define __clk_pll_mmc_hw(_ptr) __clk_regmap_hw(&(_ptr)->clkr) + +static inline struct clk_pll_mmc *to_clk_pll_mmc(struct clk_hw *hw) +{ + struct clk_regmap *clkr =3D to_clk_regmap(hw); + + return container_of(clkr, struct clk_pll_mmc, clkr); +} + +extern const struct clk_ops clk_pll_mmc_ops; +extern const struct clk_ops clk_pll_mmc_phase_ops; + #endif /* __CLK_REALTEK_CLK_PLL_H */ --=20 2.34.1