From nobody Sat Feb 7 21:23:44 2026 Received: from out-171.mta0.migadu.com (out-171.mta0.migadu.com [91.218.175.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A626221577 for ; Mon, 29 Dec 2025 06:34:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766990060; cv=none; b=Wz70PrefL5rPfyqljX5Dub45Ir+pk2/R+5qOG7eZSkfHiDTR93oTOZ62ME4Q4NvE9xQSZ3jEi+5hw0tQsBX6wzKbpXCM2jcJgZwlCYDwf9k5wjheg5VaFskB5F6nFWQ0xv96V1LIO5rlH7x/O3YAslrct5uE2VTIbVmEat7PE54= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766990060; c=relaxed/simple; bh=Tu71z43R1/men9r6Uqy83l8nEqXDO/VCDH5sN+hrXKo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aqEDydQzjWFA0A0QnWcqDFdJdqYAZ0Z67GZZoddB11Ij538rA80MbghmKom4+If3JWPqUiunPTf9JDmfj9gh+GWHOExc9OOl83/rykSN4aqqo44eScY+7DpNT6IVwJW/Ld+/fFme0ny1piiaYg1SW99fz+QIaLmybJ7mtUXx53E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=UM/f04XI; arc=none smtp.client-ip=91.218.175.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="UM/f04XI" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1766990056; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=X2mug8qAnjz7RRf26MzSBJvjU5q9D1Z2KIWQRhOyl0w=; b=UM/f04XIEcHj/nQ3xeVIFIE+CJzJOWraM0wbRbFO5K0+Ja46CS5vR5DSx8O972A22X/iLB /3PKrk694py3260ZBhCiIYcGW8tH45AjWrK4GVG8eOdWIemwQDpkz4xETSQzEi52RUeigP LeqOVYl7YtpzYvUKAbLsi2PRdrA7YeY= From: George Guo To: hengqi.chen@gmail.com Cc: chenhuacai@kernel.org, dongtai.guo@linux.dev, guodongtai@kylinos.cn, kernel@xen0n.name, lianyangyang@kylinos.cn, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, r@hev.cc, xry111@xry111.site Subject: [PATCH loongarch-next 1/4] LoongArch: Add SCQ support detection Date: Mon, 29 Dec 2025 14:34:05 +0800 Message-ID: <20251229063408.34340-2-dongtai.guo@linux.dev> In-Reply-To: <20251229063408.34340-1-dongtai.guo@linux.dev> References: <20251229063408.34340-1-dongtai.guo@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" From: George Guo Check CPUCFG2_SCQ bit to determin if the CPU supports SCQ instrction. Co-developed-by: Yangyang Lian Signed-off-by: Yangyang Lian Signed-off-by: George Guo --- arch/loongarch/include/asm/cpu-features.h | 1 + arch/loongarch/include/asm/cpu.h | 2 ++ arch/loongarch/include/asm/loongarch.h | 1 + arch/loongarch/kernel/cpu-probe.c | 2 ++ arch/loongarch/kernel/proc.c | 1 + 5 files changed, 7 insertions(+) diff --git a/arch/loongarch/include/asm/cpu-features.h b/arch/loongarch/inc= lude/asm/cpu-features.h index 3745d991a99a..39c7fe64c3ef 100644 --- a/arch/loongarch/include/asm/cpu-features.h +++ b/arch/loongarch/include/asm/cpu-features.h @@ -67,5 +67,6 @@ #define cpu_has_msgint cpu_opt(LOONGARCH_CPU_MSGINT) #define cpu_has_avecint cpu_opt(LOONGARCH_CPU_AVECINT) #define cpu_has_redirectint cpu_opt(LOONGARCH_CPU_REDIRECTINT) +#define cpu_has_scq cpu_opt(LOONGARCH_CPU_SCQ) =20 #endif /* __ASM_CPU_FEATURES_H */ diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/include/asm/= cpu.h index f3efb00b6141..5531039027ec 100644 --- a/arch/loongarch/include/asm/cpu.h +++ b/arch/loongarch/include/asm/cpu.h @@ -125,6 +125,7 @@ static inline char *id_to_core_name(unsigned int id) #define CPU_FEATURE_MSGINT 29 /* CPU has MSG interrupt */ #define CPU_FEATURE_AVECINT 30 /* CPU has AVEC interrupt */ #define CPU_FEATURE_REDIRECTINT 31 /* CPU has interrupt remapping */ +#define CPU_FEATURE_SCQ 32 /* CPU has SC.Q instruction */ =20 #define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG) #define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM) @@ -158,5 +159,6 @@ static inline char *id_to_core_name(unsigned int id) #define LOONGARCH_CPU_MSGINT BIT_ULL(CPU_FEATURE_MSGINT) #define LOONGARCH_CPU_AVECINT BIT_ULL(CPU_FEATURE_AVECINT) #define LOONGARCH_CPU_REDIRECTINT BIT_ULL(CPU_FEATURE_REDIRECTINT) +#define LOONGARCH_CPU_SCQ BIT_ULL(CPU_FEATURE_SCQ) =20 #endif /* _ASM_CPU_H */ diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/includ= e/asm/loongarch.h index e6b8ff61c8cc..817cd90941d9 100644 --- a/arch/loongarch/include/asm/loongarch.h +++ b/arch/loongarch/include/asm/loongarch.h @@ -94,6 +94,7 @@ #define CPUCFG2_LSPW BIT(21) #define CPUCFG2_LAM BIT(22) #define CPUCFG2_PTW BIT(24) +#define CPUCFG2_SCQ BIT(30) =20 #define LOONGARCH_CPUCFG3 0x3 #define CPUCFG3_CCDMA BIT(0) diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-= probe.c index 08a227034042..382c472c6bfe 100644 --- a/arch/loongarch/kernel/cpu-probe.c +++ b/arch/loongarch/kernel/cpu-probe.c @@ -205,6 +205,8 @@ static void cpu_probe_common(struct cpuinfo_loongarch *= c) c->options |=3D LOONGARCH_CPU_PTW; elf_hwcap |=3D HWCAP_LOONGARCH_PTW; } + if (config & CPUCFG2_SCQ) + c->options |=3D LOONGARCH_CPU_SCQ; if (config & CPUCFG2_LSPW) { c->options |=3D LOONGARCH_CPU_LSPW; elf_hwcap |=3D HWCAP_LOONGARCH_LSPW; diff --git a/arch/loongarch/kernel/proc.c b/arch/loongarch/kernel/proc.c index a8800d20e11b..252fa1d03b85 100644 --- a/arch/loongarch/kernel/proc.c +++ b/arch/loongarch/kernel/proc.c @@ -75,6 +75,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) if (cpu_has_lbt_x86) seq_printf(m, " lbt_x86"); if (cpu_has_lbt_arm) seq_printf(m, " lbt_arm"); if (cpu_has_lbt_mips) seq_printf(m, " lbt_mips"); + if (cpu_has_scq) seq_printf(m, " scq"); seq_printf(m, "\n"); =20 seq_printf(m, "Hardware Watchpoint\t: %s", str_yes_no(cpu_has_watch)); --=20 2.49.0 From nobody Sat Feb 7 21:23:44 2026 Received: from out-173.mta0.migadu.com (out-173.mta0.migadu.com [91.218.175.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 889662D0603 for ; Mon, 29 Dec 2025 06:34:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766990062; cv=none; b=A6ek9WiqaZUsfsoViQbKAe54HJswUWHUIIowI8fL36vIX29U3LAGwAfOz+ZJ68CYdfp4o4ZqsYp6xE0eCifLYWxynf9okF29Lk4n6r7ttm4w9MUpHRl44VpOzKvhybqIcUb7bUo7+egqwi4KEaQoJzrMgh0AXEf/N6jc1P+XQrc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766990062; c=relaxed/simple; bh=P+qofRHgKI9mEvf/M2+uRxs0vPJHcW9djs3JSnJOuKU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=M3ENqbVR7USa8qSr5pBUidr+DlWOM2dh1ktj/nfKPh1ydonZGDXoV3HpmWkpsDz2s5tbCgTuRSN8VVZubIMu0aVu5QrQpjLQBSfJNv99JKSlSLDKhk0ocSFzTSi59Dee8iqRxJ2PNnVhFs9DLrkrL43SZMhBTgXIYGuXQ6URzW0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=foB+0N8C; arc=none smtp.client-ip=91.218.175.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="foB+0N8C" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1766990058; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9e1GeNzrkliZLlZL213Exbk9DDZDpepWNXJsRZoIj9M=; b=foB+0N8C+D/7YAJV4KSBB2eIaxqQZrJXHykBcuiCYbaj9itN8sCX2iACZztrxw43VdDhk7 jvi4KOYr1VJi96rTfB3BFpPdjnE60QYVe22nfvEZbKT6vX9MujUWd0jR3/CTEL4ixpo9Fk R5E/z6n37jIUfBpjYdOdZwuIeAsE6ng= From: George Guo To: hengqi.chen@gmail.com Cc: chenhuacai@kernel.org, dongtai.guo@linux.dev, guodongtai@kylinos.cn, kernel@xen0n.name, lianyangyang@kylinos.cn, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, r@hev.cc, xry111@xry111.site Subject: [PATCH loongarch-next 2/4] LoongArch: Add 128-bit atomic cmpxchg support Date: Mon, 29 Dec 2025 14:34:06 +0800 Message-ID: <20251229063408.34340-3-dongtai.guo@linux.dev> In-Reply-To: <20251229063408.34340-1-dongtai.guo@linux.dev> References: <20251229063408.34340-1-dongtai.guo@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" From: George Guo Implement 128-bit atomic compare-and-exchange using LoongArch's LL.D/SC.Q instructions. At the same time, fix BPF scheduler test failures (scx_central scx_qmap) caused by kmalloc_nolock_noprof returning NULL due to missing 128-bit atomics. The NULL returns led to -ENOMEM errors during scheduler initialization, causing test cases to fail. Verified by testing with the scx_qmap scheduler (located in tools/sched_ext/). Building with `make` and running ./tools/sched_ext/build/bin/scx_qmap. Signed-off-by: George Guo --- arch/loongarch/include/asm/cmpxchg.h | 47 ++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/loongarch/include/asm/cmpxchg.h b/arch/loongarch/include/= asm/cmpxchg.h index 0494c2ab553e..61ce6a0889f0 100644 --- a/arch/loongarch/include/asm/cmpxchg.h +++ b/arch/loongarch/include/asm/cmpxchg.h @@ -137,6 +137,44 @@ __arch_xchg(volatile void *ptr, unsigned long x, int s= ize) __ret; \ }) =20 +union __u128_halves { + u128 full; + struct { + u64 low; + u64 high; + }; +}; + +#define __cmpxchg128_asm(ptr, old, new) \ +({ \ + union __u128_halves __old, __new, __ret; \ + volatile u64 *__ptr =3D (volatile u64 *)(ptr); \ + \ + __old.full =3D (old); \ + __new.full =3D (new); \ + \ + __asm__ __volatile__( \ + "1: ll.d %0, %3 # 128-bit cmpxchg low \n" \ + __WEAK_LLSC_MB \ + " ld.d %1, %4 # 128-bit cmpxchg high \n" \ + " bne %0, %z5, 2f \n" \ + " bne %1, %z6, 2f \n" \ + " move $t0, %z7 \n" \ + " move $t1, %z8 \n" \ + " sc.q $t0, $t1, %2 \n" \ + " beqz $t0, 1b \n" \ + "2: \n" \ + __WEAK_LLSC_MB \ + : "=3D&r" (__ret.low), "=3D&r" (__ret.high) \ + : "r" (__ptr), \ + "ZC" (__ptr[0]), "m" (__ptr[1]), \ + "Jr" (__old.low), "Jr" (__old.high), \ + "Jr" (__new.low), "Jr" (__new.high) \ + : "t0", "t1", "memory"); \ + \ + __ret.full; \ +}) + static inline unsigned int __cmpxchg_small(volatile void *ptr, unsigned in= t old, unsigned int new, unsigned int size) { @@ -224,6 +262,15 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsig= ned long new, unsigned int __res; \ }) =20 +/* cmpxchg128 */ +#define system_has_cmpxchg128() 1 + +#define arch_cmpxchg128(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 16); \ + __cmpxchg128_asm(ptr, o, n); \ +}) + #ifdef CONFIG_64BIT #define arch_cmpxchg64_local(ptr, o, n) \ ({ \ --=20 2.49.0 From nobody Sat Feb 7 21:23:44 2026 Received: from out-188.mta0.migadu.com (out-188.mta0.migadu.com [91.218.175.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFA8A230BCB for ; Mon, 29 Dec 2025 06:34:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766990064; cv=none; b=K7Uz1R5/2eA9cOIMubzN9aZ6QAWFpBikkMn7FbDMDFvI8T4wzT/dKiuC4iD9Nfw7fGSdj/LYmowWrwbrvHfE1MhDpjRKVSNks7qWYvZ6NG6KrE2lHTFCTm4Yfc0ug6snWJOxZsMqbxXEkbzqi7mFK2xmtrt9fhLTh3ckhXRZyto= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766990064; c=relaxed/simple; bh=YcCyE4sWR+scLLWTbqdvzA1M9onDStyOkC3vO2tYI7E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XlNim7YsEcC5lKSZ5rbuJNC9/XjswF94t+BKk2B7LG5qA3feoNnZ36fTt5h+sbF7r0IpcL7oMbNoLRcbjXfzsVPfPHsSdQrkw5FFjt3ZjFvWRAFQa17CGiwmDjyKf9hC9pfZwKfpUFcODWnp7Pbfc4i3rlnEnYcU/L7k2ftAgdc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=lz9W7aIg; arc=none smtp.client-ip=91.218.175.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="lz9W7aIg" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1766990060; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jlN3ZPg4mJZbFMBP3Elnj5zSylaTyq0UW3iibF0yXu0=; b=lz9W7aIgqzuvCUashaA83rDnv8wKnu4V/vqzlC7S31fqimDSMoAhR2CCvPvCuEY49Mm09g FUeca0zStpJVMLwxb/FA492TDBo8prK0L4p5l3ouSYBzqHls2cCrM8fJxbuoM9eKvN13Ac 2guA1eKQQMGlEew5gA0p17gbL3ZQ13s= From: George Guo To: hengqi.chen@gmail.com Cc: chenhuacai@kernel.org, dongtai.guo@linux.dev, guodongtai@kylinos.cn, kernel@xen0n.name, lianyangyang@kylinos.cn, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, r@hev.cc, xry111@xry111.site Subject: [PATCH loongarch-next 3/4] LoongArch: Use spinlock to emulate 128-bit cmpxchg Date: Mon, 29 Dec 2025 14:34:07 +0800 Message-ID: <20251229063408.34340-4-dongtai.guo@linux.dev> In-Reply-To: <20251229063408.34340-1-dongtai.guo@linux.dev> References: <20251229063408.34340-1-dongtai.guo@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" From: George Guo For LoongArch CPUs lacking 128-bit atomic instruction(e.g., the SCQ instruction on 3A5000), provide a fallback implementation of __cmpxchg128 using a spinlock to emulate the atomic operation. Signed-off-by: George Guo --- arch/loongarch/include/asm/cmpxchg.h | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/loongarch/include/asm/cmpxchg.h b/arch/loongarch/include/= asm/cmpxchg.h index 61ce6a0889f0..ef793bcb7b25 100644 --- a/arch/loongarch/include/asm/cmpxchg.h +++ b/arch/loongarch/include/asm/cmpxchg.h @@ -8,6 +8,7 @@ #include #include #include +#include =20 #define __xchg_amo_asm(amswap_db, m, val) \ ({ \ @@ -175,6 +176,23 @@ union __u128_halves { __ret.full; \ }) =20 +#define __cmpxchg128_locked(ptr, old, new) \ +({ \ + u128 __ret; \ + static DEFINE_SPINLOCK(lock); \ + unsigned long flags; \ + \ + spin_lock_irqsave(&lock, flags); \ + \ + __ret =3D *(volatile u128 *)(ptr); \ + if (__ret =3D=3D (old)) \ + *(volatile u128 *)(ptr) =3D (new); \ + \ + spin_unlock_irqrestore(&lock, flags); \ + \ + __ret; \ +}) + static inline unsigned int __cmpxchg_small(volatile void *ptr, unsigned in= t old, unsigned int new, unsigned int size) { @@ -268,7 +286,8 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsign= ed long new, unsigned int #define arch_cmpxchg128(ptr, o, n) \ ({ \ BUILD_BUG_ON(sizeof(*(ptr)) !=3D 16); \ - __cmpxchg128_asm(ptr, o, n); \ + cpu_has_scq ? __cmpxchg128_asm(ptr, o, n) : \ + __cmpxchg128_locked(ptr, o, n); \ }) =20 #ifdef CONFIG_64BIT --=20 2.49.0 From nobody Sat Feb 7 21:23:44 2026 Received: from out-184.mta0.migadu.com (out-184.mta0.migadu.com [91.218.175.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 009BC2D23B6 for ; Mon, 29 Dec 2025 06:34:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766990066; cv=none; b=YBytfqf5LC4G4QhEzeEmuxHvAYg397wkB+GmBONV7sB69Fl9qbkIRbeJ05BwV9a9609p0G5521W8QLWTQVLMN1B/ebcsUg06hwNOsxqzLzBdJxluSh0QAjHBawaMZYKe+OFCrQA0hqd8xIXNnkDnqj9m2P8EGae41hzvzoQaHgU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766990066; c=relaxed/simple; bh=IxKRFQ2hIDuBInN9BpkikMOrYdxArX340pZEltaRdgg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eZ53Rr/SVRYJSntaspzA5hA6Cc5TlCwJqCbWlVrkgl5eQQ2DjxCS8dGqvG8YsbbZhb3G8FSYhAjemEC9BnQMgOEvfNCYP32UscVlEg6vfNsmD8Qgd80B7/I6EkDFfp7SmMvZX+rMLPVrKDBlgNNkrOkF3lXq6w+/s/S2Nwicku4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=wA+F8b8P; arc=none smtp.client-ip=91.218.175.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="wA+F8b8P" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1766990063; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0Busr31vYwHCmPhkYpBb+hPfItK01jR0m3O6Awmw6lU=; b=wA+F8b8PEXDDcOwbDBGqjPlLk/43Kdb9MyxsZoPzAj6IPt+s6sR/ALqTlD9Z3WbnSGuujq TxQNcYNYvtwfy/4yYzHSWKhIu5DwjlPNeXCRGDZ0w8SzeieMvtXOMDWpjD6CPDyfwj0nUJ dNQwgNhsGKRzUwRaR4yEMauWmgFSNBM= From: George Guo To: hengqi.chen@gmail.com Cc: chenhuacai@kernel.org, dongtai.guo@linux.dev, guodongtai@kylinos.cn, kernel@xen0n.name, lianyangyang@kylinos.cn, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, r@hev.cc, xry111@xry111.site Subject: [PATCH loongarch-next 4/4] LoongArch: Enable 128-bit atomics cmpxchg support Date: Mon, 29 Dec 2025 14:34:08 +0800 Message-ID: <20251229063408.34340-5-dongtai.guo@linux.dev> In-Reply-To: <20251229063408.34340-1-dongtai.guo@linux.dev> References: <20251229063408.34340-1-dongtai.guo@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" From: George Guo Add select HAVE_CMPXCHG_DOUBLE and select HAVE_ALIGNED_STRUCT_PAGE in Kconf= ig to enable 128-bit atomic cmpxchg support on LoongArch. Signed-off-by: George Guo --- arch/loongarch/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index 730f34214519..d4de823276d1 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -114,6 +114,7 @@ config LOONGARCH select GENERIC_TIME_VSYSCALL select GPIOLIB select HAS_IOPORT + select HAVE_ALIGNED_STRUCT_PAGE select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_BITREVERSE select HAVE_ARCH_JUMP_LABEL @@ -141,6 +142,7 @@ config LOONGARCH select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS select HAVE_DYNAMIC_FTRACE_WITH_REGS select HAVE_EBPF_JIT + select HAVE_CMPXCHG_DOUBLE select HAVE_EFFICIENT_UNALIGNED_ACCESS if !ARCH_STRICT_ALIGN select HAVE_EXIT_THREAD select HAVE_GENERIC_TIF_BITS --=20 2.49.0