From nobody Tue Feb 10 04:12:58 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97053275AEB for ; Mon, 29 Dec 2025 04:55:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766984158; cv=none; b=cX68mJ+TzW06tfXQtOU81nPUqX9E5Fc3QuOX6UVASjG+CGxUgDwS+KsJl43rdEYT2YH90I5Lf1/AoUdkmndRTgLe0U0OQtA/RnwjaTtMI2KhDOla6pm61mqBdr1582J+JyOCG67bAPmk0RNq5VJfb0PQHX4Ba3CKQ5wv03SkYNo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766984158; c=relaxed/simple; bh=5xsApeJnKutP/DbrLu9m78Eok6FpXw0T47Onyc9grx0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ctmK0Fs1GJZ1qnwRZA7PvWe7nmoSWf5l+AixVM6SJWBZMfuMLqHyxQbmdK6BBvowCnCPaJZqzFjUCnsZaU9vqdkzjM7lJX+SnOCbSlvNgm5KAAG5L8e6bgtPqCwM6WOk/BNp2uQIxeUfjwtWsX2Mgpfhd+EtwyUg9YU4wVOxeV0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=QQtWb0y5; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=JJYEQA1U; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="QQtWb0y5"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="JJYEQA1U" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BT0I0hY1528321 for ; Mon, 29 Dec 2025 04:55:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=sqaUgDVKZ6m 4wCTCNsu1hZ5yx1Nzly5OMpjbviE6Ct8=; b=QQtWb0y5GRMV2upvKejX5YFVhPS folry3j5gp5TVU7hK2borz4hSnzJLt+mOY3LNoHVtfCDS1fURhGFVsljV1n6KOUp wAa/SpfOL5Ysg1tTBk+nuQsvICsKmJSA5hFHamrrea6rCO+ZxOdaTuZtK6q9qBjo ELD+jm5PhWwo6FXzKYvSOn9nDyU1ek2btmo7ffw/vW/jm7Mo8US8FmHAdyjGSzHA pdItY6EQMzxLywQCwMhjoJh9bsN6tTgANJGmvGHG3sdAxZNgzgoaFHMgBJGxcTDf I/rd781vbpCkKMbLfCq86EE3et2qlw88dGiDVcCLq++TJ9WDZomQFsJHiDg== Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bavrj1tea-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 29 Dec 2025 04:55:55 +0000 (GMT) Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-7b90740249dso15740853b3a.0 for ; Sun, 28 Dec 2025 20:55:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1766984155; x=1767588955; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sqaUgDVKZ6m4wCTCNsu1hZ5yx1Nzly5OMpjbviE6Ct8=; b=JJYEQA1UNXhyjAGzVVoFhKTAI1o2uOISs9XiK5PfYBDAZg+GECKYHXWG73WrdtxWdl igzbUB7gv0Fx+P2KEXfbphYeHxzfKEot9jB9wVZ7YAUluAaFLfGifQSosEX5IVBR0h9b KqJSe9NURzvr0On61J4QeNPWTEFXYCGEr2ZP1+9kNRMerEIfVjYrO81BiSRdWnhYD8Pv iS4vufdjDPhAvNALHuMCpXRWD51/hZ1PVgfzUFqSKTWpxcOTbXoxarX04ikIpZmOBtYJ SfX9JNwrpMMNN2P7tayPKKHP5ytsmcyltt25bCH0MRWyiyQnW8dMOPvS6whsTaMkX7Nh Ad1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766984155; x=1767588955; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=sqaUgDVKZ6m4wCTCNsu1hZ5yx1Nzly5OMpjbviE6Ct8=; b=PUrFqXmx7USvPQ1FxKGc0Q1TLxuOrltQ1fWe/Y//XfgKkngB4xcFsykl1hr/S89uTw DxUxQS0mI9FR9ZJMleLBc8BT7HufSAUegow9fnOGuBPenmyb3eqH8u0OJ2Vtc0cKCg1z zDvzvOkT6JpgPufnb7wWu0/ToSd9VwGu92mERcvoRIS2N039m2S4xFggOIu6hXh2FaX0 hGEj6sfquek2k0f1fxtBb71mD3IJC367Ed9RIo8jQpcb/h7osdhpXProLQXwzPKiGHpo IYqSYpzJhHQZZjfs1+pBVYW/VERSPZMLksRDLNbN+Xs/HFIirlRPTbDEcqFcIQ/7cjOt 1VeQ== X-Forwarded-Encrypted: i=1; AJvYcCW74UASuqJQd9dYqkp/9udA2AmXt4VfQgmoXLC3kFn6M/KDL5B0T+MG+smRv1sePNz6vMwKMnLMXC1Rg6E=@vger.kernel.org X-Gm-Message-State: AOJu0Yws7ZakNb+0UrLckTU72RRhtjNBz2L/bDd4KfT/ht9v9kSMNH6S 2KmGAkY0SIhohZGmh6UIJ/TNwP7Wyj2JlGspVjsjjfetpXKsNJ/IS9VamNN774Z+p+eetUeuXIu i81hp/umhcYNJfawxnnaBtM03/Nle+NkCPENmN3ivu/YyG4EMwMkFsOnGK7ECxRydKf8= X-Gm-Gg: AY/fxX531bhYzVub9Hz3y6/eK/WeSe+Qy/AKVbn2F53gulbcGBZq7ayRS9EFj5iQjxK HlZPx3xInuaHgLS9RHGt03LqQmFrqjsKN2W0taUeUGGAp3nF3eAfzW9LCfmykKY5n6CC1DJXdhv pJXP3VBs9WWwPlOenQjEolpxMpLoPmyTyc0ra3Il00MoIUuiMuw8nG9vWy+1wVQSWOF9QJkBLCI PnDCyZCB6+riceMwLyRh8ebfM5ub7g1XJq6KzkSyYb/gT8bOGedxSEy3lP2dc7m4l250HVfm987 tt7qC66hgduaKOFGm8WVcNJWFmNaM7REx4VbMO+xd25HkR5HR6cOLbwssI3lnJm5K3/buATtBrQ CyNXDAWQH9kyNUmSsRNG2J2TOgG4yvHLDLTnUv9csqXM= X-Received: by 2002:a05:6a00:414b:b0:7e8:450c:61b6 with SMTP id d2e1a72fcca58-7ff6607cf9emr29366161b3a.38.1766984155063; Sun, 28 Dec 2025 20:55:55 -0800 (PST) X-Google-Smtp-Source: AGHT+IFVWAN3I3GIksPa2s4fGOxAGvD5QkitCuunHhLaFdnhBZjdXLBug8IwYxrjA4PPSx+ZGFqufA== X-Received: by 2002:a05:6a00:414b:b0:7e8:450c:61b6 with SMTP id d2e1a72fcca58-7ff6607cf9emr29366138b3a.38.1766984154479; Sun, 28 Dec 2025 20:55:54 -0800 (PST) Received: from hu-ptalari-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7ff7dfac29bsm27902080b3a.39.2025.12.28.20.55.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Dec 2025 20:55:54 -0800 (PST) From: Praveen Talari To: Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mukesh Kumar Savaliya , Viken Dadhaniya , Bjorn Andersson , Konrad Dybcio , Praveen Talari , linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alexey.klimov@linaro.org, krzk@kernel.org, bryan.odonoghue@linaro.org, jorge.ramirez@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com Cc: psodagud@quicinc.com, djaggi@quicinc.com, quic_msavaliy@quicinc.com, quic_vtanuku@quicinc.com, quic_arandive@quicinc.com, quic_shazhuss@quicinc.com, quic_cchiluve@quicinc.com Subject: [PATCH v2 08/12] i2c: qcom-geni: Isolate serial engine setup Date: Mon, 29 Dec 2025 10:24:42 +0530 Message-Id: <20251229045446.3227667-9-praveen.talari@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251229045446.3227667-1-praveen.talari@oss.qualcomm.com> References: <20251229045446.3227667-1-praveen.talari@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 8iuBSBwmBgO9BENAr8T3SUqbl989b7fq X-Proofpoint-GUID: 8iuBSBwmBgO9BENAr8T3SUqbl989b7fq X-Authority-Analysis: v=2.4 cv=coiWUl4i c=1 sm=1 tr=0 ts=695209db cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=6GPvvr__t7aM35KwLhsA:9 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjI5MDA0MiBTYWx0ZWRfXwgdj+20mwinc AN+CYH0AHSCFeR43GQUv32/y4IwQDlMyMKjuPz/rRnFizA1WC+locZQMoxbjlVukpiOImR1ykB+ iCh3Ljv+U27gs+b6Yo7i6I6fWUzZT5Y71Z+lC1xeDE4Un/WrU13fZjfqwsXbCxuCkUHakWhzZxh qR4HUgnVsa64qXbriAktqCUl6uDcUQgR4QAqU0gL6wbuSY36NqcrZngB2fsEyrlrEMn8bNung4T AoLHKQFsy9Kk6IUQo3P94d+gIvPqWvJH5Zg8Mpjh9HNuRD8FefPQkCCUIujAuR0HExF3bj9wyt+ txC9HqY0dzVvxVD2Tv1XMP2S6LVRLJOIQFxd2vFczI0QQJSc9nPJPk9vYqsNr/DAgcObbD5vL7m pP6Z3DFMDMUL6X/ip3xX2AYlTFlSL8vugsT81eL1fvxjPZduIjOQWLjxlReULCm/puc6Yrx6G0j KFZYRmplFsv7KD6K+cw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-29_01,2025-12-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 malwarescore=0 phishscore=0 adultscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512290042 Content-Type: text/plain; charset="utf-8" Moving the serial engine setup to geni_i2c_init() API for a cleaner probe function and utilizes the PM runtime API to control resources instead of direct clock-related APIs for better resource management. Enables reusability of the serial engine initialization like hibernation and deep sleep features where hardware context is lost. Signed-off-by: Praveen Talari --- v1->v2: Bjorn: - Updated commit text. --- drivers/i2c/busses/i2c-qcom-geni.c | 154 ++++++++++++++--------------- 1 file changed, 73 insertions(+), 81 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qc= om-geni.c index 3a04016db2c3..58c32ffbd150 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -976,10 +976,75 @@ static int setup_gpi_dma(struct geni_i2c_dev *gi2c) return ret; } =20 +static int geni_i2c_init(struct geni_i2c_dev *gi2c) +{ + const struct geni_i2c_desc *desc =3D NULL; + u32 proto, tx_depth; + bool fifo_disable; + int ret; + + ret =3D pm_runtime_resume_and_get(gi2c->se.dev); + if (ret < 0) { + dev_err(gi2c->se.dev, "error turning on device :%d\n", ret); + return ret; + } + + proto =3D geni_se_read_proto(&gi2c->se); + if (proto =3D=3D GENI_SE_INVALID_PROTO) { + ret =3D geni_load_se_firmware(&gi2c->se, GENI_SE_I2C); + if (ret) { + dev_err_probe(gi2c->se.dev, ret, "i2c firmware load failed ret: %d\n", = ret); + goto err; + } + } else if (proto !=3D GENI_SE_I2C) { + ret =3D dev_err_probe(gi2c->se.dev, -ENXIO, "Invalid proto %d\n", proto); + goto err; + } + + desc =3D device_get_match_data(gi2c->se.dev); + if (desc && desc->no_dma_support) + fifo_disable =3D false; + else + fifo_disable =3D readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIF= O_IF_DISABLE; + + if (fifo_disable) { + /* FIFO is disabled, so we can only use GPI DMA */ + gi2c->gpi_mode =3D true; + ret =3D setup_gpi_dma(gi2c); + if (ret) + goto err; + + dev_dbg(gi2c->se.dev, "Using GPI DMA mode for I2C\n"); + } else { + gi2c->gpi_mode =3D false; + tx_depth =3D geni_se_get_tx_fifo_depth(&gi2c->se); + + /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */ + if (!tx_depth && desc) + tx_depth =3D desc->tx_fifo_depth; + + if (!tx_depth) { + ret =3D dev_err_probe(gi2c->se.dev, -EINVAL, + "Invalid TX FIFO depth\n"); + goto err; + } + + gi2c->tx_wm =3D tx_depth - 1; + geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth); + geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, + PACKING_BYTES_PW, true, true, true); + + dev_dbg(gi2c->se.dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth); + } + +err: + pm_runtime_put(gi2c->se.dev); + return ret; +} + static int geni_i2c_probe(struct platform_device *pdev) { struct geni_i2c_dev *gi2c; - u32 proto, tx_depth, fifo_disable; int ret; struct device *dev =3D &pdev->dev; const struct geni_i2c_desc *desc =3D NULL; @@ -1059,100 +1124,27 @@ static int geni_i2c_probe(struct platform_device *= pdev) if (ret) return ret; =20 - ret =3D clk_prepare_enable(gi2c->core_clk); - if (ret) - return ret; - - ret =3D geni_se_resources_on(&gi2c->se); - if (ret) { - dev_err_probe(dev, ret, "Error turning on resources\n"); - goto err_clk; - } - proto =3D geni_se_read_proto(&gi2c->se); - if (proto =3D=3D GENI_SE_INVALID_PROTO) { - ret =3D geni_load_se_firmware(&gi2c->se, GENI_SE_I2C); - if (ret) { - dev_err_probe(dev, ret, "i2c firmware load failed ret: %d\n", ret); - goto err_resources; - } - } else if (proto !=3D GENI_SE_I2C) { - ret =3D dev_err_probe(dev, -ENXIO, "Invalid proto %d\n", proto); - goto err_resources; - } - - if (desc && desc->no_dma_support) - fifo_disable =3D false; - else - fifo_disable =3D readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIF= O_IF_DISABLE; - - if (fifo_disable) { - /* FIFO is disabled, so we can only use GPI DMA */ - gi2c->gpi_mode =3D true; - ret =3D setup_gpi_dma(gi2c); - if (ret) - goto err_resources; - - dev_dbg(dev, "Using GPI DMA mode for I2C\n"); - } else { - gi2c->gpi_mode =3D false; - tx_depth =3D geni_se_get_tx_fifo_depth(&gi2c->se); - - /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */ - if (!tx_depth && desc) - tx_depth =3D desc->tx_fifo_depth; - - if (!tx_depth) { - ret =3D dev_err_probe(dev, -EINVAL, - "Invalid TX FIFO depth\n"); - goto err_resources; - } - - gi2c->tx_wm =3D tx_depth - 1; - geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth); - geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, - PACKING_BYTES_PW, true, true, true); - - dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth); - } - - clk_disable_unprepare(gi2c->core_clk); - ret =3D geni_se_resources_off(&gi2c->se); - if (ret) { - dev_err_probe(dev, ret, "Error turning off resources\n"); - goto err_dma; - } - - ret =3D geni_icc_disable(&gi2c->se); - if (ret) - goto err_dma; - gi2c->suspended =3D 1; pm_runtime_set_suspended(gi2c->se.dev); pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY); pm_runtime_use_autosuspend(gi2c->se.dev); pm_runtime_enable(gi2c->se.dev); =20 + ret =3D geni_i2c_init(gi2c); + if (ret < 0) { + pm_runtime_disable(gi2c->se.dev); + return ret; + } + ret =3D i2c_add_adapter(&gi2c->adap); if (ret) { dev_err_probe(dev, ret, "Error adding i2c adapter\n"); pm_runtime_disable(gi2c->se.dev); - goto err_dma; + return ret; } =20 dev_dbg(dev, "Geni-I2C adaptor successfully added\n"); =20 - return ret; - -err_resources: - geni_se_resources_off(&gi2c->se); -err_clk: - clk_disable_unprepare(gi2c->core_clk); - - return ret; - -err_dma: - release_gpi_dma(gi2c); - return ret; } =20 --=20 2.34.1