From nobody Tue Feb 10 20:28:35 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85F242222B7 for ; Mon, 29 Dec 2025 04:55:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766984144; cv=none; b=klOFI6YOFFcr6mdw7fcNCFXbOv/A15LCa9xIL7XT8goaXfhG5Z/WwnMjcNtTEVmDPjOyQ753KNrygEk0HgqoX567bXA5L60jetLz5GdXBh+MrRESUUjMSYwHEuvThXrHThAHOJoH5rhuHkcX03f9ltTIDkvlOPv2yTuZCAjzeac= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766984144; c=relaxed/simple; bh=zfRE6HDH/oF9kt+zrOv76BV+vG94brTWdHbAGi6F1EA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TNKYAiC2AkU1MqbT98SCSfLl5VQKTEIYt3hBQZW2fwJp7UUZLjIL8fP0NmQ9UimI6tAWTHu46UM6NM1FJfeWLytTFLnuTB6yBjdfzQ5KqmISzM/iOC+3xxpZf4tArEnM3aDQmmN9uOZgsIi+0+DDdCOMomy0kbdXpNX/wqPc/EQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=GhPQuK3a; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=Q4iBG3CX; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="GhPQuK3a"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="Q4iBG3CX" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5BSN8jdU4073743 for ; Mon, 29 Dec 2025 04:55:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=9JJcvoCC/Az K5BxMcEfo4IlZ7RecYF5sBRU9NuOJgNs=; b=GhPQuK3aTQFsr2DpsqQhLEK/daO bu2RzLTXw3ad/z9ztV9xYW8LaJ2zFfaVUWyCtWAL+hi47OWFYSFJeNK5CUoKyz6j G0ybgksHwwjAtrmF7eQ5HroaabF8fO352itH8NUki/hNFgUmZgfA2YyDQ1E/vO5x xWMZr6Y43C/XiH655LHjPk1/ghboOW1qQ+ElvhsoiooS5YymEtJjTSu7Q0segx1I M0vYCOoEPn5ELEJT5i3NHzkjoQVZavrlBZB5rnm4xRbUf9TUeg/zpviic6IxPbON PcPGP2sz4YZgRU2cnjp+xBCR4McAIF9YirUHfTwaHTDlv/WjgvQr+PyG+lA== Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ba87buc6d-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 29 Dec 2025 04:55:41 +0000 (GMT) Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-7b80de683efso16708646b3a.3 for ; Sun, 28 Dec 2025 20:55:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1766984141; x=1767588941; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9JJcvoCC/AzK5BxMcEfo4IlZ7RecYF5sBRU9NuOJgNs=; b=Q4iBG3CXLcLcjjqX/a32mfUqKcLL7PCVTvE5dFUayNT89yug+hVFpYfsPxqR82V9NV E5zOUkitdNELpxEn0sEvlY9q4nvPThex8VXWEhcoRUAkefV4u2amWjSJalQekM6Gouq7 FJBhWlnJNpAtGKFahpW84s119W4XMwYsUR6+DiJF3I4b4R6es85yicF/juTdL3XKjMje RaGdIR386dhkTjfvusTIFrsVTLwyrsUh9Cp8+RpbfU0GJJL/YhBRXNrEKO7dyHURujhr XeN7vZSGIl9uLupoFqI30JI1oJMPhMVEzMnnyJ7k5uwMcVN6z90pyITVSkY4HKrQEhZC ettg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1766984141; x=1767588941; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=9JJcvoCC/AzK5BxMcEfo4IlZ7RecYF5sBRU9NuOJgNs=; b=Ap30kTSh090P58t2L2ftHk95co7IkOCQx7dBJ2ajI5nsI4P1Mxt5m3lO2VQOoTDt3n VTWf2lw/mskOdalwevO5RLSzirZUm/ZD3ap+l8GJGAV9ZKPc2WX0NfXKHivXEu+UTYHN oUctNuZN27R1F5Q+Z6dX5bs/1RX9sV2QYNdO88JYW+hHetxCgELg8aMalKdmyrr1zZ2M nMCyGhVxDe9Y3nhCNoS2by+O/sKvv1rZI8g28cIsrfvRASS5Y0Kkfe0aQ7+SleAUGHs+ NZIZ1esO6iyNV0OI6kWmzl5tPphjxUzXTc4KN/9ilqBPoU7THoApr/twdlvXXNHCD+jf VixQ== X-Forwarded-Encrypted: i=1; AJvYcCXz8NyabjGThwoWNE4Wm8LXnSpoNSw6FH2zsewrGWw0Jz3Ic8r63tnvSKQMNAA2cN6pyyI7mhfTJU5r28g=@vger.kernel.org X-Gm-Message-State: AOJu0YxjBBC5SpZ7Dus+OsFzxeA21ifvXqG4QAUJNUkm8G/KYdNTkXzI LYvV0TwYrrD/qWzHi70ma3FsTAYDjZ6KqHcA7/21c2AUFlUus1Xe3MD/iijrqv8B2/+vmqvS29y 9jJ7e22e7Dl3ClVoD1m0VtKFWdnmOaBXhjOLtLQiDiJOTmCXRUxnMEq1c/Z1seYI+I84= X-Gm-Gg: AY/fxX7Qvp4aIwFOhOOIm9CTF26VMis7/nkeZCy2BNjl2d0cSMWZXFNYgYMtzCyKsQx zq2K3puT2NtsNEJy1SkJomQHVDR7wpN60mDdPr2yTHTu88s5N2u+AEIAHkQ3ka9Sg2Icss5jY4w 9Yldm8bDaaGlkPRXz22y3XHnhBKqPxdyQ4zyO0W7BuStPPI3E7rzpP0cpIhgfaB8v3FiJghDNSG KyVoWMLGIf/VEWY8vund4Z/dSrT/KJAW5S9/KkD1WjwPv9wNtTQoSttKdMqMWCj7q66lawHceEk lTmwJhqUiD4Y9zNxs46vo8W6x3Q2znwniZiWrs9GqM5wiJYFc2a0Cu0aJEsp28PRjh9p8KqeI7c y36LCJciF5FDzA+xIAlOq6rinmc/wjsMw6R4ZrImbnts= X-Received: by 2002:a05:6a00:4219:b0:7f1:4c9c:782a with SMTP id d2e1a72fcca58-7ff648ee056mr25255697b3a.26.1766984140850; Sun, 28 Dec 2025 20:55:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IEXCTnJjfarrI9o6MPsZS7rS2u30bcKXIYNYtBf38hhzg8nPONoGbVH/4VzgJrLZa5tNpi19A== X-Received: by 2002:a05:6a00:4219:b0:7f1:4c9c:782a with SMTP id d2e1a72fcca58-7ff648ee056mr25255678b3a.26.1766984140294; Sun, 28 Dec 2025 20:55:40 -0800 (PST) Received: from hu-ptalari-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7ff7dfac29bsm27902080b3a.39.2025.12.28.20.55.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Dec 2025 20:55:39 -0800 (PST) From: Praveen Talari To: Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mukesh Kumar Savaliya , Viken Dadhaniya , Bjorn Andersson , Konrad Dybcio , Praveen Talari , linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alexey.klimov@linaro.org, krzk@kernel.org, bryan.odonoghue@linaro.org, jorge.ramirez@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com Cc: psodagud@quicinc.com, djaggi@quicinc.com, quic_msavaliy@quicinc.com, quic_vtanuku@quicinc.com, quic_arandive@quicinc.com, quic_shazhuss@quicinc.com, quic_cchiluve@quicinc.com Subject: [PATCH v2 06/12] soc: qcom: geni-se: Introduce helper APIs for performance control Date: Mon, 29 Dec 2025 10:24:40 +0530 Message-Id: <20251229045446.3227667-7-praveen.talari@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251229045446.3227667-1-praveen.talari@oss.qualcomm.com> References: <20251229045446.3227667-1-praveen.talari@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: tqr-jnYoYVCiuoaaoTSE-zNKT8BehZeF X-Proofpoint-GUID: tqr-jnYoYVCiuoaaoTSE-zNKT8BehZeF X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjI5MDA0MiBTYWx0ZWRfX2tfVVYUSuSzU hiW/wwUX2Fw7IpEOoBjK+XDmo6dvMRItaJ0bE0o1i2Q2gjsnUfDCo0DqkBQkORj6CAB6gjGVTRA HPoOGARY/scTRfH6J04D9b6qj4sOE1x4Lt9dns+hfb/w6V0q8xN4IW36uIH9Yhb6+gbOYff/vSW Br62RK41RZ5pxgLUZs19pF3Dcu6D9t1i26t44ngRdbXwo43JvW9moBRiQvohHckwWQNNpTS8R+w b1zabh3tNCRq1GvImTFuoUAVUDsqqmdP8XJD3139MxL7fbmqXit5RfNuCtUmAx/TgI/oTLEaYJ+ mqgU6SAKOzG1aHdxmQ3bBNTPKXYILu31WH7YOMG0rk737L8obxkcLmLmfVDG69GG8DrV4lgKUkZ QNvwX/kkohZh1Yxb9BrOyNXv//1b5PKJq1CpiV/lsY4qf4RsviVE26jmMtDJoUPA87cDF5H+lNB 0MmNE5fiweQWBGCjFnA== X-Authority-Analysis: v=2.4 cv=do7Wylg4 c=1 sm=1 tr=0 ts=695209cd cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=NwCh5GMA9Nt760FYQHkA:9 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-29_01,2025-12-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 spamscore=0 suspectscore=0 phishscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512290042 Content-Type: text/plain; charset="utf-8" The GENI Serial Engine (SE) drivers (I2C, SPI, and SERIAL) currently manage performance levels and operating points directly. This resulting in code duplication across drivers. such as configuring a specific level or find and apply an OPP based on a clock frequency. Introduce two new helper APIs, geni_se_set_perf_level() and geni_se_set_perf_opp(), addresses this issue by providing a streamlined method for the GENI Serial Engine (SE) drivers to find and set the OPP based on the desired performance level, thereby eliminating redundancy. Signed-off-by: Praveen Talari --- drivers/soc/qcom/qcom-geni-se.c | 50 ++++++++++++++++++++++++++++++++ include/linux/soc/qcom/geni-se.h | 4 +++ 2 files changed, 54 insertions(+) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-s= e.c index decf7cf5172e..fd63cc6a7faf 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -282,6 +282,12 @@ struct se_fw_hdr { #define geni_setbits32(_addr, _v) writel(readl(_addr) | (_v), _addr) #define geni_clrbits32(_addr, _v) writel(readl(_addr) & ~(_v), _addr) =20 +enum domain_idx { + DOMAIN_IDX_POWER, + DOMAIN_IDX_PERF, + DOMAIN_IDX_MAX +}; + /** * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version * @se: Pointer to the corresponding serial engine. @@ -1091,6 +1097,50 @@ int geni_se_resources_activate(struct geni_se *se) return ret; } =20 +/** + * geni_se_set_perf_level() - Set performance level for GENI SE. + * @se: Pointer to the struct geni_se instance. + * @level: The desired performance level. + * + * Sets the performance level by directly calling dev_pm_opp_set_level + * on the performance device associated with the SE. + * + * Return: 0 on success, or a negative error code on failure. + */ +int geni_se_set_perf_level(struct geni_se *se, unsigned long level) +{ + return dev_pm_opp_set_level(se->pd_list->pd_devs[DOMAIN_IDX_PERF], level); +} +EXPORT_SYMBOL_GPL(geni_se_set_perf_level); + +/** + * geni_se_set_perf_opp() - Set performance OPP for GENI SE by frequency. + * @se: Pointer to the struct geni_se instance. + * @clk_freq: The requested clock frequency. + * + * Finds the nearest operating performance point (OPP) for the given + * clock frequency and applies it to the SE's performance device. + * + * Return: 0 on success, or a negative error code on failure. + */ +int geni_se_set_perf_opp(struct geni_se *se, unsigned long clk_freq) +{ + struct device *perf_dev =3D se->pd_list->pd_devs[DOMAIN_IDX_PERF]; + struct dev_pm_opp *opp; + int ret; + + opp =3D dev_pm_opp_find_freq_floor(perf_dev, &clk_freq); + if (IS_ERR(opp)) { + dev_err(se->dev, "failed to find opp for freq %lu\n", clk_freq); + return PTR_ERR(opp); + } + + ret =3D dev_pm_opp_set_opp(perf_dev, opp); + dev_pm_opp_put(opp); + return ret; +} +EXPORT_SYMBOL_GPL(geni_se_set_perf_opp); + /** * geni_se_domain_attach() - Attach power domains to a GENI SE device. * @se: Pointer to the geni_se structure representing the GENI SE device. diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni= -se.h index 5f75159c5531..c5e6ab85df09 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -550,5 +550,9 @@ int geni_se_resources_deactivate(struct geni_se *se); int geni_load_se_firmware(struct geni_se *se, enum geni_se_protocol_type p= rotocol); =20 int geni_se_domain_attach(struct geni_se *se); + +int geni_se_set_perf_level(struct geni_se *se, unsigned long level); + +int geni_se_set_perf_opp(struct geni_se *se, unsigned long clk_freq); #endif #endif --=20 2.34.1